c_can.c revision 33f8100977693fa09c2a32b1ca6dbf4d6eabdd0c
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37 38#include <linux/can.h> 39#include <linux/can/dev.h> 40#include <linux/can/error.h> 41 42#include "c_can.h" 43 44/* Number of interface registers */ 45#define IF_ENUM_REG_LEN 11 46#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 47 48/* control register */ 49#define CONTROL_TEST BIT(7) 50#define CONTROL_CCE BIT(6) 51#define CONTROL_DISABLE_AR BIT(5) 52#define CONTROL_ENABLE_AR (0 << 5) 53#define CONTROL_EIE BIT(3) 54#define CONTROL_SIE BIT(2) 55#define CONTROL_IE BIT(1) 56#define CONTROL_INIT BIT(0) 57 58/* test register */ 59#define TEST_RX BIT(7) 60#define TEST_TX1 BIT(6) 61#define TEST_TX2 BIT(5) 62#define TEST_LBACK BIT(4) 63#define TEST_SILENT BIT(3) 64#define TEST_BASIC BIT(2) 65 66/* status register */ 67#define STATUS_BOFF BIT(7) 68#define STATUS_EWARN BIT(6) 69#define STATUS_EPASS BIT(5) 70#define STATUS_RXOK BIT(4) 71#define STATUS_TXOK BIT(3) 72 73/* error counter register */ 74#define ERR_CNT_TEC_MASK 0xff 75#define ERR_CNT_TEC_SHIFT 0 76#define ERR_CNT_REC_SHIFT 8 77#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 78#define ERR_CNT_RP_SHIFT 15 79#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 80 81/* bit-timing register */ 82#define BTR_BRP_MASK 0x3f 83#define BTR_BRP_SHIFT 0 84#define BTR_SJW_SHIFT 6 85#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 86#define BTR_TSEG1_SHIFT 8 87#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 88#define BTR_TSEG2_SHIFT 12 89#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 90 91/* brp extension register */ 92#define BRP_EXT_BRPE_MASK 0x0f 93#define BRP_EXT_BRPE_SHIFT 0 94 95/* IFx command request */ 96#define IF_COMR_BUSY BIT(15) 97 98/* IFx command mask */ 99#define IF_COMM_WR BIT(7) 100#define IF_COMM_MASK BIT(6) 101#define IF_COMM_ARB BIT(5) 102#define IF_COMM_CONTROL BIT(4) 103#define IF_COMM_CLR_INT_PND BIT(3) 104#define IF_COMM_TXRQST BIT(2) 105#define IF_COMM_DATAA BIT(1) 106#define IF_COMM_DATAB BIT(0) 107#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ 108 IF_COMM_CONTROL | IF_COMM_TXRQST | \ 109 IF_COMM_DATAA | IF_COMM_DATAB) 110 111/* IFx arbitration */ 112#define IF_ARB_MSGVAL BIT(15) 113#define IF_ARB_MSGXTD BIT(14) 114#define IF_ARB_TRANSMIT BIT(13) 115 116/* IFx message control */ 117#define IF_MCONT_NEWDAT BIT(15) 118#define IF_MCONT_MSGLST BIT(14) 119#define IF_MCONT_CLR_MSGLST (0 << 14) 120#define IF_MCONT_INTPND BIT(13) 121#define IF_MCONT_UMASK BIT(12) 122#define IF_MCONT_TXIE BIT(11) 123#define IF_MCONT_RXIE BIT(10) 124#define IF_MCONT_RMTEN BIT(9) 125#define IF_MCONT_TXRQST BIT(8) 126#define IF_MCONT_EOB BIT(7) 127#define IF_MCONT_DLC_MASK 0xf 128 129/* 130 * IFx register masks: 131 * allow easy operation on 16-bit registers when the 132 * argument is 32-bit instead 133 */ 134#define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF) 135#define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16) 136 137/* message object split */ 138#define C_CAN_NO_OF_OBJECTS 32 139#define C_CAN_MSG_OBJ_RX_NUM 16 140#define C_CAN_MSG_OBJ_TX_NUM 16 141 142#define C_CAN_MSG_OBJ_RX_FIRST 1 143#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \ 144 C_CAN_MSG_OBJ_RX_NUM - 1) 145 146#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1) 147#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \ 148 C_CAN_MSG_OBJ_TX_NUM - 1) 149 150#define C_CAN_MSG_OBJ_RX_SPLIT 9 151#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1) 152 153#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1) 154#define RECEIVE_OBJECT_BITS 0x0000ffff 155 156/* status interrupt */ 157#define STATUS_INTERRUPT 0x8000 158 159/* global interrupt masks */ 160#define ENABLE_ALL_INTERRUPTS 1 161#define DISABLE_ALL_INTERRUPTS 0 162 163/* minimum timeout for checking BUSY status */ 164#define MIN_TIMEOUT_VALUE 6 165 166/* napi related */ 167#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 168 169/* c_can lec values */ 170enum c_can_lec_type { 171 LEC_NO_ERROR = 0, 172 LEC_STUFF_ERROR, 173 LEC_FORM_ERROR, 174 LEC_ACK_ERROR, 175 LEC_BIT1_ERROR, 176 LEC_BIT0_ERROR, 177 LEC_CRC_ERROR, 178 LEC_UNUSED, 179}; 180 181/* 182 * c_can error types: 183 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 184 */ 185enum c_can_bus_error_types { 186 C_CAN_NO_ERROR = 0, 187 C_CAN_BUS_OFF, 188 C_CAN_ERROR_WARNING, 189 C_CAN_ERROR_PASSIVE, 190}; 191 192static struct can_bittiming_const c_can_bittiming_const = { 193 .name = KBUILD_MODNAME, 194 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 195 .tseg1_max = 16, 196 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 197 .tseg2_max = 8, 198 .sjw_max = 4, 199 .brp_min = 1, 200 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 201 .brp_inc = 1, 202}; 203 204static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 205{ 206 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + 207 C_CAN_MSG_OBJ_TX_FIRST; 208} 209 210static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv) 211{ 212 return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) + 213 C_CAN_MSG_OBJ_TX_FIRST; 214} 215 216static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) 217{ 218 u32 val = priv->read_reg(priv, index); 219 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 220 return val; 221} 222 223static void c_can_enable_all_interrupts(struct c_can_priv *priv, 224 int enable) 225{ 226 unsigned int cntrl_save = priv->read_reg(priv, 227 C_CAN_CTRL_REG); 228 229 if (enable) 230 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 231 else 232 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); 233 234 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); 235} 236 237static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 238{ 239 int count = MIN_TIMEOUT_VALUE; 240 241 while (count && priv->read_reg(priv, 242 C_CAN_IFACE(COMREQ_REG, iface)) & 243 IF_COMR_BUSY) { 244 count--; 245 udelay(1); 246 } 247 248 if (!count) 249 return 1; 250 251 return 0; 252} 253 254static inline void c_can_object_get(struct net_device *dev, 255 int iface, int objno, int mask) 256{ 257 struct c_can_priv *priv = netdev_priv(dev); 258 259 /* 260 * As per specs, after writting the message object number in the 261 * IF command request register the transfer b/w interface 262 * register and message RAM must be complete in 6 CAN-CLK 263 * period. 264 */ 265 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 266 IFX_WRITE_LOW_16BIT(mask)); 267 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 268 IFX_WRITE_LOW_16BIT(objno)); 269 270 if (c_can_msg_obj_is_busy(priv, iface)) 271 netdev_err(dev, "timed out in object get\n"); 272} 273 274static inline void c_can_object_put(struct net_device *dev, 275 int iface, int objno, int mask) 276{ 277 struct c_can_priv *priv = netdev_priv(dev); 278 279 /* 280 * As per specs, after writting the message object number in the 281 * IF command request register the transfer b/w interface 282 * register and message RAM must be complete in 6 CAN-CLK 283 * period. 284 */ 285 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 286 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); 287 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 288 IFX_WRITE_LOW_16BIT(objno)); 289 290 if (c_can_msg_obj_is_busy(priv, iface)) 291 netdev_err(dev, "timed out in object put\n"); 292} 293 294static void c_can_write_msg_object(struct net_device *dev, 295 int iface, struct can_frame *frame, int objno) 296{ 297 int i; 298 u16 flags = 0; 299 unsigned int id; 300 struct c_can_priv *priv = netdev_priv(dev); 301 302 if (!(frame->can_id & CAN_RTR_FLAG)) 303 flags |= IF_ARB_TRANSMIT; 304 305 if (frame->can_id & CAN_EFF_FLAG) { 306 id = frame->can_id & CAN_EFF_MASK; 307 flags |= IF_ARB_MSGXTD; 308 } else 309 id = ((frame->can_id & CAN_SFF_MASK) << 18); 310 311 flags |= IF_ARB_MSGVAL; 312 313 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 314 IFX_WRITE_LOW_16BIT(id)); 315 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | 316 IFX_WRITE_HIGH_16BIT(id)); 317 318 for (i = 0; i < frame->can_dlc; i += 2) { 319 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 320 frame->data[i] | (frame->data[i + 1] << 8)); 321 } 322 323 /* enable interrupt for this message object */ 324 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 325 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | 326 frame->can_dlc); 327 c_can_object_put(dev, iface, objno, IF_COMM_ALL); 328} 329 330static inline void c_can_mark_rx_msg_obj(struct net_device *dev, 331 int iface, int ctrl_mask, 332 int obj) 333{ 334 struct c_can_priv *priv = netdev_priv(dev); 335 336 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 337 ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND)); 338 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); 339 340} 341 342static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 343 int iface, 344 int ctrl_mask) 345{ 346 int i; 347 struct c_can_priv *priv = netdev_priv(dev); 348 349 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { 350 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 351 ctrl_mask & ~(IF_MCONT_MSGLST | 352 IF_MCONT_INTPND | IF_MCONT_NEWDAT)); 353 c_can_object_put(dev, iface, i, IF_COMM_CONTROL); 354 } 355} 356 357static inline void c_can_activate_rx_msg_obj(struct net_device *dev, 358 int iface, int ctrl_mask, 359 int obj) 360{ 361 struct c_can_priv *priv = netdev_priv(dev); 362 363 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 364 ctrl_mask & ~(IF_MCONT_MSGLST | 365 IF_MCONT_INTPND | IF_MCONT_NEWDAT)); 366 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); 367} 368 369static void c_can_handle_lost_msg_obj(struct net_device *dev, 370 int iface, int objno) 371{ 372 struct c_can_priv *priv = netdev_priv(dev); 373 struct net_device_stats *stats = &dev->stats; 374 struct sk_buff *skb; 375 struct can_frame *frame; 376 377 netdev_err(dev, "msg lost in buffer %d\n", objno); 378 379 c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 380 381 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 382 IF_MCONT_CLR_MSGLST); 383 384 c_can_object_put(dev, 0, objno, IF_COMM_CONTROL); 385 386 /* create an error msg */ 387 skb = alloc_can_err_skb(dev, &frame); 388 if (unlikely(!skb)) 389 return; 390 391 frame->can_id |= CAN_ERR_CRTL; 392 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 393 stats->rx_errors++; 394 stats->rx_over_errors++; 395 396 netif_receive_skb(skb); 397} 398 399static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) 400{ 401 u16 flags, data; 402 int i; 403 unsigned int val; 404 struct c_can_priv *priv = netdev_priv(dev); 405 struct net_device_stats *stats = &dev->stats; 406 struct sk_buff *skb; 407 struct can_frame *frame; 408 409 skb = alloc_can_skb(dev, &frame); 410 if (!skb) { 411 stats->rx_dropped++; 412 return -ENOMEM; 413 } 414 415 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 416 417 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); 418 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | 419 (flags << 16); 420 421 if (flags & IF_ARB_MSGXTD) 422 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; 423 else 424 frame->can_id = (val >> 18) & CAN_SFF_MASK; 425 426 if (flags & IF_ARB_TRANSMIT) 427 frame->can_id |= CAN_RTR_FLAG; 428 else { 429 for (i = 0; i < frame->can_dlc; i += 2) { 430 data = priv->read_reg(priv, 431 C_CAN_IFACE(DATA1_REG, iface) + i / 2); 432 frame->data[i] = data; 433 frame->data[i + 1] = data >> 8; 434 } 435 } 436 437 netif_receive_skb(skb); 438 439 stats->rx_packets++; 440 stats->rx_bytes += frame->can_dlc; 441 442 return 0; 443} 444 445static void c_can_setup_receive_object(struct net_device *dev, int iface, 446 int objno, unsigned int mask, 447 unsigned int id, unsigned int mcont) 448{ 449 struct c_can_priv *priv = netdev_priv(dev); 450 451 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), 452 IFX_WRITE_LOW_16BIT(mask)); 453 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), 454 IFX_WRITE_HIGH_16BIT(mask)); 455 456 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 457 IFX_WRITE_LOW_16BIT(id)); 458 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 459 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); 460 461 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 462 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 463 464 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 465 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 466} 467 468static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) 469{ 470 struct c_can_priv *priv = netdev_priv(dev); 471 472 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 473 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 474 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 475 476 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); 477 478 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 479 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 480} 481 482static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 483{ 484 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 485 486 /* 487 * as transmission request register's bit n-1 corresponds to 488 * message object n, we need to handle the same properly. 489 */ 490 if (val & (1 << (objno - 1))) 491 return 1; 492 493 return 0; 494} 495 496static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 497 struct net_device *dev) 498{ 499 u32 msg_obj_no; 500 struct c_can_priv *priv = netdev_priv(dev); 501 struct can_frame *frame = (struct can_frame *)skb->data; 502 503 if (can_dropped_invalid_skb(dev, skb)) 504 return NETDEV_TX_OK; 505 506 msg_obj_no = get_tx_next_msg_obj(priv); 507 508 /* prepare message object for transmission */ 509 c_can_write_msg_object(dev, 0, frame, msg_obj_no); 510 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 511 512 /* 513 * we have to stop the queue in case of a wrap around or 514 * if the next TX message object is still in use 515 */ 516 priv->tx_next++; 517 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 518 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 519 netif_stop_queue(dev); 520 521 return NETDEV_TX_OK; 522} 523 524static int c_can_set_bittiming(struct net_device *dev) 525{ 526 unsigned int reg_btr, reg_brpe, ctrl_save; 527 u8 brp, brpe, sjw, tseg1, tseg2; 528 u32 ten_bit_brp; 529 struct c_can_priv *priv = netdev_priv(dev); 530 const struct can_bittiming *bt = &priv->can.bittiming; 531 532 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 533 ten_bit_brp = bt->brp - 1; 534 brp = ten_bit_brp & BTR_BRP_MASK; 535 brpe = ten_bit_brp >> 6; 536 537 sjw = bt->sjw - 1; 538 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 539 tseg2 = bt->phase_seg2 - 1; 540 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 541 (tseg2 << BTR_TSEG2_SHIFT); 542 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 543 544 netdev_info(dev, 545 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 546 547 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 548 priv->write_reg(priv, C_CAN_CTRL_REG, 549 ctrl_save | CONTROL_CCE | CONTROL_INIT); 550 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 551 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 552 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 553 554 return 0; 555} 556 557/* 558 * Configure C_CAN message objects for Tx and Rx purposes: 559 * C_CAN provides a total of 32 message objects that can be configured 560 * either for Tx or Rx purposes. Here the first 16 message objects are used as 561 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 562 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 563 * See user guide document for further details on configuring message 564 * objects. 565 */ 566static void c_can_configure_msg_objects(struct net_device *dev) 567{ 568 int i; 569 570 /* first invalidate all message objects */ 571 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 572 c_can_inval_msg_object(dev, 0, i); 573 574 /* setup receive message objects */ 575 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 576 c_can_setup_receive_object(dev, 0, i, 0, 0, 577 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); 578 579 c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 580 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); 581} 582 583/* 584 * Configure C_CAN chip: 585 * - enable/disable auto-retransmission 586 * - set operating mode 587 * - configure message objects 588 */ 589static void c_can_chip_config(struct net_device *dev) 590{ 591 struct c_can_priv *priv = netdev_priv(dev); 592 593 /* enable automatic retransmission */ 594 priv->write_reg(priv, C_CAN_CTRL_REG, 595 CONTROL_ENABLE_AR); 596 597 if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY & 598 CAN_CTRLMODE_LOOPBACK)) { 599 /* loopback + silent mode : useful for hot self-test */ 600 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 601 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 602 priv->write_reg(priv, C_CAN_TEST_REG, 603 TEST_LBACK | TEST_SILENT); 604 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 605 /* loopback mode : useful for self-test function */ 606 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 607 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 608 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 609 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 610 /* silent mode : bus-monitoring mode */ 611 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 612 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 613 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 614 } else 615 /* normal mode*/ 616 priv->write_reg(priv, C_CAN_CTRL_REG, 617 CONTROL_EIE | CONTROL_SIE | CONTROL_IE); 618 619 /* configure message objects */ 620 c_can_configure_msg_objects(dev); 621 622 /* set a `lec` value so that we can check for updates later */ 623 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 624 625 /* set bittiming params */ 626 c_can_set_bittiming(dev); 627} 628 629static void c_can_start(struct net_device *dev) 630{ 631 struct c_can_priv *priv = netdev_priv(dev); 632 633 /* basic c_can configuration */ 634 c_can_chip_config(dev); 635 636 priv->can.state = CAN_STATE_ERROR_ACTIVE; 637 638 /* reset tx helper pointers */ 639 priv->tx_next = priv->tx_echo = 0; 640 641 /* enable status change, error and module interrupts */ 642 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 643} 644 645static void c_can_stop(struct net_device *dev) 646{ 647 struct c_can_priv *priv = netdev_priv(dev); 648 649 /* disable all interrupts */ 650 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 651 652 /* set the state as STOPPED */ 653 priv->can.state = CAN_STATE_STOPPED; 654} 655 656static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 657{ 658 switch (mode) { 659 case CAN_MODE_START: 660 c_can_start(dev); 661 netif_wake_queue(dev); 662 break; 663 default: 664 return -EOPNOTSUPP; 665 } 666 667 return 0; 668} 669 670static int c_can_get_berr_counter(const struct net_device *dev, 671 struct can_berr_counter *bec) 672{ 673 unsigned int reg_err_counter; 674 struct c_can_priv *priv = netdev_priv(dev); 675 676 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 677 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 678 ERR_CNT_REC_SHIFT; 679 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 680 681 return 0; 682} 683 684/* 685 * theory of operation: 686 * 687 * priv->tx_echo holds the number of the oldest can_frame put for 688 * transmission into the hardware, but not yet ACKed by the CAN tx 689 * complete IRQ. 690 * 691 * We iterate from priv->tx_echo to priv->tx_next and check if the 692 * packet has been transmitted, echo it back to the CAN framework. 693 * If we discover a not yet transmitted packet, stop looking for more. 694 */ 695static void c_can_do_tx(struct net_device *dev) 696{ 697 u32 val; 698 u32 msg_obj_no; 699 struct c_can_priv *priv = netdev_priv(dev); 700 struct net_device_stats *stats = &dev->stats; 701 702 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 703 msg_obj_no = get_tx_echo_msg_obj(priv); 704 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 705 if (!(val & (1 << (msg_obj_no - 1)))) { 706 can_get_echo_skb(dev, 707 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 708 stats->tx_bytes += priv->read_reg(priv, 709 C_CAN_IFACE(MSGCTRL_REG, 0)) 710 & IF_MCONT_DLC_MASK; 711 stats->tx_packets++; 712 c_can_inval_msg_object(dev, 0, msg_obj_no); 713 } else { 714 break; 715 } 716 } 717 718 /* restart queue if wrap-up or if queue stalled on last pkt */ 719 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 720 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) 721 netif_wake_queue(dev); 722} 723 724/* 725 * theory of operation: 726 * 727 * c_can core saves a received CAN message into the first free message 728 * object it finds free (starting with the lowest). Bits NEWDAT and 729 * INTPND are set for this message object indicating that a new message 730 * has arrived. To work-around this issue, we keep two groups of message 731 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 732 * 733 * To ensure in-order frame reception we use the following 734 * approach while re-activating a message object to receive further 735 * frames: 736 * - if the current message object number is lower than 737 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 738 * the INTPND bit. 739 * - if the current message object number is equal to 740 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 741 * receive message objects. 742 * - if the current message object number is greater than 743 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 744 * only this message object. 745 */ 746static int c_can_do_rx_poll(struct net_device *dev, int quota) 747{ 748 u32 num_rx_pkts = 0; 749 unsigned int msg_obj, msg_ctrl_save; 750 struct c_can_priv *priv = netdev_priv(dev); 751 u32 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG); 752 753 for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST; 754 msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0; 755 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG), 756 msg_obj++) { 757 /* 758 * as interrupt pending register's bit n-1 corresponds to 759 * message object n, we need to handle the same properly. 760 */ 761 if (val & (1 << (msg_obj - 1))) { 762 c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL & 763 ~IF_COMM_TXRQST); 764 msg_ctrl_save = priv->read_reg(priv, 765 C_CAN_IFACE(MSGCTRL_REG, 0)); 766 767 if (msg_ctrl_save & IF_MCONT_EOB) 768 return num_rx_pkts; 769 770 if (msg_ctrl_save & IF_MCONT_MSGLST) { 771 c_can_handle_lost_msg_obj(dev, 0, msg_obj); 772 num_rx_pkts++; 773 quota--; 774 continue; 775 } 776 777 if (!(msg_ctrl_save & IF_MCONT_NEWDAT)) 778 continue; 779 780 /* read the data from the message object */ 781 c_can_read_msg_object(dev, 0, msg_ctrl_save); 782 783 if (msg_obj < C_CAN_MSG_RX_LOW_LAST) 784 c_can_mark_rx_msg_obj(dev, 0, 785 msg_ctrl_save, msg_obj); 786 else if (msg_obj > C_CAN_MSG_RX_LOW_LAST) 787 /* activate this msg obj */ 788 c_can_activate_rx_msg_obj(dev, 0, 789 msg_ctrl_save, msg_obj); 790 else if (msg_obj == C_CAN_MSG_RX_LOW_LAST) 791 /* activate all lower message objects */ 792 c_can_activate_all_lower_rx_msg_obj(dev, 793 0, msg_ctrl_save); 794 795 num_rx_pkts++; 796 quota--; 797 } 798 } 799 800 return num_rx_pkts; 801} 802 803static inline int c_can_has_and_handle_berr(struct c_can_priv *priv) 804{ 805 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 806 (priv->current_status & LEC_UNUSED); 807} 808 809static int c_can_handle_state_change(struct net_device *dev, 810 enum c_can_bus_error_types error_type) 811{ 812 unsigned int reg_err_counter; 813 unsigned int rx_err_passive; 814 struct c_can_priv *priv = netdev_priv(dev); 815 struct net_device_stats *stats = &dev->stats; 816 struct can_frame *cf; 817 struct sk_buff *skb; 818 struct can_berr_counter bec; 819 820 /* propagate the error condition to the CAN stack */ 821 skb = alloc_can_err_skb(dev, &cf); 822 if (unlikely(!skb)) 823 return 0; 824 825 c_can_get_berr_counter(dev, &bec); 826 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 827 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 828 ERR_CNT_RP_SHIFT; 829 830 switch (error_type) { 831 case C_CAN_ERROR_WARNING: 832 /* error warning state */ 833 priv->can.can_stats.error_warning++; 834 priv->can.state = CAN_STATE_ERROR_WARNING; 835 cf->can_id |= CAN_ERR_CRTL; 836 cf->data[1] = (bec.txerr > bec.rxerr) ? 837 CAN_ERR_CRTL_TX_WARNING : 838 CAN_ERR_CRTL_RX_WARNING; 839 cf->data[6] = bec.txerr; 840 cf->data[7] = bec.rxerr; 841 842 break; 843 case C_CAN_ERROR_PASSIVE: 844 /* error passive state */ 845 priv->can.can_stats.error_passive++; 846 priv->can.state = CAN_STATE_ERROR_PASSIVE; 847 cf->can_id |= CAN_ERR_CRTL; 848 if (rx_err_passive) 849 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 850 if (bec.txerr > 127) 851 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 852 853 cf->data[6] = bec.txerr; 854 cf->data[7] = bec.rxerr; 855 break; 856 case C_CAN_BUS_OFF: 857 /* bus-off state */ 858 priv->can.state = CAN_STATE_BUS_OFF; 859 cf->can_id |= CAN_ERR_BUSOFF; 860 /* 861 * disable all interrupts in bus-off mode to ensure that 862 * the CPU is not hogged down 863 */ 864 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 865 can_bus_off(dev); 866 break; 867 default: 868 break; 869 } 870 871 netif_receive_skb(skb); 872 stats->rx_packets++; 873 stats->rx_bytes += cf->can_dlc; 874 875 return 1; 876} 877 878static int c_can_handle_bus_err(struct net_device *dev, 879 enum c_can_lec_type lec_type) 880{ 881 struct c_can_priv *priv = netdev_priv(dev); 882 struct net_device_stats *stats = &dev->stats; 883 struct can_frame *cf; 884 struct sk_buff *skb; 885 886 /* 887 * early exit if no lec update or no error. 888 * no lec update means that no CAN bus event has been detected 889 * since CPU wrote 0x7 value to status reg. 890 */ 891 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 892 return 0; 893 894 /* propagate the error condition to the CAN stack */ 895 skb = alloc_can_err_skb(dev, &cf); 896 if (unlikely(!skb)) 897 return 0; 898 899 /* 900 * check for 'last error code' which tells us the 901 * type of the last error to occur on the CAN bus 902 */ 903 904 /* common for all type of bus errors */ 905 priv->can.can_stats.bus_error++; 906 stats->rx_errors++; 907 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 908 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 909 910 switch (lec_type) { 911 case LEC_STUFF_ERROR: 912 netdev_dbg(dev, "stuff error\n"); 913 cf->data[2] |= CAN_ERR_PROT_STUFF; 914 break; 915 case LEC_FORM_ERROR: 916 netdev_dbg(dev, "form error\n"); 917 cf->data[2] |= CAN_ERR_PROT_FORM; 918 break; 919 case LEC_ACK_ERROR: 920 netdev_dbg(dev, "ack error\n"); 921 cf->data[2] |= (CAN_ERR_PROT_LOC_ACK | 922 CAN_ERR_PROT_LOC_ACK_DEL); 923 break; 924 case LEC_BIT1_ERROR: 925 netdev_dbg(dev, "bit1 error\n"); 926 cf->data[2] |= CAN_ERR_PROT_BIT1; 927 break; 928 case LEC_BIT0_ERROR: 929 netdev_dbg(dev, "bit0 error\n"); 930 cf->data[2] |= CAN_ERR_PROT_BIT0; 931 break; 932 case LEC_CRC_ERROR: 933 netdev_dbg(dev, "CRC error\n"); 934 cf->data[2] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 935 CAN_ERR_PROT_LOC_CRC_DEL); 936 break; 937 default: 938 break; 939 } 940 941 /* set a `lec` value so that we can check for updates later */ 942 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 943 944 netif_receive_skb(skb); 945 stats->rx_packets++; 946 stats->rx_bytes += cf->can_dlc; 947 948 return 1; 949} 950 951static int c_can_poll(struct napi_struct *napi, int quota) 952{ 953 u16 irqstatus; 954 int lec_type = 0; 955 int work_done = 0; 956 struct net_device *dev = napi->dev; 957 struct c_can_priv *priv = netdev_priv(dev); 958 959 irqstatus = priv->irqstatus; 960 if (!irqstatus) 961 goto end; 962 963 /* status events have the highest priority */ 964 if (irqstatus == STATUS_INTERRUPT) { 965 priv->current_status = priv->read_reg(priv, 966 C_CAN_STS_REG); 967 968 /* handle Tx/Rx events */ 969 if (priv->current_status & STATUS_TXOK) 970 priv->write_reg(priv, C_CAN_STS_REG, 971 priv->current_status & ~STATUS_TXOK); 972 973 if (priv->current_status & STATUS_RXOK) 974 priv->write_reg(priv, C_CAN_STS_REG, 975 priv->current_status & ~STATUS_RXOK); 976 977 /* handle state changes */ 978 if ((priv->current_status & STATUS_EWARN) && 979 (!(priv->last_status & STATUS_EWARN))) { 980 netdev_dbg(dev, "entered error warning state\n"); 981 work_done += c_can_handle_state_change(dev, 982 C_CAN_ERROR_WARNING); 983 } 984 if ((priv->current_status & STATUS_EPASS) && 985 (!(priv->last_status & STATUS_EPASS))) { 986 netdev_dbg(dev, "entered error passive state\n"); 987 work_done += c_can_handle_state_change(dev, 988 C_CAN_ERROR_PASSIVE); 989 } 990 if ((priv->current_status & STATUS_BOFF) && 991 (!(priv->last_status & STATUS_BOFF))) { 992 netdev_dbg(dev, "entered bus off state\n"); 993 work_done += c_can_handle_state_change(dev, 994 C_CAN_BUS_OFF); 995 } 996 997 /* handle bus recovery events */ 998 if ((!(priv->current_status & STATUS_BOFF)) && 999 (priv->last_status & STATUS_BOFF)) { 1000 netdev_dbg(dev, "left bus off state\n"); 1001 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1002 } 1003 if ((!(priv->current_status & STATUS_EPASS)) && 1004 (priv->last_status & STATUS_EPASS)) { 1005 netdev_dbg(dev, "left error passive state\n"); 1006 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1007 } 1008 1009 priv->last_status = priv->current_status; 1010 1011 /* handle lec errors on the bus */ 1012 lec_type = c_can_has_and_handle_berr(priv); 1013 if (lec_type) 1014 work_done += c_can_handle_bus_err(dev, lec_type); 1015 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && 1016 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { 1017 /* handle events corresponding to receive message objects */ 1018 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1019 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && 1020 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { 1021 /* handle events corresponding to transmit message objects */ 1022 c_can_do_tx(dev); 1023 } 1024 1025end: 1026 if (work_done < quota) { 1027 napi_complete(napi); 1028 /* enable all IRQs */ 1029 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1030 } 1031 1032 return work_done; 1033} 1034 1035static irqreturn_t c_can_isr(int irq, void *dev_id) 1036{ 1037 struct net_device *dev = (struct net_device *)dev_id; 1038 struct c_can_priv *priv = netdev_priv(dev); 1039 1040 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); 1041 if (!priv->irqstatus) 1042 return IRQ_NONE; 1043 1044 /* disable all interrupts and schedule the NAPI */ 1045 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1046 napi_schedule(&priv->napi); 1047 1048 return IRQ_HANDLED; 1049} 1050 1051static int c_can_open(struct net_device *dev) 1052{ 1053 int err; 1054 struct c_can_priv *priv = netdev_priv(dev); 1055 1056 /* open the can device */ 1057 err = open_candev(dev); 1058 if (err) { 1059 netdev_err(dev, "failed to open can device\n"); 1060 return err; 1061 } 1062 1063 /* register interrupt handler */ 1064 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1065 dev); 1066 if (err < 0) { 1067 netdev_err(dev, "failed to request interrupt\n"); 1068 goto exit_irq_fail; 1069 } 1070 1071 napi_enable(&priv->napi); 1072 1073 /* start the c_can controller */ 1074 c_can_start(dev); 1075 1076 netif_start_queue(dev); 1077 1078 return 0; 1079 1080exit_irq_fail: 1081 close_candev(dev); 1082 return err; 1083} 1084 1085static int c_can_close(struct net_device *dev) 1086{ 1087 struct c_can_priv *priv = netdev_priv(dev); 1088 1089 netif_stop_queue(dev); 1090 napi_disable(&priv->napi); 1091 c_can_stop(dev); 1092 free_irq(dev->irq, dev); 1093 close_candev(dev); 1094 1095 return 0; 1096} 1097 1098struct net_device *alloc_c_can_dev(void) 1099{ 1100 struct net_device *dev; 1101 struct c_can_priv *priv; 1102 1103 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1104 if (!dev) 1105 return NULL; 1106 1107 priv = netdev_priv(dev); 1108 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1109 1110 priv->dev = dev; 1111 priv->can.bittiming_const = &c_can_bittiming_const; 1112 priv->can.do_set_mode = c_can_set_mode; 1113 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1114 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1115 CAN_CTRLMODE_LISTENONLY | 1116 CAN_CTRLMODE_BERR_REPORTING; 1117 1118 return dev; 1119} 1120EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1121 1122void free_c_can_dev(struct net_device *dev) 1123{ 1124 free_candev(dev); 1125} 1126EXPORT_SYMBOL_GPL(free_c_can_dev); 1127 1128static const struct net_device_ops c_can_netdev_ops = { 1129 .ndo_open = c_can_open, 1130 .ndo_stop = c_can_close, 1131 .ndo_start_xmit = c_can_start_xmit, 1132}; 1133 1134int register_c_can_dev(struct net_device *dev) 1135{ 1136 dev->flags |= IFF_ECHO; /* we support local echo */ 1137 dev->netdev_ops = &c_can_netdev_ops; 1138 1139 return register_candev(dev); 1140} 1141EXPORT_SYMBOL_GPL(register_c_can_dev); 1142 1143void unregister_c_can_dev(struct net_device *dev) 1144{ 1145 struct c_can_priv *priv = netdev_priv(dev); 1146 1147 /* disable all interrupts */ 1148 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1149 1150 unregister_candev(dev); 1151} 1152EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1153 1154MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1155MODULE_LICENSE("GPL v2"); 1156MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1157