c_can.c revision 35bdafb576c5c0a06815e7a681571c3ab950ff7e
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42#include <linux/can/led.h> 43 44#include "c_can.h" 45 46/* Number of interface registers */ 47#define IF_ENUM_REG_LEN 11 48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 49 50/* control extension register D_CAN specific */ 51#define CONTROL_EX_PDR BIT(8) 52 53/* control register */ 54#define CONTROL_TEST BIT(7) 55#define CONTROL_CCE BIT(6) 56#define CONTROL_DISABLE_AR BIT(5) 57#define CONTROL_ENABLE_AR (0 << 5) 58#define CONTROL_EIE BIT(3) 59#define CONTROL_SIE BIT(2) 60#define CONTROL_IE BIT(1) 61#define CONTROL_INIT BIT(0) 62 63#define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE) 64 65/* test register */ 66#define TEST_RX BIT(7) 67#define TEST_TX1 BIT(6) 68#define TEST_TX2 BIT(5) 69#define TEST_LBACK BIT(4) 70#define TEST_SILENT BIT(3) 71#define TEST_BASIC BIT(2) 72 73/* status register */ 74#define STATUS_PDA BIT(10) 75#define STATUS_BOFF BIT(7) 76#define STATUS_EWARN BIT(6) 77#define STATUS_EPASS BIT(5) 78#define STATUS_RXOK BIT(4) 79#define STATUS_TXOK BIT(3) 80 81/* error counter register */ 82#define ERR_CNT_TEC_MASK 0xff 83#define ERR_CNT_TEC_SHIFT 0 84#define ERR_CNT_REC_SHIFT 8 85#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 86#define ERR_CNT_RP_SHIFT 15 87#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 88 89/* bit-timing register */ 90#define BTR_BRP_MASK 0x3f 91#define BTR_BRP_SHIFT 0 92#define BTR_SJW_SHIFT 6 93#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 94#define BTR_TSEG1_SHIFT 8 95#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 96#define BTR_TSEG2_SHIFT 12 97#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 98 99/* brp extension register */ 100#define BRP_EXT_BRPE_MASK 0x0f 101#define BRP_EXT_BRPE_SHIFT 0 102 103/* IFx command request */ 104#define IF_COMR_BUSY BIT(15) 105 106/* IFx command mask */ 107#define IF_COMM_WR BIT(7) 108#define IF_COMM_MASK BIT(6) 109#define IF_COMM_ARB BIT(5) 110#define IF_COMM_CONTROL BIT(4) 111#define IF_COMM_CLR_INT_PND BIT(3) 112#define IF_COMM_TXRQST BIT(2) 113#define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST 114#define IF_COMM_DATAA BIT(1) 115#define IF_COMM_DATAB BIT(0) 116 117/* TX buffer setup */ 118#define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \ 119 IF_COMM_TXRQST | \ 120 IF_COMM_DATAA | IF_COMM_DATAB) 121 122/* For the low buffers we clear the interrupt bit, but keep newdat */ 123#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 124 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 125 IF_COMM_DATAA | IF_COMM_DATAB) 126 127/* For the high buffers we clear the interrupt bit and newdat */ 128#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT) 129 130 131/* Receive setup of message objects */ 132#define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL) 133 134/* Invalidation of message objects */ 135#define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL) 136 137/* IFx arbitration */ 138#define IF_ARB_MSGVAL BIT(31) 139#define IF_ARB_MSGXTD BIT(30) 140#define IF_ARB_TRANSMIT BIT(29) 141 142/* IFx message control */ 143#define IF_MCONT_NEWDAT BIT(15) 144#define IF_MCONT_MSGLST BIT(14) 145#define IF_MCONT_INTPND BIT(13) 146#define IF_MCONT_UMASK BIT(12) 147#define IF_MCONT_TXIE BIT(11) 148#define IF_MCONT_RXIE BIT(10) 149#define IF_MCONT_RMTEN BIT(9) 150#define IF_MCONT_TXRQST BIT(8) 151#define IF_MCONT_EOB BIT(7) 152#define IF_MCONT_DLC_MASK 0xf 153 154#define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK) 155#define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB) 156 157#define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB) 158 159/* 160 * Use IF1 for RX and IF2 for TX 161 */ 162#define IF_RX 0 163#define IF_TX 1 164 165/* minimum timeout for checking BUSY status */ 166#define MIN_TIMEOUT_VALUE 6 167 168/* Wait for ~1 sec for INIT bit */ 169#define INIT_WAIT_MS 1000 170 171/* napi related */ 172#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 173 174/* c_can lec values */ 175enum c_can_lec_type { 176 LEC_NO_ERROR = 0, 177 LEC_STUFF_ERROR, 178 LEC_FORM_ERROR, 179 LEC_ACK_ERROR, 180 LEC_BIT1_ERROR, 181 LEC_BIT0_ERROR, 182 LEC_CRC_ERROR, 183 LEC_UNUSED, 184 LEC_MASK = LEC_UNUSED, 185}; 186 187/* 188 * c_can error types: 189 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 190 */ 191enum c_can_bus_error_types { 192 C_CAN_NO_ERROR = 0, 193 C_CAN_BUS_OFF, 194 C_CAN_ERROR_WARNING, 195 C_CAN_ERROR_PASSIVE, 196}; 197 198static const struct can_bittiming_const c_can_bittiming_const = { 199 .name = KBUILD_MODNAME, 200 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 201 .tseg1_max = 16, 202 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 203 .tseg2_max = 8, 204 .sjw_max = 4, 205 .brp_min = 1, 206 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 207 .brp_inc = 1, 208}; 209 210static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 211{ 212 if (priv->device) 213 pm_runtime_enable(priv->device); 214} 215 216static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 217{ 218 if (priv->device) 219 pm_runtime_disable(priv->device); 220} 221 222static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 223{ 224 if (priv->device) 225 pm_runtime_get_sync(priv->device); 226} 227 228static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 229{ 230 if (priv->device) 231 pm_runtime_put_sync(priv->device); 232} 233 234static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 235{ 236 if (priv->raminit) 237 priv->raminit(priv, enable); 238} 239 240static void c_can_irq_control(struct c_can_priv *priv, bool enable) 241{ 242 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK; 243 244 if (enable) 245 ctrl |= CONTROL_IRQMSK; 246 247 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl); 248} 249 250static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj) 251{ 252 struct c_can_priv *priv = netdev_priv(dev); 253 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface); 254 255 priv->write_reg(priv, reg + 1, cmd); 256 priv->write_reg(priv, reg, obj); 257 258 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) { 259 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY)) 260 return; 261 udelay(1); 262 } 263 netdev_err(dev, "Updating object timed out\n"); 264 265} 266 267static inline void c_can_object_get(struct net_device *dev, int iface, 268 u32 obj, u32 cmd) 269{ 270 c_can_obj_update(dev, iface, cmd, obj); 271} 272 273static inline void c_can_object_put(struct net_device *dev, int iface, 274 u32 obj, u32 cmd) 275{ 276 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj); 277} 278 279static void c_can_setup_tx_object(struct net_device *dev, int iface, 280 struct can_frame *frame, int obj) 281{ 282 struct c_can_priv *priv = netdev_priv(dev); 283 u16 ctrl = IF_MCONT_TX | frame->can_dlc; 284 u32 arb = IF_ARB_MSGVAL; 285 int i; 286 287 if (frame->can_id & CAN_EFF_FLAG) { 288 arb |= frame->can_id & CAN_EFF_MASK; 289 arb |= IF_ARB_MSGXTD; 290 } else { 291 arb |= (frame->can_id & CAN_SFF_MASK) << 18; 292 } 293 294 if (!(frame->can_id & CAN_RTR_FLAG)) 295 arb |= IF_ARB_TRANSMIT; 296 297 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), arb); 298 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), arb >> 16); 299 300 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 301 302 for (i = 0; i < frame->can_dlc; i += 2) { 303 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 304 frame->data[i] | (frame->data[i + 1] << 8)); 305 } 306} 307 308static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 309 int iface) 310{ 311 int i; 312 313 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) 314 c_can_object_get(dev, iface, i, IF_COMM_CLR_NEWDAT); 315} 316 317static int c_can_handle_lost_msg_obj(struct net_device *dev, 318 int iface, int objno, u32 ctrl) 319{ 320 struct net_device_stats *stats = &dev->stats; 321 struct c_can_priv *priv = netdev_priv(dev); 322 struct can_frame *frame; 323 struct sk_buff *skb; 324 325 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 326 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 327 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 328 329 stats->rx_errors++; 330 stats->rx_over_errors++; 331 332 /* create an error msg */ 333 skb = alloc_can_err_skb(dev, &frame); 334 if (unlikely(!skb)) 335 return 0; 336 337 frame->can_id |= CAN_ERR_CRTL; 338 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 339 340 netif_receive_skb(skb); 341 return 1; 342} 343 344static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl) 345{ 346 struct net_device_stats *stats = &dev->stats; 347 struct c_can_priv *priv = netdev_priv(dev); 348 struct can_frame *frame; 349 struct sk_buff *skb; 350 u32 arb, data; 351 352 skb = alloc_can_skb(dev, &frame); 353 if (!skb) { 354 stats->rx_dropped++; 355 return -ENOMEM; 356 } 357 358 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 359 360 arb = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)); 361 arb |= priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)) << 16; 362 363 if (arb & IF_ARB_MSGXTD) 364 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG; 365 else 366 frame->can_id = (arb >> 18) & CAN_SFF_MASK; 367 368 if (arb & IF_ARB_TRANSMIT) { 369 frame->can_id |= CAN_RTR_FLAG; 370 } else { 371 int i, dreg = C_CAN_IFACE(DATA1_REG, iface); 372 373 for (i = 0; i < frame->can_dlc; i += 2, dreg ++) { 374 data = priv->read_reg(priv, dreg); 375 frame->data[i] = data; 376 frame->data[i + 1] = data >> 8; 377 } 378 } 379 380 stats->rx_packets++; 381 stats->rx_bytes += frame->can_dlc; 382 383 netif_receive_skb(skb); 384 return 0; 385} 386 387static void c_can_setup_receive_object(struct net_device *dev, int iface, 388 u32 obj, u32 mask, u32 id, u32 mcont) 389{ 390 struct c_can_priv *priv = netdev_priv(dev); 391 392 mask |= BIT(29); 393 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), mask); 394 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), mask >> 16); 395 396 id |= IF_ARB_MSGVAL; 397 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), id); 398 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), id >> 16); 399 400 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 401 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP); 402} 403 404static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj) 405{ 406 struct c_can_priv *priv = netdev_priv(dev); 407 408 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 409 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 410 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 411 412 c_can_object_put(dev, iface, obj, IF_COMM_INVAL); 413} 414 415static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 416 struct net_device *dev) 417{ 418 struct can_frame *frame = (struct can_frame *)skb->data; 419 struct c_can_priv *priv = netdev_priv(dev); 420 u32 idx, obj; 421 422 if (can_dropped_invalid_skb(dev, skb)) 423 return NETDEV_TX_OK; 424 /* 425 * This is not a FIFO. C/D_CAN sends out the buffers 426 * prioritized. The lowest buffer number wins. 427 */ 428 idx = fls(atomic_read(&priv->tx_active)); 429 obj = idx + C_CAN_MSG_OBJ_TX_FIRST; 430 431 /* If this is the last buffer, stop the xmit queue */ 432 if (idx == C_CAN_MSG_OBJ_TX_NUM - 1) 433 netif_stop_queue(dev); 434 /* 435 * Store the message in the interface so we can call 436 * can_put_echo_skb(). We must do this before we enable 437 * transmit as we might race against do_tx(). 438 */ 439 c_can_setup_tx_object(dev, IF_TX, frame, obj); 440 priv->dlc[idx] = frame->can_dlc; 441 can_put_echo_skb(skb, dev, idx); 442 443 /* Update the active bits */ 444 atomic_add((1 << idx), &priv->tx_active); 445 /* Start transmission */ 446 c_can_object_put(dev, IF_TX, obj, IF_COMM_TX); 447 448 return NETDEV_TX_OK; 449} 450 451static int c_can_wait_for_ctrl_init(struct net_device *dev, 452 struct c_can_priv *priv, u32 init) 453{ 454 int retry = 0; 455 456 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 457 udelay(10); 458 if (retry++ > 1000) { 459 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 460 return -EIO; 461 } 462 } 463 return 0; 464} 465 466static int c_can_set_bittiming(struct net_device *dev) 467{ 468 unsigned int reg_btr, reg_brpe, ctrl_save; 469 u8 brp, brpe, sjw, tseg1, tseg2; 470 u32 ten_bit_brp; 471 struct c_can_priv *priv = netdev_priv(dev); 472 const struct can_bittiming *bt = &priv->can.bittiming; 473 int res; 474 475 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 476 ten_bit_brp = bt->brp - 1; 477 brp = ten_bit_brp & BTR_BRP_MASK; 478 brpe = ten_bit_brp >> 6; 479 480 sjw = bt->sjw - 1; 481 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 482 tseg2 = bt->phase_seg2 - 1; 483 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 484 (tseg2 << BTR_TSEG2_SHIFT); 485 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 486 487 netdev_info(dev, 488 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 489 490 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 491 ctrl_save &= ~CONTROL_INIT; 492 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 493 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 494 if (res) 495 return res; 496 497 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 498 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 499 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 500 501 return c_can_wait_for_ctrl_init(dev, priv, 0); 502} 503 504/* 505 * Configure C_CAN message objects for Tx and Rx purposes: 506 * C_CAN provides a total of 32 message objects that can be configured 507 * either for Tx or Rx purposes. Here the first 16 message objects are used as 508 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 509 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 510 * See user guide document for further details on configuring message 511 * objects. 512 */ 513static void c_can_configure_msg_objects(struct net_device *dev) 514{ 515 int i; 516 517 /* first invalidate all message objects */ 518 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 519 c_can_inval_msg_object(dev, IF_RX, i); 520 521 /* setup receive message objects */ 522 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 523 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV); 524 525 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 526 IF_MCONT_RCV_EOB); 527} 528 529/* 530 * Configure C_CAN chip: 531 * - enable/disable auto-retransmission 532 * - set operating mode 533 * - configure message objects 534 */ 535static int c_can_chip_config(struct net_device *dev) 536{ 537 struct c_can_priv *priv = netdev_priv(dev); 538 539 /* enable automatic retransmission */ 540 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); 541 542 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 543 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 544 /* loopback + silent mode : useful for hot self-test */ 545 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 546 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); 547 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 548 /* loopback mode : useful for self-test function */ 549 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 550 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 551 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 552 /* silent mode : bus-monitoring mode */ 553 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 554 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 555 } 556 557 /* configure message objects */ 558 c_can_configure_msg_objects(dev); 559 560 /* set a `lec` value so that we can check for updates later */ 561 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 562 563 /* Clear all internal status */ 564 atomic_set(&priv->tx_active, 0); 565 priv->rxmasked = 0; 566 567 /* set bittiming params */ 568 return c_can_set_bittiming(dev); 569} 570 571static int c_can_start(struct net_device *dev) 572{ 573 struct c_can_priv *priv = netdev_priv(dev); 574 int err; 575 576 /* basic c_can configuration */ 577 err = c_can_chip_config(dev); 578 if (err) 579 return err; 580 581 /* Setup the command for new messages */ 582 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ? 583 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 584 585 priv->can.state = CAN_STATE_ERROR_ACTIVE; 586 587 return 0; 588} 589 590static void c_can_stop(struct net_device *dev) 591{ 592 struct c_can_priv *priv = netdev_priv(dev); 593 594 c_can_irq_control(priv, false); 595 priv->can.state = CAN_STATE_STOPPED; 596} 597 598static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 599{ 600 struct c_can_priv *priv = netdev_priv(dev); 601 int err; 602 603 switch (mode) { 604 case CAN_MODE_START: 605 err = c_can_start(dev); 606 if (err) 607 return err; 608 netif_wake_queue(dev); 609 c_can_irq_control(priv, true); 610 break; 611 default: 612 return -EOPNOTSUPP; 613 } 614 615 return 0; 616} 617 618static int __c_can_get_berr_counter(const struct net_device *dev, 619 struct can_berr_counter *bec) 620{ 621 unsigned int reg_err_counter; 622 struct c_can_priv *priv = netdev_priv(dev); 623 624 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 625 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 626 ERR_CNT_REC_SHIFT; 627 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 628 629 return 0; 630} 631 632static int c_can_get_berr_counter(const struct net_device *dev, 633 struct can_berr_counter *bec) 634{ 635 struct c_can_priv *priv = netdev_priv(dev); 636 int err; 637 638 c_can_pm_runtime_get_sync(priv); 639 err = __c_can_get_berr_counter(dev, bec); 640 c_can_pm_runtime_put_sync(priv); 641 642 return err; 643} 644 645static void c_can_do_tx(struct net_device *dev) 646{ 647 struct c_can_priv *priv = netdev_priv(dev); 648 struct net_device_stats *stats = &dev->stats; 649 u32 idx, obj, pkts = 0, bytes = 0, pend, clr; 650 651 clr = pend = priv->read_reg(priv, C_CAN_INTPND2_REG); 652 653 while ((idx = ffs(pend))) { 654 idx--; 655 pend &= ~(1 << idx); 656 obj = idx + C_CAN_MSG_OBJ_TX_FIRST; 657 c_can_inval_msg_object(dev, IF_RX, obj); 658 can_get_echo_skb(dev, idx); 659 bytes += priv->dlc[idx]; 660 pkts++; 661 } 662 663 /* Clear the bits in the tx_active mask */ 664 atomic_sub(clr, &priv->tx_active); 665 666 if (clr & (1 << (C_CAN_MSG_OBJ_TX_NUM - 1))) 667 netif_wake_queue(dev); 668 669 if (pkts) { 670 stats->tx_bytes += bytes; 671 stats->tx_packets += pkts; 672 can_led_event(dev, CAN_LED_EVENT_TX); 673 } 674} 675 676/* 677 * If we have a gap in the pending bits, that means we either 678 * raced with the hardware or failed to readout all upper 679 * objects in the last run due to quota limit. 680 */ 681static u32 c_can_adjust_pending(u32 pend) 682{ 683 u32 weight, lasts; 684 685 if (pend == RECEIVE_OBJECT_BITS) 686 return pend; 687 688 /* 689 * If the last set bit is larger than the number of pending 690 * bits we have a gap. 691 */ 692 weight = hweight32(pend); 693 lasts = fls(pend); 694 695 /* If the bits are linear, nothing to do */ 696 if (lasts == weight) 697 return pend; 698 699 /* 700 * Find the first set bit after the gap. We walk backwards 701 * from the last set bit. 702 */ 703 for (lasts--; pend & (1 << (lasts - 1)); lasts--); 704 705 return pend & ~((1 << lasts) - 1); 706} 707 708static inline void c_can_rx_object_get(struct net_device *dev, 709 struct c_can_priv *priv, u32 obj) 710{ 711#ifdef CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING 712 if (obj < C_CAN_MSG_RX_LOW_LAST) 713 c_can_object_get(dev, IF_RX, obj, IF_COMM_RCV_LOW); 714 else 715#endif 716 c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high); 717} 718 719static inline void c_can_rx_finalize(struct net_device *dev, 720 struct c_can_priv *priv, u32 obj) 721{ 722#ifdef CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING 723 if (obj < C_CAN_MSG_RX_LOW_LAST) 724 priv->rxmasked |= BIT(obj - 1); 725 else if (obj == C_CAN_MSG_RX_LOW_LAST) { 726 priv->rxmasked = 0; 727 /* activate all lower message objects */ 728 c_can_activate_all_lower_rx_msg_obj(dev, IF_RX); 729 } 730#endif 731 if (priv->type != BOSCH_D_CAN) 732 c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT); 733} 734 735static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 736 u32 pend, int quota) 737{ 738 u32 pkts = 0, ctrl, obj; 739 740 while ((obj = ffs(pend)) && quota > 0) { 741 pend &= ~BIT(obj - 1); 742 743 c_can_rx_object_get(dev, priv, obj); 744 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 745 746 if (ctrl & IF_MCONT_MSGLST) { 747 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); 748 749 pkts += n; 750 quota -= n; 751 continue; 752 } 753 754 /* 755 * This really should not happen, but this covers some 756 * odd HW behaviour. Do not remove that unless you 757 * want to brick your machine. 758 */ 759 if (!(ctrl & IF_MCONT_NEWDAT)) 760 continue; 761 762 /* read the data from the message object */ 763 c_can_read_msg_object(dev, IF_RX, ctrl); 764 765 c_can_rx_finalize(dev, priv, obj); 766 767 pkts++; 768 quota--; 769 } 770 771 return pkts; 772} 773 774static inline u32 c_can_get_pending(struct c_can_priv *priv) 775{ 776 u32 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG); 777 778#ifdef CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING 779 pend &= ~priv->rxmasked; 780#endif 781 return pend; 782} 783 784/* 785 * theory of operation: 786 * 787 * c_can core saves a received CAN message into the first free message 788 * object it finds free (starting with the lowest). Bits NEWDAT and 789 * INTPND are set for this message object indicating that a new message 790 * has arrived. To work-around this issue, we keep two groups of message 791 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 792 * 793 * If CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING = y 794 * 795 * To ensure in-order frame reception we use the following 796 * approach while re-activating a message object to receive further 797 * frames: 798 * - if the current message object number is lower than 799 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 800 * the INTPND bit. 801 * - if the current message object number is equal to 802 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 803 * receive message objects. 804 * - if the current message object number is greater than 805 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 806 * only this message object. 807 * 808 * This can cause packet loss! 809 * 810 * If CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING = n 811 * 812 * We clear the newdat bit right away. 813 * 814 * This can result in packet reordering when the readout is slow. 815 */ 816static int c_can_do_rx_poll(struct net_device *dev, int quota) 817{ 818 struct c_can_priv *priv = netdev_priv(dev); 819 u32 pkts = 0, pend = 0, toread, n; 820 821 /* 822 * It is faster to read only one 16bit register. This is only possible 823 * for a maximum number of 16 objects. 824 */ 825 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, 826 "Implementation does not support more message objects than 16"); 827 828 while (quota > 0) { 829 if (!pend) { 830 pend = c_can_get_pending(priv); 831 if (!pend) 832 break; 833 /* 834 * If the pending field has a gap, handle the 835 * bits above the gap first. 836 */ 837 toread = c_can_adjust_pending(pend); 838 } else { 839 toread = pend; 840 } 841 /* Remove the bits from pend */ 842 pend &= ~toread; 843 /* Read the objects */ 844 n = c_can_read_objects(dev, priv, toread, quota); 845 pkts += n; 846 quota -= n; 847 } 848 849 if (pkts) 850 can_led_event(dev, CAN_LED_EVENT_RX); 851 852 return pkts; 853} 854 855static int c_can_handle_state_change(struct net_device *dev, 856 enum c_can_bus_error_types error_type) 857{ 858 unsigned int reg_err_counter; 859 unsigned int rx_err_passive; 860 struct c_can_priv *priv = netdev_priv(dev); 861 struct net_device_stats *stats = &dev->stats; 862 struct can_frame *cf; 863 struct sk_buff *skb; 864 struct can_berr_counter bec; 865 866 switch (error_type) { 867 case C_CAN_ERROR_WARNING: 868 /* error warning state */ 869 priv->can.can_stats.error_warning++; 870 priv->can.state = CAN_STATE_ERROR_WARNING; 871 break; 872 case C_CAN_ERROR_PASSIVE: 873 /* error passive state */ 874 priv->can.can_stats.error_passive++; 875 priv->can.state = CAN_STATE_ERROR_PASSIVE; 876 break; 877 case C_CAN_BUS_OFF: 878 /* bus-off state */ 879 priv->can.state = CAN_STATE_BUS_OFF; 880 can_bus_off(dev); 881 break; 882 default: 883 break; 884 } 885 886 /* propagate the error condition to the CAN stack */ 887 skb = alloc_can_err_skb(dev, &cf); 888 if (unlikely(!skb)) 889 return 0; 890 891 __c_can_get_berr_counter(dev, &bec); 892 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 893 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 894 ERR_CNT_RP_SHIFT; 895 896 switch (error_type) { 897 case C_CAN_ERROR_WARNING: 898 /* error warning state */ 899 cf->can_id |= CAN_ERR_CRTL; 900 cf->data[1] = (bec.txerr > bec.rxerr) ? 901 CAN_ERR_CRTL_TX_WARNING : 902 CAN_ERR_CRTL_RX_WARNING; 903 cf->data[6] = bec.txerr; 904 cf->data[7] = bec.rxerr; 905 906 break; 907 case C_CAN_ERROR_PASSIVE: 908 /* error passive state */ 909 cf->can_id |= CAN_ERR_CRTL; 910 if (rx_err_passive) 911 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 912 if (bec.txerr > 127) 913 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 914 915 cf->data[6] = bec.txerr; 916 cf->data[7] = bec.rxerr; 917 break; 918 case C_CAN_BUS_OFF: 919 /* bus-off state */ 920 cf->can_id |= CAN_ERR_BUSOFF; 921 can_bus_off(dev); 922 break; 923 default: 924 break; 925 } 926 927 stats->rx_packets++; 928 stats->rx_bytes += cf->can_dlc; 929 netif_receive_skb(skb); 930 931 return 1; 932} 933 934static int c_can_handle_bus_err(struct net_device *dev, 935 enum c_can_lec_type lec_type) 936{ 937 struct c_can_priv *priv = netdev_priv(dev); 938 struct net_device_stats *stats = &dev->stats; 939 struct can_frame *cf; 940 struct sk_buff *skb; 941 942 /* 943 * early exit if no lec update or no error. 944 * no lec update means that no CAN bus event has been detected 945 * since CPU wrote 0x7 value to status reg. 946 */ 947 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 948 return 0; 949 950 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 951 return 0; 952 953 /* common for all type of bus errors */ 954 priv->can.can_stats.bus_error++; 955 stats->rx_errors++; 956 957 /* propagate the error condition to the CAN stack */ 958 skb = alloc_can_err_skb(dev, &cf); 959 if (unlikely(!skb)) 960 return 0; 961 962 /* 963 * check for 'last error code' which tells us the 964 * type of the last error to occur on the CAN bus 965 */ 966 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 967 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 968 969 switch (lec_type) { 970 case LEC_STUFF_ERROR: 971 netdev_dbg(dev, "stuff error\n"); 972 cf->data[2] |= CAN_ERR_PROT_STUFF; 973 break; 974 case LEC_FORM_ERROR: 975 netdev_dbg(dev, "form error\n"); 976 cf->data[2] |= CAN_ERR_PROT_FORM; 977 break; 978 case LEC_ACK_ERROR: 979 netdev_dbg(dev, "ack error\n"); 980 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 981 CAN_ERR_PROT_LOC_ACK_DEL); 982 break; 983 case LEC_BIT1_ERROR: 984 netdev_dbg(dev, "bit1 error\n"); 985 cf->data[2] |= CAN_ERR_PROT_BIT1; 986 break; 987 case LEC_BIT0_ERROR: 988 netdev_dbg(dev, "bit0 error\n"); 989 cf->data[2] |= CAN_ERR_PROT_BIT0; 990 break; 991 case LEC_CRC_ERROR: 992 netdev_dbg(dev, "CRC error\n"); 993 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 994 CAN_ERR_PROT_LOC_CRC_DEL); 995 break; 996 default: 997 break; 998 } 999 1000 stats->rx_packets++; 1001 stats->rx_bytes += cf->can_dlc; 1002 netif_receive_skb(skb); 1003 return 1; 1004} 1005 1006static int c_can_poll(struct napi_struct *napi, int quota) 1007{ 1008 struct net_device *dev = napi->dev; 1009 struct c_can_priv *priv = netdev_priv(dev); 1010 u16 curr, last = priv->last_status; 1011 int work_done = 0; 1012 1013 priv->last_status = curr = priv->read_reg(priv, C_CAN_STS_REG); 1014 /* Ack status on C_CAN. D_CAN is self clearing */ 1015 if (priv->type != BOSCH_D_CAN) 1016 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1017 1018 /* handle state changes */ 1019 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) { 1020 netdev_dbg(dev, "entered error warning state\n"); 1021 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); 1022 } 1023 1024 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) { 1025 netdev_dbg(dev, "entered error passive state\n"); 1026 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); 1027 } 1028 1029 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) { 1030 netdev_dbg(dev, "entered bus off state\n"); 1031 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF); 1032 goto end; 1033 } 1034 1035 /* handle bus recovery events */ 1036 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) { 1037 netdev_dbg(dev, "left bus off state\n"); 1038 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1039 } 1040 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) { 1041 netdev_dbg(dev, "left error passive state\n"); 1042 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1043 } 1044 1045 /* handle lec errors on the bus */ 1046 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK); 1047 1048 /* Handle Tx/Rx events. We do this unconditionally */ 1049 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1050 c_can_do_tx(dev); 1051 1052end: 1053 if (work_done < quota) { 1054 napi_complete(napi); 1055 /* enable all IRQs if we are not in bus off state */ 1056 if (priv->can.state != CAN_STATE_BUS_OFF) 1057 c_can_irq_control(priv, true); 1058 } 1059 1060 return work_done; 1061} 1062 1063static irqreturn_t c_can_isr(int irq, void *dev_id) 1064{ 1065 struct net_device *dev = (struct net_device *)dev_id; 1066 struct c_can_priv *priv = netdev_priv(dev); 1067 1068 if (!priv->read_reg(priv, C_CAN_INT_REG)) 1069 return IRQ_NONE; 1070 1071 /* disable all interrupts and schedule the NAPI */ 1072 c_can_irq_control(priv, false); 1073 napi_schedule(&priv->napi); 1074 1075 return IRQ_HANDLED; 1076} 1077 1078static int c_can_open(struct net_device *dev) 1079{ 1080 int err; 1081 struct c_can_priv *priv = netdev_priv(dev); 1082 1083 c_can_pm_runtime_get_sync(priv); 1084 c_can_reset_ram(priv, true); 1085 1086 /* open the can device */ 1087 err = open_candev(dev); 1088 if (err) { 1089 netdev_err(dev, "failed to open can device\n"); 1090 goto exit_open_fail; 1091 } 1092 1093 /* register interrupt handler */ 1094 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1095 dev); 1096 if (err < 0) { 1097 netdev_err(dev, "failed to request interrupt\n"); 1098 goto exit_irq_fail; 1099 } 1100 1101 /* start the c_can controller */ 1102 err = c_can_start(dev); 1103 if (err) 1104 goto exit_start_fail; 1105 1106 can_led_event(dev, CAN_LED_EVENT_OPEN); 1107 1108 napi_enable(&priv->napi); 1109 /* enable status change, error and module interrupts */ 1110 c_can_irq_control(priv, true); 1111 netif_start_queue(dev); 1112 1113 return 0; 1114 1115exit_start_fail: 1116 free_irq(dev->irq, dev); 1117exit_irq_fail: 1118 close_candev(dev); 1119exit_open_fail: 1120 c_can_reset_ram(priv, false); 1121 c_can_pm_runtime_put_sync(priv); 1122 return err; 1123} 1124 1125static int c_can_close(struct net_device *dev) 1126{ 1127 struct c_can_priv *priv = netdev_priv(dev); 1128 1129 netif_stop_queue(dev); 1130 napi_disable(&priv->napi); 1131 c_can_stop(dev); 1132 free_irq(dev->irq, dev); 1133 close_candev(dev); 1134 1135 c_can_reset_ram(priv, false); 1136 c_can_pm_runtime_put_sync(priv); 1137 1138 can_led_event(dev, CAN_LED_EVENT_STOP); 1139 1140 return 0; 1141} 1142 1143struct net_device *alloc_c_can_dev(void) 1144{ 1145 struct net_device *dev; 1146 struct c_can_priv *priv; 1147 1148 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1149 if (!dev) 1150 return NULL; 1151 1152 priv = netdev_priv(dev); 1153 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1154 1155 priv->dev = dev; 1156 priv->can.bittiming_const = &c_can_bittiming_const; 1157 priv->can.do_set_mode = c_can_set_mode; 1158 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1159 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1160 CAN_CTRLMODE_LISTENONLY | 1161 CAN_CTRLMODE_BERR_REPORTING; 1162 1163 return dev; 1164} 1165EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1166 1167#ifdef CONFIG_PM 1168int c_can_power_down(struct net_device *dev) 1169{ 1170 u32 val; 1171 unsigned long time_out; 1172 struct c_can_priv *priv = netdev_priv(dev); 1173 1174 if (!(dev->flags & IFF_UP)) 1175 return 0; 1176 1177 WARN_ON(priv->type != BOSCH_D_CAN); 1178 1179 /* set PDR value so the device goes to power down mode */ 1180 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1181 val |= CONTROL_EX_PDR; 1182 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1183 1184 /* Wait for the PDA bit to get set */ 1185 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1186 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1187 time_after(time_out, jiffies)) 1188 cpu_relax(); 1189 1190 if (time_after(jiffies, time_out)) 1191 return -ETIMEDOUT; 1192 1193 c_can_stop(dev); 1194 1195 c_can_reset_ram(priv, false); 1196 c_can_pm_runtime_put_sync(priv); 1197 1198 return 0; 1199} 1200EXPORT_SYMBOL_GPL(c_can_power_down); 1201 1202int c_can_power_up(struct net_device *dev) 1203{ 1204 u32 val; 1205 unsigned long time_out; 1206 struct c_can_priv *priv = netdev_priv(dev); 1207 int ret; 1208 1209 if (!(dev->flags & IFF_UP)) 1210 return 0; 1211 1212 WARN_ON(priv->type != BOSCH_D_CAN); 1213 1214 c_can_pm_runtime_get_sync(priv); 1215 c_can_reset_ram(priv, true); 1216 1217 /* Clear PDR and INIT bits */ 1218 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1219 val &= ~CONTROL_EX_PDR; 1220 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1221 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1222 val &= ~CONTROL_INIT; 1223 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1224 1225 /* Wait for the PDA bit to get clear */ 1226 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1227 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1228 time_after(time_out, jiffies)) 1229 cpu_relax(); 1230 1231 if (time_after(jiffies, time_out)) 1232 return -ETIMEDOUT; 1233 1234 ret = c_can_start(dev); 1235 if (!ret) 1236 c_can_irq_control(priv, true); 1237 1238 return ret; 1239} 1240EXPORT_SYMBOL_GPL(c_can_power_up); 1241#endif 1242 1243void free_c_can_dev(struct net_device *dev) 1244{ 1245 struct c_can_priv *priv = netdev_priv(dev); 1246 1247 netif_napi_del(&priv->napi); 1248 free_candev(dev); 1249} 1250EXPORT_SYMBOL_GPL(free_c_can_dev); 1251 1252static const struct net_device_ops c_can_netdev_ops = { 1253 .ndo_open = c_can_open, 1254 .ndo_stop = c_can_close, 1255 .ndo_start_xmit = c_can_start_xmit, 1256 .ndo_change_mtu = can_change_mtu, 1257}; 1258 1259int register_c_can_dev(struct net_device *dev) 1260{ 1261 struct c_can_priv *priv = netdev_priv(dev); 1262 int err; 1263 1264 c_can_pm_runtime_enable(priv); 1265 1266 dev->flags |= IFF_ECHO; /* we support local echo */ 1267 dev->netdev_ops = &c_can_netdev_ops; 1268 1269 err = register_candev(dev); 1270 if (err) 1271 c_can_pm_runtime_disable(priv); 1272 else 1273 devm_can_led_init(dev); 1274 1275 return err; 1276} 1277EXPORT_SYMBOL_GPL(register_c_can_dev); 1278 1279void unregister_c_can_dev(struct net_device *dev) 1280{ 1281 struct c_can_priv *priv = netdev_priv(dev); 1282 1283 unregister_candev(dev); 1284 1285 c_can_pm_runtime_disable(priv); 1286} 1287EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1288 1289MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1290MODULE_LICENSE("GPL v2"); 1291MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1292