c_can.c revision 4cdd34b26826e89972c03043987b83f76e7ad510
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42 43#include "c_can.h" 44 45/* Number of interface registers */ 46#define IF_ENUM_REG_LEN 11 47#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 48 49/* control register */ 50#define CONTROL_TEST BIT(7) 51#define CONTROL_CCE BIT(6) 52#define CONTROL_DISABLE_AR BIT(5) 53#define CONTROL_ENABLE_AR (0 << 5) 54#define CONTROL_EIE BIT(3) 55#define CONTROL_SIE BIT(2) 56#define CONTROL_IE BIT(1) 57#define CONTROL_INIT BIT(0) 58 59/* test register */ 60#define TEST_RX BIT(7) 61#define TEST_TX1 BIT(6) 62#define TEST_TX2 BIT(5) 63#define TEST_LBACK BIT(4) 64#define TEST_SILENT BIT(3) 65#define TEST_BASIC BIT(2) 66 67/* status register */ 68#define STATUS_BOFF BIT(7) 69#define STATUS_EWARN BIT(6) 70#define STATUS_EPASS BIT(5) 71#define STATUS_RXOK BIT(4) 72#define STATUS_TXOK BIT(3) 73 74/* error counter register */ 75#define ERR_CNT_TEC_MASK 0xff 76#define ERR_CNT_TEC_SHIFT 0 77#define ERR_CNT_REC_SHIFT 8 78#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 79#define ERR_CNT_RP_SHIFT 15 80#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 81 82/* bit-timing register */ 83#define BTR_BRP_MASK 0x3f 84#define BTR_BRP_SHIFT 0 85#define BTR_SJW_SHIFT 6 86#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 87#define BTR_TSEG1_SHIFT 8 88#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 89#define BTR_TSEG2_SHIFT 12 90#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 91 92/* brp extension register */ 93#define BRP_EXT_BRPE_MASK 0x0f 94#define BRP_EXT_BRPE_SHIFT 0 95 96/* IFx command request */ 97#define IF_COMR_BUSY BIT(15) 98 99/* IFx command mask */ 100#define IF_COMM_WR BIT(7) 101#define IF_COMM_MASK BIT(6) 102#define IF_COMM_ARB BIT(5) 103#define IF_COMM_CONTROL BIT(4) 104#define IF_COMM_CLR_INT_PND BIT(3) 105#define IF_COMM_TXRQST BIT(2) 106#define IF_COMM_DATAA BIT(1) 107#define IF_COMM_DATAB BIT(0) 108#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ 109 IF_COMM_CONTROL | IF_COMM_TXRQST | \ 110 IF_COMM_DATAA | IF_COMM_DATAB) 111 112/* IFx arbitration */ 113#define IF_ARB_MSGVAL BIT(15) 114#define IF_ARB_MSGXTD BIT(14) 115#define IF_ARB_TRANSMIT BIT(13) 116 117/* IFx message control */ 118#define IF_MCONT_NEWDAT BIT(15) 119#define IF_MCONT_MSGLST BIT(14) 120#define IF_MCONT_CLR_MSGLST (0 << 14) 121#define IF_MCONT_INTPND BIT(13) 122#define IF_MCONT_UMASK BIT(12) 123#define IF_MCONT_TXIE BIT(11) 124#define IF_MCONT_RXIE BIT(10) 125#define IF_MCONT_RMTEN BIT(9) 126#define IF_MCONT_TXRQST BIT(8) 127#define IF_MCONT_EOB BIT(7) 128#define IF_MCONT_DLC_MASK 0xf 129 130/* 131 * IFx register masks: 132 * allow easy operation on 16-bit registers when the 133 * argument is 32-bit instead 134 */ 135#define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF) 136#define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16) 137 138/* message object split */ 139#define C_CAN_NO_OF_OBJECTS 32 140#define C_CAN_MSG_OBJ_RX_NUM 16 141#define C_CAN_MSG_OBJ_TX_NUM 16 142 143#define C_CAN_MSG_OBJ_RX_FIRST 1 144#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \ 145 C_CAN_MSG_OBJ_RX_NUM - 1) 146 147#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1) 148#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \ 149 C_CAN_MSG_OBJ_TX_NUM - 1) 150 151#define C_CAN_MSG_OBJ_RX_SPLIT 9 152#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1) 153 154#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1) 155#define RECEIVE_OBJECT_BITS 0x0000ffff 156 157/* status interrupt */ 158#define STATUS_INTERRUPT 0x8000 159 160/* global interrupt masks */ 161#define ENABLE_ALL_INTERRUPTS 1 162#define DISABLE_ALL_INTERRUPTS 0 163 164/* minimum timeout for checking BUSY status */ 165#define MIN_TIMEOUT_VALUE 6 166 167/* napi related */ 168#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 169 170/* c_can lec values */ 171enum c_can_lec_type { 172 LEC_NO_ERROR = 0, 173 LEC_STUFF_ERROR, 174 LEC_FORM_ERROR, 175 LEC_ACK_ERROR, 176 LEC_BIT1_ERROR, 177 LEC_BIT0_ERROR, 178 LEC_CRC_ERROR, 179 LEC_UNUSED, 180}; 181 182/* 183 * c_can error types: 184 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 185 */ 186enum c_can_bus_error_types { 187 C_CAN_NO_ERROR = 0, 188 C_CAN_BUS_OFF, 189 C_CAN_ERROR_WARNING, 190 C_CAN_ERROR_PASSIVE, 191}; 192 193static const struct can_bittiming_const c_can_bittiming_const = { 194 .name = KBUILD_MODNAME, 195 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 196 .tseg1_max = 16, 197 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 198 .tseg2_max = 8, 199 .sjw_max = 4, 200 .brp_min = 1, 201 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 202 .brp_inc = 1, 203}; 204 205static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 206{ 207 if (priv->device) 208 pm_runtime_enable(priv->device); 209} 210 211static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 212{ 213 if (priv->device) 214 pm_runtime_disable(priv->device); 215} 216 217static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 218{ 219 if (priv->device) 220 pm_runtime_get_sync(priv->device); 221} 222 223static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 224{ 225 if (priv->device) 226 pm_runtime_put_sync(priv->device); 227} 228 229static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 230{ 231 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + 232 C_CAN_MSG_OBJ_TX_FIRST; 233} 234 235static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv) 236{ 237 return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) + 238 C_CAN_MSG_OBJ_TX_FIRST; 239} 240 241static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) 242{ 243 u32 val = priv->read_reg(priv, index); 244 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 245 return val; 246} 247 248static void c_can_enable_all_interrupts(struct c_can_priv *priv, 249 int enable) 250{ 251 unsigned int cntrl_save = priv->read_reg(priv, 252 C_CAN_CTRL_REG); 253 254 if (enable) 255 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 256 else 257 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); 258 259 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); 260} 261 262static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 263{ 264 int count = MIN_TIMEOUT_VALUE; 265 266 while (count && priv->read_reg(priv, 267 C_CAN_IFACE(COMREQ_REG, iface)) & 268 IF_COMR_BUSY) { 269 count--; 270 udelay(1); 271 } 272 273 if (!count) 274 return 1; 275 276 return 0; 277} 278 279static inline void c_can_object_get(struct net_device *dev, 280 int iface, int objno, int mask) 281{ 282 struct c_can_priv *priv = netdev_priv(dev); 283 284 /* 285 * As per specs, after writting the message object number in the 286 * IF command request register the transfer b/w interface 287 * register and message RAM must be complete in 6 CAN-CLK 288 * period. 289 */ 290 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 291 IFX_WRITE_LOW_16BIT(mask)); 292 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 293 IFX_WRITE_LOW_16BIT(objno)); 294 295 if (c_can_msg_obj_is_busy(priv, iface)) 296 netdev_err(dev, "timed out in object get\n"); 297} 298 299static inline void c_can_object_put(struct net_device *dev, 300 int iface, int objno, int mask) 301{ 302 struct c_can_priv *priv = netdev_priv(dev); 303 304 /* 305 * As per specs, after writting the message object number in the 306 * IF command request register the transfer b/w interface 307 * register and message RAM must be complete in 6 CAN-CLK 308 * period. 309 */ 310 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 311 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); 312 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 313 IFX_WRITE_LOW_16BIT(objno)); 314 315 if (c_can_msg_obj_is_busy(priv, iface)) 316 netdev_err(dev, "timed out in object put\n"); 317} 318 319static void c_can_write_msg_object(struct net_device *dev, 320 int iface, struct can_frame *frame, int objno) 321{ 322 int i; 323 u16 flags = 0; 324 unsigned int id; 325 struct c_can_priv *priv = netdev_priv(dev); 326 327 if (!(frame->can_id & CAN_RTR_FLAG)) 328 flags |= IF_ARB_TRANSMIT; 329 330 if (frame->can_id & CAN_EFF_FLAG) { 331 id = frame->can_id & CAN_EFF_MASK; 332 flags |= IF_ARB_MSGXTD; 333 } else 334 id = ((frame->can_id & CAN_SFF_MASK) << 18); 335 336 flags |= IF_ARB_MSGVAL; 337 338 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 339 IFX_WRITE_LOW_16BIT(id)); 340 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | 341 IFX_WRITE_HIGH_16BIT(id)); 342 343 for (i = 0; i < frame->can_dlc; i += 2) { 344 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 345 frame->data[i] | (frame->data[i + 1] << 8)); 346 } 347 348 /* enable interrupt for this message object */ 349 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 350 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | 351 frame->can_dlc); 352 c_can_object_put(dev, iface, objno, IF_COMM_ALL); 353} 354 355static inline void c_can_mark_rx_msg_obj(struct net_device *dev, 356 int iface, int ctrl_mask, 357 int obj) 358{ 359 struct c_can_priv *priv = netdev_priv(dev); 360 361 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 362 ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND)); 363 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); 364 365} 366 367static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 368 int iface, 369 int ctrl_mask) 370{ 371 int i; 372 struct c_can_priv *priv = netdev_priv(dev); 373 374 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { 375 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 376 ctrl_mask & ~(IF_MCONT_MSGLST | 377 IF_MCONT_INTPND | IF_MCONT_NEWDAT)); 378 c_can_object_put(dev, iface, i, IF_COMM_CONTROL); 379 } 380} 381 382static inline void c_can_activate_rx_msg_obj(struct net_device *dev, 383 int iface, int ctrl_mask, 384 int obj) 385{ 386 struct c_can_priv *priv = netdev_priv(dev); 387 388 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 389 ctrl_mask & ~(IF_MCONT_MSGLST | 390 IF_MCONT_INTPND | IF_MCONT_NEWDAT)); 391 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); 392} 393 394static void c_can_handle_lost_msg_obj(struct net_device *dev, 395 int iface, int objno) 396{ 397 struct c_can_priv *priv = netdev_priv(dev); 398 struct net_device_stats *stats = &dev->stats; 399 struct sk_buff *skb; 400 struct can_frame *frame; 401 402 netdev_err(dev, "msg lost in buffer %d\n", objno); 403 404 c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 405 406 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 407 IF_MCONT_CLR_MSGLST); 408 409 c_can_object_put(dev, 0, objno, IF_COMM_CONTROL); 410 411 /* create an error msg */ 412 skb = alloc_can_err_skb(dev, &frame); 413 if (unlikely(!skb)) 414 return; 415 416 frame->can_id |= CAN_ERR_CRTL; 417 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 418 stats->rx_errors++; 419 stats->rx_over_errors++; 420 421 netif_receive_skb(skb); 422} 423 424static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) 425{ 426 u16 flags, data; 427 int i; 428 unsigned int val; 429 struct c_can_priv *priv = netdev_priv(dev); 430 struct net_device_stats *stats = &dev->stats; 431 struct sk_buff *skb; 432 struct can_frame *frame; 433 434 skb = alloc_can_skb(dev, &frame); 435 if (!skb) { 436 stats->rx_dropped++; 437 return -ENOMEM; 438 } 439 440 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 441 442 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); 443 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | 444 (flags << 16); 445 446 if (flags & IF_ARB_MSGXTD) 447 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; 448 else 449 frame->can_id = (val >> 18) & CAN_SFF_MASK; 450 451 if (flags & IF_ARB_TRANSMIT) 452 frame->can_id |= CAN_RTR_FLAG; 453 else { 454 for (i = 0; i < frame->can_dlc; i += 2) { 455 data = priv->read_reg(priv, 456 C_CAN_IFACE(DATA1_REG, iface) + i / 2); 457 frame->data[i] = data; 458 frame->data[i + 1] = data >> 8; 459 } 460 } 461 462 netif_receive_skb(skb); 463 464 stats->rx_packets++; 465 stats->rx_bytes += frame->can_dlc; 466 467 return 0; 468} 469 470static void c_can_setup_receive_object(struct net_device *dev, int iface, 471 int objno, unsigned int mask, 472 unsigned int id, unsigned int mcont) 473{ 474 struct c_can_priv *priv = netdev_priv(dev); 475 476 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), 477 IFX_WRITE_LOW_16BIT(mask)); 478 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), 479 IFX_WRITE_HIGH_16BIT(mask)); 480 481 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 482 IFX_WRITE_LOW_16BIT(id)); 483 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 484 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); 485 486 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 487 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 488 489 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 490 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 491} 492 493static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) 494{ 495 struct c_can_priv *priv = netdev_priv(dev); 496 497 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 498 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 499 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 500 501 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); 502 503 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 504 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 505} 506 507static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 508{ 509 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 510 511 /* 512 * as transmission request register's bit n-1 corresponds to 513 * message object n, we need to handle the same properly. 514 */ 515 if (val & (1 << (objno - 1))) 516 return 1; 517 518 return 0; 519} 520 521static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 522 struct net_device *dev) 523{ 524 u32 msg_obj_no; 525 struct c_can_priv *priv = netdev_priv(dev); 526 struct can_frame *frame = (struct can_frame *)skb->data; 527 528 if (can_dropped_invalid_skb(dev, skb)) 529 return NETDEV_TX_OK; 530 531 msg_obj_no = get_tx_next_msg_obj(priv); 532 533 /* prepare message object for transmission */ 534 c_can_write_msg_object(dev, 0, frame, msg_obj_no); 535 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 536 537 /* 538 * we have to stop the queue in case of a wrap around or 539 * if the next TX message object is still in use 540 */ 541 priv->tx_next++; 542 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 543 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 544 netif_stop_queue(dev); 545 546 return NETDEV_TX_OK; 547} 548 549static int c_can_set_bittiming(struct net_device *dev) 550{ 551 unsigned int reg_btr, reg_brpe, ctrl_save; 552 u8 brp, brpe, sjw, tseg1, tseg2; 553 u32 ten_bit_brp; 554 struct c_can_priv *priv = netdev_priv(dev); 555 const struct can_bittiming *bt = &priv->can.bittiming; 556 557 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 558 ten_bit_brp = bt->brp - 1; 559 brp = ten_bit_brp & BTR_BRP_MASK; 560 brpe = ten_bit_brp >> 6; 561 562 sjw = bt->sjw - 1; 563 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 564 tseg2 = bt->phase_seg2 - 1; 565 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 566 (tseg2 << BTR_TSEG2_SHIFT); 567 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 568 569 netdev_info(dev, 570 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 571 572 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 573 priv->write_reg(priv, C_CAN_CTRL_REG, 574 ctrl_save | CONTROL_CCE | CONTROL_INIT); 575 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 576 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 577 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 578 579 return 0; 580} 581 582/* 583 * Configure C_CAN message objects for Tx and Rx purposes: 584 * C_CAN provides a total of 32 message objects that can be configured 585 * either for Tx or Rx purposes. Here the first 16 message objects are used as 586 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 587 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 588 * See user guide document for further details on configuring message 589 * objects. 590 */ 591static void c_can_configure_msg_objects(struct net_device *dev) 592{ 593 int i; 594 595 /* first invalidate all message objects */ 596 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 597 c_can_inval_msg_object(dev, 0, i); 598 599 /* setup receive message objects */ 600 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 601 c_can_setup_receive_object(dev, 0, i, 0, 0, 602 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); 603 604 c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 605 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); 606} 607 608/* 609 * Configure C_CAN chip: 610 * - enable/disable auto-retransmission 611 * - set operating mode 612 * - configure message objects 613 */ 614static void c_can_chip_config(struct net_device *dev) 615{ 616 struct c_can_priv *priv = netdev_priv(dev); 617 618 /* enable automatic retransmission */ 619 priv->write_reg(priv, C_CAN_CTRL_REG, 620 CONTROL_ENABLE_AR); 621 622 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 623 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 624 /* loopback + silent mode : useful for hot self-test */ 625 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 626 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 627 priv->write_reg(priv, C_CAN_TEST_REG, 628 TEST_LBACK | TEST_SILENT); 629 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 630 /* loopback mode : useful for self-test function */ 631 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 632 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 633 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 634 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 635 /* silent mode : bus-monitoring mode */ 636 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 637 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 638 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 639 } else 640 /* normal mode*/ 641 priv->write_reg(priv, C_CAN_CTRL_REG, 642 CONTROL_EIE | CONTROL_SIE | CONTROL_IE); 643 644 /* configure message objects */ 645 c_can_configure_msg_objects(dev); 646 647 /* set a `lec` value so that we can check for updates later */ 648 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 649 650 /* set bittiming params */ 651 c_can_set_bittiming(dev); 652} 653 654static void c_can_start(struct net_device *dev) 655{ 656 struct c_can_priv *priv = netdev_priv(dev); 657 658 /* basic c_can configuration */ 659 c_can_chip_config(dev); 660 661 priv->can.state = CAN_STATE_ERROR_ACTIVE; 662 663 /* reset tx helper pointers */ 664 priv->tx_next = priv->tx_echo = 0; 665 666 /* enable status change, error and module interrupts */ 667 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 668} 669 670static void c_can_stop(struct net_device *dev) 671{ 672 struct c_can_priv *priv = netdev_priv(dev); 673 674 /* disable all interrupts */ 675 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 676 677 /* set the state as STOPPED */ 678 priv->can.state = CAN_STATE_STOPPED; 679} 680 681static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 682{ 683 switch (mode) { 684 case CAN_MODE_START: 685 c_can_start(dev); 686 netif_wake_queue(dev); 687 break; 688 default: 689 return -EOPNOTSUPP; 690 } 691 692 return 0; 693} 694 695static int c_can_get_berr_counter(const struct net_device *dev, 696 struct can_berr_counter *bec) 697{ 698 unsigned int reg_err_counter; 699 struct c_can_priv *priv = netdev_priv(dev); 700 701 c_can_pm_runtime_get_sync(priv); 702 703 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 704 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 705 ERR_CNT_REC_SHIFT; 706 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 707 708 c_can_pm_runtime_put_sync(priv); 709 710 return 0; 711} 712 713/* 714 * theory of operation: 715 * 716 * priv->tx_echo holds the number of the oldest can_frame put for 717 * transmission into the hardware, but not yet ACKed by the CAN tx 718 * complete IRQ. 719 * 720 * We iterate from priv->tx_echo to priv->tx_next and check if the 721 * packet has been transmitted, echo it back to the CAN framework. 722 * If we discover a not yet transmitted packet, stop looking for more. 723 */ 724static void c_can_do_tx(struct net_device *dev) 725{ 726 u32 val; 727 u32 msg_obj_no; 728 struct c_can_priv *priv = netdev_priv(dev); 729 struct net_device_stats *stats = &dev->stats; 730 731 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 732 msg_obj_no = get_tx_echo_msg_obj(priv); 733 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 734 if (!(val & (1 << (msg_obj_no - 1)))) { 735 can_get_echo_skb(dev, 736 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 737 stats->tx_bytes += priv->read_reg(priv, 738 C_CAN_IFACE(MSGCTRL_REG, 0)) 739 & IF_MCONT_DLC_MASK; 740 stats->tx_packets++; 741 c_can_inval_msg_object(dev, 0, msg_obj_no); 742 } else { 743 break; 744 } 745 } 746 747 /* restart queue if wrap-up or if queue stalled on last pkt */ 748 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 749 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) 750 netif_wake_queue(dev); 751} 752 753/* 754 * theory of operation: 755 * 756 * c_can core saves a received CAN message into the first free message 757 * object it finds free (starting with the lowest). Bits NEWDAT and 758 * INTPND are set for this message object indicating that a new message 759 * has arrived. To work-around this issue, we keep two groups of message 760 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 761 * 762 * To ensure in-order frame reception we use the following 763 * approach while re-activating a message object to receive further 764 * frames: 765 * - if the current message object number is lower than 766 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 767 * the INTPND bit. 768 * - if the current message object number is equal to 769 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 770 * receive message objects. 771 * - if the current message object number is greater than 772 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 773 * only this message object. 774 */ 775static int c_can_do_rx_poll(struct net_device *dev, int quota) 776{ 777 u32 num_rx_pkts = 0; 778 unsigned int msg_obj, msg_ctrl_save; 779 struct c_can_priv *priv = netdev_priv(dev); 780 u32 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG); 781 782 for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST; 783 msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0; 784 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG), 785 msg_obj++) { 786 /* 787 * as interrupt pending register's bit n-1 corresponds to 788 * message object n, we need to handle the same properly. 789 */ 790 if (val & (1 << (msg_obj - 1))) { 791 c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL & 792 ~IF_COMM_TXRQST); 793 msg_ctrl_save = priv->read_reg(priv, 794 C_CAN_IFACE(MSGCTRL_REG, 0)); 795 796 if (msg_ctrl_save & IF_MCONT_EOB) 797 return num_rx_pkts; 798 799 if (msg_ctrl_save & IF_MCONT_MSGLST) { 800 c_can_handle_lost_msg_obj(dev, 0, msg_obj); 801 num_rx_pkts++; 802 quota--; 803 continue; 804 } 805 806 if (!(msg_ctrl_save & IF_MCONT_NEWDAT)) 807 continue; 808 809 /* read the data from the message object */ 810 c_can_read_msg_object(dev, 0, msg_ctrl_save); 811 812 if (msg_obj < C_CAN_MSG_RX_LOW_LAST) 813 c_can_mark_rx_msg_obj(dev, 0, 814 msg_ctrl_save, msg_obj); 815 else if (msg_obj > C_CAN_MSG_RX_LOW_LAST) 816 /* activate this msg obj */ 817 c_can_activate_rx_msg_obj(dev, 0, 818 msg_ctrl_save, msg_obj); 819 else if (msg_obj == C_CAN_MSG_RX_LOW_LAST) 820 /* activate all lower message objects */ 821 c_can_activate_all_lower_rx_msg_obj(dev, 822 0, msg_ctrl_save); 823 824 num_rx_pkts++; 825 quota--; 826 } 827 } 828 829 return num_rx_pkts; 830} 831 832static inline int c_can_has_and_handle_berr(struct c_can_priv *priv) 833{ 834 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 835 (priv->current_status & LEC_UNUSED); 836} 837 838static int c_can_handle_state_change(struct net_device *dev, 839 enum c_can_bus_error_types error_type) 840{ 841 unsigned int reg_err_counter; 842 unsigned int rx_err_passive; 843 struct c_can_priv *priv = netdev_priv(dev); 844 struct net_device_stats *stats = &dev->stats; 845 struct can_frame *cf; 846 struct sk_buff *skb; 847 struct can_berr_counter bec; 848 849 /* propagate the error condition to the CAN stack */ 850 skb = alloc_can_err_skb(dev, &cf); 851 if (unlikely(!skb)) 852 return 0; 853 854 c_can_get_berr_counter(dev, &bec); 855 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 856 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 857 ERR_CNT_RP_SHIFT; 858 859 switch (error_type) { 860 case C_CAN_ERROR_WARNING: 861 /* error warning state */ 862 priv->can.can_stats.error_warning++; 863 priv->can.state = CAN_STATE_ERROR_WARNING; 864 cf->can_id |= CAN_ERR_CRTL; 865 cf->data[1] = (bec.txerr > bec.rxerr) ? 866 CAN_ERR_CRTL_TX_WARNING : 867 CAN_ERR_CRTL_RX_WARNING; 868 cf->data[6] = bec.txerr; 869 cf->data[7] = bec.rxerr; 870 871 break; 872 case C_CAN_ERROR_PASSIVE: 873 /* error passive state */ 874 priv->can.can_stats.error_passive++; 875 priv->can.state = CAN_STATE_ERROR_PASSIVE; 876 cf->can_id |= CAN_ERR_CRTL; 877 if (rx_err_passive) 878 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 879 if (bec.txerr > 127) 880 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 881 882 cf->data[6] = bec.txerr; 883 cf->data[7] = bec.rxerr; 884 break; 885 case C_CAN_BUS_OFF: 886 /* bus-off state */ 887 priv->can.state = CAN_STATE_BUS_OFF; 888 cf->can_id |= CAN_ERR_BUSOFF; 889 /* 890 * disable all interrupts in bus-off mode to ensure that 891 * the CPU is not hogged down 892 */ 893 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 894 can_bus_off(dev); 895 break; 896 default: 897 break; 898 } 899 900 netif_receive_skb(skb); 901 stats->rx_packets++; 902 stats->rx_bytes += cf->can_dlc; 903 904 return 1; 905} 906 907static int c_can_handle_bus_err(struct net_device *dev, 908 enum c_can_lec_type lec_type) 909{ 910 struct c_can_priv *priv = netdev_priv(dev); 911 struct net_device_stats *stats = &dev->stats; 912 struct can_frame *cf; 913 struct sk_buff *skb; 914 915 /* 916 * early exit if no lec update or no error. 917 * no lec update means that no CAN bus event has been detected 918 * since CPU wrote 0x7 value to status reg. 919 */ 920 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 921 return 0; 922 923 /* propagate the error condition to the CAN stack */ 924 skb = alloc_can_err_skb(dev, &cf); 925 if (unlikely(!skb)) 926 return 0; 927 928 /* 929 * check for 'last error code' which tells us the 930 * type of the last error to occur on the CAN bus 931 */ 932 933 /* common for all type of bus errors */ 934 priv->can.can_stats.bus_error++; 935 stats->rx_errors++; 936 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 937 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 938 939 switch (lec_type) { 940 case LEC_STUFF_ERROR: 941 netdev_dbg(dev, "stuff error\n"); 942 cf->data[2] |= CAN_ERR_PROT_STUFF; 943 break; 944 case LEC_FORM_ERROR: 945 netdev_dbg(dev, "form error\n"); 946 cf->data[2] |= CAN_ERR_PROT_FORM; 947 break; 948 case LEC_ACK_ERROR: 949 netdev_dbg(dev, "ack error\n"); 950 cf->data[2] |= (CAN_ERR_PROT_LOC_ACK | 951 CAN_ERR_PROT_LOC_ACK_DEL); 952 break; 953 case LEC_BIT1_ERROR: 954 netdev_dbg(dev, "bit1 error\n"); 955 cf->data[2] |= CAN_ERR_PROT_BIT1; 956 break; 957 case LEC_BIT0_ERROR: 958 netdev_dbg(dev, "bit0 error\n"); 959 cf->data[2] |= CAN_ERR_PROT_BIT0; 960 break; 961 case LEC_CRC_ERROR: 962 netdev_dbg(dev, "CRC error\n"); 963 cf->data[2] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 964 CAN_ERR_PROT_LOC_CRC_DEL); 965 break; 966 default: 967 break; 968 } 969 970 /* set a `lec` value so that we can check for updates later */ 971 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 972 973 netif_receive_skb(skb); 974 stats->rx_packets++; 975 stats->rx_bytes += cf->can_dlc; 976 977 return 1; 978} 979 980static int c_can_poll(struct napi_struct *napi, int quota) 981{ 982 u16 irqstatus; 983 int lec_type = 0; 984 int work_done = 0; 985 struct net_device *dev = napi->dev; 986 struct c_can_priv *priv = netdev_priv(dev); 987 988 irqstatus = priv->irqstatus; 989 if (!irqstatus) 990 goto end; 991 992 /* status events have the highest priority */ 993 if (irqstatus == STATUS_INTERRUPT) { 994 priv->current_status = priv->read_reg(priv, 995 C_CAN_STS_REG); 996 997 /* handle Tx/Rx events */ 998 if (priv->current_status & STATUS_TXOK) 999 priv->write_reg(priv, C_CAN_STS_REG, 1000 priv->current_status & ~STATUS_TXOK); 1001 1002 if (priv->current_status & STATUS_RXOK) 1003 priv->write_reg(priv, C_CAN_STS_REG, 1004 priv->current_status & ~STATUS_RXOK); 1005 1006 /* handle state changes */ 1007 if ((priv->current_status & STATUS_EWARN) && 1008 (!(priv->last_status & STATUS_EWARN))) { 1009 netdev_dbg(dev, "entered error warning state\n"); 1010 work_done += c_can_handle_state_change(dev, 1011 C_CAN_ERROR_WARNING); 1012 } 1013 if ((priv->current_status & STATUS_EPASS) && 1014 (!(priv->last_status & STATUS_EPASS))) { 1015 netdev_dbg(dev, "entered error passive state\n"); 1016 work_done += c_can_handle_state_change(dev, 1017 C_CAN_ERROR_PASSIVE); 1018 } 1019 if ((priv->current_status & STATUS_BOFF) && 1020 (!(priv->last_status & STATUS_BOFF))) { 1021 netdev_dbg(dev, "entered bus off state\n"); 1022 work_done += c_can_handle_state_change(dev, 1023 C_CAN_BUS_OFF); 1024 } 1025 1026 /* handle bus recovery events */ 1027 if ((!(priv->current_status & STATUS_BOFF)) && 1028 (priv->last_status & STATUS_BOFF)) { 1029 netdev_dbg(dev, "left bus off state\n"); 1030 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1031 } 1032 if ((!(priv->current_status & STATUS_EPASS)) && 1033 (priv->last_status & STATUS_EPASS)) { 1034 netdev_dbg(dev, "left error passive state\n"); 1035 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1036 } 1037 1038 priv->last_status = priv->current_status; 1039 1040 /* handle lec errors on the bus */ 1041 lec_type = c_can_has_and_handle_berr(priv); 1042 if (lec_type) 1043 work_done += c_can_handle_bus_err(dev, lec_type); 1044 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && 1045 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { 1046 /* handle events corresponding to receive message objects */ 1047 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1048 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && 1049 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { 1050 /* handle events corresponding to transmit message objects */ 1051 c_can_do_tx(dev); 1052 } 1053 1054end: 1055 if (work_done < quota) { 1056 napi_complete(napi); 1057 /* enable all IRQs */ 1058 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1059 } 1060 1061 return work_done; 1062} 1063 1064static irqreturn_t c_can_isr(int irq, void *dev_id) 1065{ 1066 struct net_device *dev = (struct net_device *)dev_id; 1067 struct c_can_priv *priv = netdev_priv(dev); 1068 1069 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); 1070 if (!priv->irqstatus) 1071 return IRQ_NONE; 1072 1073 /* disable all interrupts and schedule the NAPI */ 1074 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1075 napi_schedule(&priv->napi); 1076 1077 return IRQ_HANDLED; 1078} 1079 1080static int c_can_open(struct net_device *dev) 1081{ 1082 int err; 1083 struct c_can_priv *priv = netdev_priv(dev); 1084 1085 c_can_pm_runtime_get_sync(priv); 1086 1087 /* open the can device */ 1088 err = open_candev(dev); 1089 if (err) { 1090 netdev_err(dev, "failed to open can device\n"); 1091 goto exit_open_fail; 1092 } 1093 1094 /* register interrupt handler */ 1095 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1096 dev); 1097 if (err < 0) { 1098 netdev_err(dev, "failed to request interrupt\n"); 1099 goto exit_irq_fail; 1100 } 1101 1102 napi_enable(&priv->napi); 1103 1104 /* start the c_can controller */ 1105 c_can_start(dev); 1106 1107 netif_start_queue(dev); 1108 1109 return 0; 1110 1111exit_irq_fail: 1112 close_candev(dev); 1113exit_open_fail: 1114 c_can_pm_runtime_put_sync(priv); 1115 return err; 1116} 1117 1118static int c_can_close(struct net_device *dev) 1119{ 1120 struct c_can_priv *priv = netdev_priv(dev); 1121 1122 netif_stop_queue(dev); 1123 napi_disable(&priv->napi); 1124 c_can_stop(dev); 1125 free_irq(dev->irq, dev); 1126 close_candev(dev); 1127 c_can_pm_runtime_put_sync(priv); 1128 1129 return 0; 1130} 1131 1132struct net_device *alloc_c_can_dev(void) 1133{ 1134 struct net_device *dev; 1135 struct c_can_priv *priv; 1136 1137 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1138 if (!dev) 1139 return NULL; 1140 1141 priv = netdev_priv(dev); 1142 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1143 1144 priv->dev = dev; 1145 priv->can.bittiming_const = &c_can_bittiming_const; 1146 priv->can.do_set_mode = c_can_set_mode; 1147 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1148 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1149 CAN_CTRLMODE_LISTENONLY | 1150 CAN_CTRLMODE_BERR_REPORTING; 1151 1152 return dev; 1153} 1154EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1155 1156void free_c_can_dev(struct net_device *dev) 1157{ 1158 free_candev(dev); 1159} 1160EXPORT_SYMBOL_GPL(free_c_can_dev); 1161 1162static const struct net_device_ops c_can_netdev_ops = { 1163 .ndo_open = c_can_open, 1164 .ndo_stop = c_can_close, 1165 .ndo_start_xmit = c_can_start_xmit, 1166}; 1167 1168int register_c_can_dev(struct net_device *dev) 1169{ 1170 struct c_can_priv *priv = netdev_priv(dev); 1171 int err; 1172 1173 c_can_pm_runtime_enable(priv); 1174 1175 dev->flags |= IFF_ECHO; /* we support local echo */ 1176 dev->netdev_ops = &c_can_netdev_ops; 1177 1178 err = register_candev(dev); 1179 if (err) 1180 c_can_pm_runtime_disable(priv); 1181 1182 return err; 1183} 1184EXPORT_SYMBOL_GPL(register_c_can_dev); 1185 1186void unregister_c_can_dev(struct net_device *dev) 1187{ 1188 struct c_can_priv *priv = netdev_priv(dev); 1189 1190 /* disable all interrupts */ 1191 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1192 1193 unregister_candev(dev); 1194 1195 c_can_pm_runtime_disable(priv); 1196} 1197EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1198 1199MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1200MODULE_LICENSE("GPL v2"); 1201MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1202