c_can.c revision 5090f805600ff7dccca358f9986a92dd34185326
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42#include <linux/can/led.h> 43 44#include "c_can.h" 45 46/* Number of interface registers */ 47#define IF_ENUM_REG_LEN 11 48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 49 50/* control extension register D_CAN specific */ 51#define CONTROL_EX_PDR BIT(8) 52 53/* control register */ 54#define CONTROL_TEST BIT(7) 55#define CONTROL_CCE BIT(6) 56#define CONTROL_DISABLE_AR BIT(5) 57#define CONTROL_ENABLE_AR (0 << 5) 58#define CONTROL_EIE BIT(3) 59#define CONTROL_SIE BIT(2) 60#define CONTROL_IE BIT(1) 61#define CONTROL_INIT BIT(0) 62 63/* test register */ 64#define TEST_RX BIT(7) 65#define TEST_TX1 BIT(6) 66#define TEST_TX2 BIT(5) 67#define TEST_LBACK BIT(4) 68#define TEST_SILENT BIT(3) 69#define TEST_BASIC BIT(2) 70 71/* status register */ 72#define STATUS_PDA BIT(10) 73#define STATUS_BOFF BIT(7) 74#define STATUS_EWARN BIT(6) 75#define STATUS_EPASS BIT(5) 76#define STATUS_RXOK BIT(4) 77#define STATUS_TXOK BIT(3) 78 79/* error counter register */ 80#define ERR_CNT_TEC_MASK 0xff 81#define ERR_CNT_TEC_SHIFT 0 82#define ERR_CNT_REC_SHIFT 8 83#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 84#define ERR_CNT_RP_SHIFT 15 85#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 86 87/* bit-timing register */ 88#define BTR_BRP_MASK 0x3f 89#define BTR_BRP_SHIFT 0 90#define BTR_SJW_SHIFT 6 91#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 92#define BTR_TSEG1_SHIFT 8 93#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 94#define BTR_TSEG2_SHIFT 12 95#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 96 97/* brp extension register */ 98#define BRP_EXT_BRPE_MASK 0x0f 99#define BRP_EXT_BRPE_SHIFT 0 100 101/* IFx command request */ 102#define IF_COMR_BUSY BIT(15) 103 104/* IFx command mask */ 105#define IF_COMM_WR BIT(7) 106#define IF_COMM_MASK BIT(6) 107#define IF_COMM_ARB BIT(5) 108#define IF_COMM_CONTROL BIT(4) 109#define IF_COMM_CLR_INT_PND BIT(3) 110#define IF_COMM_TXRQST BIT(2) 111#define IF_COMM_DATAA BIT(1) 112#define IF_COMM_DATAB BIT(0) 113#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ 114 IF_COMM_CONTROL | IF_COMM_TXRQST | \ 115 IF_COMM_DATAA | IF_COMM_DATAB) 116 117/* IFx arbitration */ 118#define IF_ARB_MSGVAL BIT(15) 119#define IF_ARB_MSGXTD BIT(14) 120#define IF_ARB_TRANSMIT BIT(13) 121 122/* IFx message control */ 123#define IF_MCONT_NEWDAT BIT(15) 124#define IF_MCONT_MSGLST BIT(14) 125#define IF_MCONT_CLR_MSGLST (0 << 14) 126#define IF_MCONT_INTPND BIT(13) 127#define IF_MCONT_UMASK BIT(12) 128#define IF_MCONT_TXIE BIT(11) 129#define IF_MCONT_RXIE BIT(10) 130#define IF_MCONT_RMTEN BIT(9) 131#define IF_MCONT_TXRQST BIT(8) 132#define IF_MCONT_EOB BIT(7) 133#define IF_MCONT_DLC_MASK 0xf 134 135/* 136 * IFx register masks: 137 * allow easy operation on 16-bit registers when the 138 * argument is 32-bit instead 139 */ 140#define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF) 141#define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16) 142 143/* message object split */ 144#define C_CAN_NO_OF_OBJECTS 32 145#define C_CAN_MSG_OBJ_RX_NUM 16 146#define C_CAN_MSG_OBJ_TX_NUM 16 147 148#define C_CAN_MSG_OBJ_RX_FIRST 1 149#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \ 150 C_CAN_MSG_OBJ_RX_NUM - 1) 151 152#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1) 153#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \ 154 C_CAN_MSG_OBJ_TX_NUM - 1) 155 156#define C_CAN_MSG_OBJ_RX_SPLIT 9 157#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1) 158 159#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1) 160#define RECEIVE_OBJECT_BITS 0x0000ffff 161 162/* status interrupt */ 163#define STATUS_INTERRUPT 0x8000 164 165/* global interrupt masks */ 166#define ENABLE_ALL_INTERRUPTS 1 167#define DISABLE_ALL_INTERRUPTS 0 168 169/* minimum timeout for checking BUSY status */ 170#define MIN_TIMEOUT_VALUE 6 171 172/* Wait for ~1 sec for INIT bit */ 173#define INIT_WAIT_MS 1000 174 175/* napi related */ 176#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 177 178/* c_can lec values */ 179enum c_can_lec_type { 180 LEC_NO_ERROR = 0, 181 LEC_STUFF_ERROR, 182 LEC_FORM_ERROR, 183 LEC_ACK_ERROR, 184 LEC_BIT1_ERROR, 185 LEC_BIT0_ERROR, 186 LEC_CRC_ERROR, 187 LEC_UNUSED, 188}; 189 190/* 191 * c_can error types: 192 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 193 */ 194enum c_can_bus_error_types { 195 C_CAN_NO_ERROR = 0, 196 C_CAN_BUS_OFF, 197 C_CAN_ERROR_WARNING, 198 C_CAN_ERROR_PASSIVE, 199}; 200 201static const struct can_bittiming_const c_can_bittiming_const = { 202 .name = KBUILD_MODNAME, 203 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 204 .tseg1_max = 16, 205 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 206 .tseg2_max = 8, 207 .sjw_max = 4, 208 .brp_min = 1, 209 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 210 .brp_inc = 1, 211}; 212 213static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 214{ 215 if (priv->device) 216 pm_runtime_enable(priv->device); 217} 218 219static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 220{ 221 if (priv->device) 222 pm_runtime_disable(priv->device); 223} 224 225static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 226{ 227 if (priv->device) 228 pm_runtime_get_sync(priv->device); 229} 230 231static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 232{ 233 if (priv->device) 234 pm_runtime_put_sync(priv->device); 235} 236 237static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 238{ 239 if (priv->raminit) 240 priv->raminit(priv, enable); 241} 242 243static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 244{ 245 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + 246 C_CAN_MSG_OBJ_TX_FIRST; 247} 248 249static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv) 250{ 251 return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) + 252 C_CAN_MSG_OBJ_TX_FIRST; 253} 254 255static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) 256{ 257 u32 val = priv->read_reg(priv, index); 258 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 259 return val; 260} 261 262static void c_can_enable_all_interrupts(struct c_can_priv *priv, 263 int enable) 264{ 265 unsigned int cntrl_save = priv->read_reg(priv, 266 C_CAN_CTRL_REG); 267 268 if (enable) 269 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 270 else 271 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); 272 273 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); 274} 275 276static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 277{ 278 int count = MIN_TIMEOUT_VALUE; 279 280 while (count && priv->read_reg(priv, 281 C_CAN_IFACE(COMREQ_REG, iface)) & 282 IF_COMR_BUSY) { 283 count--; 284 udelay(1); 285 } 286 287 if (!count) 288 return 1; 289 290 return 0; 291} 292 293static inline void c_can_object_get(struct net_device *dev, 294 int iface, int objno, int mask) 295{ 296 struct c_can_priv *priv = netdev_priv(dev); 297 298 /* 299 * As per specs, after writting the message object number in the 300 * IF command request register the transfer b/w interface 301 * register and message RAM must be complete in 6 CAN-CLK 302 * period. 303 */ 304 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 305 IFX_WRITE_LOW_16BIT(mask)); 306 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 307 IFX_WRITE_LOW_16BIT(objno)); 308 309 if (c_can_msg_obj_is_busy(priv, iface)) 310 netdev_err(dev, "timed out in object get\n"); 311} 312 313static inline void c_can_object_put(struct net_device *dev, 314 int iface, int objno, int mask) 315{ 316 struct c_can_priv *priv = netdev_priv(dev); 317 318 /* 319 * As per specs, after writting the message object number in the 320 * IF command request register the transfer b/w interface 321 * register and message RAM must be complete in 6 CAN-CLK 322 * period. 323 */ 324 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 325 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); 326 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 327 IFX_WRITE_LOW_16BIT(objno)); 328 329 if (c_can_msg_obj_is_busy(priv, iface)) 330 netdev_err(dev, "timed out in object put\n"); 331} 332 333static void c_can_write_msg_object(struct net_device *dev, 334 int iface, struct can_frame *frame, int objno) 335{ 336 int i; 337 u16 flags = 0; 338 unsigned int id; 339 struct c_can_priv *priv = netdev_priv(dev); 340 341 if (!(frame->can_id & CAN_RTR_FLAG)) 342 flags |= IF_ARB_TRANSMIT; 343 344 if (frame->can_id & CAN_EFF_FLAG) { 345 id = frame->can_id & CAN_EFF_MASK; 346 flags |= IF_ARB_MSGXTD; 347 } else 348 id = ((frame->can_id & CAN_SFF_MASK) << 18); 349 350 flags |= IF_ARB_MSGVAL; 351 352 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 353 IFX_WRITE_LOW_16BIT(id)); 354 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | 355 IFX_WRITE_HIGH_16BIT(id)); 356 357 for (i = 0; i < frame->can_dlc; i += 2) { 358 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 359 frame->data[i] | (frame->data[i + 1] << 8)); 360 } 361 362 /* enable interrupt for this message object */ 363 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 364 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | 365 frame->can_dlc); 366 c_can_object_put(dev, iface, objno, IF_COMM_ALL); 367} 368 369static inline void c_can_mark_rx_msg_obj(struct net_device *dev, 370 int iface, int ctrl_mask, 371 int obj) 372{ 373 struct c_can_priv *priv = netdev_priv(dev); 374 375 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 376 ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND)); 377 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); 378 379} 380 381static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 382 int iface, 383 int ctrl_mask) 384{ 385 int i; 386 struct c_can_priv *priv = netdev_priv(dev); 387 388 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { 389 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 390 ctrl_mask & ~(IF_MCONT_MSGLST | 391 IF_MCONT_INTPND | IF_MCONT_NEWDAT)); 392 c_can_object_put(dev, iface, i, IF_COMM_CONTROL); 393 } 394} 395 396static inline void c_can_activate_rx_msg_obj(struct net_device *dev, 397 int iface, int ctrl_mask, 398 int obj) 399{ 400 struct c_can_priv *priv = netdev_priv(dev); 401 402 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 403 ctrl_mask & ~(IF_MCONT_MSGLST | 404 IF_MCONT_INTPND | IF_MCONT_NEWDAT)); 405 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); 406} 407 408static void c_can_handle_lost_msg_obj(struct net_device *dev, 409 int iface, int objno) 410{ 411 struct c_can_priv *priv = netdev_priv(dev); 412 struct net_device_stats *stats = &dev->stats; 413 struct sk_buff *skb; 414 struct can_frame *frame; 415 416 netdev_err(dev, "msg lost in buffer %d\n", objno); 417 418 c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 419 420 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 421 IF_MCONT_CLR_MSGLST); 422 423 c_can_object_put(dev, 0, objno, IF_COMM_CONTROL); 424 425 /* create an error msg */ 426 skb = alloc_can_err_skb(dev, &frame); 427 if (unlikely(!skb)) 428 return; 429 430 frame->can_id |= CAN_ERR_CRTL; 431 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 432 stats->rx_errors++; 433 stats->rx_over_errors++; 434 435 netif_receive_skb(skb); 436} 437 438static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) 439{ 440 u16 flags, data; 441 int i; 442 unsigned int val; 443 struct c_can_priv *priv = netdev_priv(dev); 444 struct net_device_stats *stats = &dev->stats; 445 struct sk_buff *skb; 446 struct can_frame *frame; 447 448 skb = alloc_can_skb(dev, &frame); 449 if (!skb) { 450 stats->rx_dropped++; 451 return -ENOMEM; 452 } 453 454 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 455 456 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); 457 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | 458 (flags << 16); 459 460 if (flags & IF_ARB_MSGXTD) 461 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; 462 else 463 frame->can_id = (val >> 18) & CAN_SFF_MASK; 464 465 if (flags & IF_ARB_TRANSMIT) 466 frame->can_id |= CAN_RTR_FLAG; 467 else { 468 for (i = 0; i < frame->can_dlc; i += 2) { 469 data = priv->read_reg(priv, 470 C_CAN_IFACE(DATA1_REG, iface) + i / 2); 471 frame->data[i] = data; 472 frame->data[i + 1] = data >> 8; 473 } 474 } 475 476 netif_receive_skb(skb); 477 478 stats->rx_packets++; 479 stats->rx_bytes += frame->can_dlc; 480 481 can_led_event(dev, CAN_LED_EVENT_RX); 482 483 return 0; 484} 485 486static void c_can_setup_receive_object(struct net_device *dev, int iface, 487 int objno, unsigned int mask, 488 unsigned int id, unsigned int mcont) 489{ 490 struct c_can_priv *priv = netdev_priv(dev); 491 492 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), 493 IFX_WRITE_LOW_16BIT(mask)); 494 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), 495 IFX_WRITE_HIGH_16BIT(mask)); 496 497 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 498 IFX_WRITE_LOW_16BIT(id)); 499 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 500 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); 501 502 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 503 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 504 505 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 506 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 507} 508 509static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) 510{ 511 struct c_can_priv *priv = netdev_priv(dev); 512 513 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 514 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 515 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 516 517 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); 518 519 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 520 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 521} 522 523static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 524{ 525 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 526 527 /* 528 * as transmission request register's bit n-1 corresponds to 529 * message object n, we need to handle the same properly. 530 */ 531 if (val & (1 << (objno - 1))) 532 return 1; 533 534 return 0; 535} 536 537static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 538 struct net_device *dev) 539{ 540 u32 msg_obj_no; 541 struct c_can_priv *priv = netdev_priv(dev); 542 struct can_frame *frame = (struct can_frame *)skb->data; 543 544 if (can_dropped_invalid_skb(dev, skb)) 545 return NETDEV_TX_OK; 546 547 msg_obj_no = get_tx_next_msg_obj(priv); 548 549 /* prepare message object for transmission */ 550 c_can_write_msg_object(dev, 0, frame, msg_obj_no); 551 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 552 553 /* 554 * we have to stop the queue in case of a wrap around or 555 * if the next TX message object is still in use 556 */ 557 priv->tx_next++; 558 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 559 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 560 netif_stop_queue(dev); 561 562 return NETDEV_TX_OK; 563} 564 565static int c_can_set_bittiming(struct net_device *dev) 566{ 567 unsigned int reg_btr, reg_brpe, ctrl_save; 568 u8 brp, brpe, sjw, tseg1, tseg2; 569 u32 ten_bit_brp; 570 struct c_can_priv *priv = netdev_priv(dev); 571 const struct can_bittiming *bt = &priv->can.bittiming; 572 573 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 574 ten_bit_brp = bt->brp - 1; 575 brp = ten_bit_brp & BTR_BRP_MASK; 576 brpe = ten_bit_brp >> 6; 577 578 sjw = bt->sjw - 1; 579 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 580 tseg2 = bt->phase_seg2 - 1; 581 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 582 (tseg2 << BTR_TSEG2_SHIFT); 583 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 584 585 netdev_info(dev, 586 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 587 588 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 589 priv->write_reg(priv, C_CAN_CTRL_REG, 590 ctrl_save | CONTROL_CCE | CONTROL_INIT); 591 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 592 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 593 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 594 595 return 0; 596} 597 598/* 599 * Configure C_CAN message objects for Tx and Rx purposes: 600 * C_CAN provides a total of 32 message objects that can be configured 601 * either for Tx or Rx purposes. Here the first 16 message objects are used as 602 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 603 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 604 * See user guide document for further details on configuring message 605 * objects. 606 */ 607static void c_can_configure_msg_objects(struct net_device *dev) 608{ 609 int i; 610 611 /* first invalidate all message objects */ 612 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 613 c_can_inval_msg_object(dev, 0, i); 614 615 /* setup receive message objects */ 616 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 617 c_can_setup_receive_object(dev, 0, i, 0, 0, 618 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); 619 620 c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 621 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); 622} 623 624/* 625 * Configure C_CAN chip: 626 * - enable/disable auto-retransmission 627 * - set operating mode 628 * - configure message objects 629 */ 630static void c_can_chip_config(struct net_device *dev) 631{ 632 struct c_can_priv *priv = netdev_priv(dev); 633 634 /* enable automatic retransmission */ 635 priv->write_reg(priv, C_CAN_CTRL_REG, 636 CONTROL_ENABLE_AR); 637 638 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 639 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 640 /* loopback + silent mode : useful for hot self-test */ 641 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 642 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 643 priv->write_reg(priv, C_CAN_TEST_REG, 644 TEST_LBACK | TEST_SILENT); 645 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 646 /* loopback mode : useful for self-test function */ 647 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 648 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 649 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 650 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 651 /* silent mode : bus-monitoring mode */ 652 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 653 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 654 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 655 } else 656 /* normal mode*/ 657 priv->write_reg(priv, C_CAN_CTRL_REG, 658 CONTROL_EIE | CONTROL_SIE | CONTROL_IE); 659 660 /* configure message objects */ 661 c_can_configure_msg_objects(dev); 662 663 /* set a `lec` value so that we can check for updates later */ 664 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 665 666 /* set bittiming params */ 667 c_can_set_bittiming(dev); 668} 669 670static void c_can_start(struct net_device *dev) 671{ 672 struct c_can_priv *priv = netdev_priv(dev); 673 674 /* basic c_can configuration */ 675 c_can_chip_config(dev); 676 677 priv->can.state = CAN_STATE_ERROR_ACTIVE; 678 679 /* reset tx helper pointers */ 680 priv->tx_next = priv->tx_echo = 0; 681 682 /* enable status change, error and module interrupts */ 683 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 684} 685 686static void c_can_stop(struct net_device *dev) 687{ 688 struct c_can_priv *priv = netdev_priv(dev); 689 690 /* disable all interrupts */ 691 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 692 693 /* set the state as STOPPED */ 694 priv->can.state = CAN_STATE_STOPPED; 695} 696 697static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 698{ 699 switch (mode) { 700 case CAN_MODE_START: 701 c_can_start(dev); 702 netif_wake_queue(dev); 703 break; 704 default: 705 return -EOPNOTSUPP; 706 } 707 708 return 0; 709} 710 711static int c_can_get_berr_counter(const struct net_device *dev, 712 struct can_berr_counter *bec) 713{ 714 unsigned int reg_err_counter; 715 struct c_can_priv *priv = netdev_priv(dev); 716 717 c_can_pm_runtime_get_sync(priv); 718 719 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 720 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 721 ERR_CNT_REC_SHIFT; 722 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 723 724 c_can_pm_runtime_put_sync(priv); 725 726 return 0; 727} 728 729/* 730 * theory of operation: 731 * 732 * priv->tx_echo holds the number of the oldest can_frame put for 733 * transmission into the hardware, but not yet ACKed by the CAN tx 734 * complete IRQ. 735 * 736 * We iterate from priv->tx_echo to priv->tx_next and check if the 737 * packet has been transmitted, echo it back to the CAN framework. 738 * If we discover a not yet transmitted packet, stop looking for more. 739 */ 740static void c_can_do_tx(struct net_device *dev) 741{ 742 u32 val; 743 u32 msg_obj_no; 744 struct c_can_priv *priv = netdev_priv(dev); 745 struct net_device_stats *stats = &dev->stats; 746 747 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 748 msg_obj_no = get_tx_echo_msg_obj(priv); 749 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 750 if (!(val & (1 << (msg_obj_no - 1)))) { 751 can_get_echo_skb(dev, 752 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 753 stats->tx_bytes += priv->read_reg(priv, 754 C_CAN_IFACE(MSGCTRL_REG, 0)) 755 & IF_MCONT_DLC_MASK; 756 stats->tx_packets++; 757 can_led_event(dev, CAN_LED_EVENT_TX); 758 c_can_inval_msg_object(dev, 0, msg_obj_no); 759 } else { 760 break; 761 } 762 } 763 764 /* restart queue if wrap-up or if queue stalled on last pkt */ 765 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 766 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) 767 netif_wake_queue(dev); 768} 769 770/* 771 * theory of operation: 772 * 773 * c_can core saves a received CAN message into the first free message 774 * object it finds free (starting with the lowest). Bits NEWDAT and 775 * INTPND are set for this message object indicating that a new message 776 * has arrived. To work-around this issue, we keep two groups of message 777 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 778 * 779 * To ensure in-order frame reception we use the following 780 * approach while re-activating a message object to receive further 781 * frames: 782 * - if the current message object number is lower than 783 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 784 * the INTPND bit. 785 * - if the current message object number is equal to 786 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 787 * receive message objects. 788 * - if the current message object number is greater than 789 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 790 * only this message object. 791 */ 792static int c_can_do_rx_poll(struct net_device *dev, int quota) 793{ 794 u32 num_rx_pkts = 0; 795 unsigned int msg_obj, msg_ctrl_save; 796 struct c_can_priv *priv = netdev_priv(dev); 797 u32 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG); 798 799 for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST; 800 msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0; 801 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG), 802 msg_obj++) { 803 /* 804 * as interrupt pending register's bit n-1 corresponds to 805 * message object n, we need to handle the same properly. 806 */ 807 if (val & (1 << (msg_obj - 1))) { 808 c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL & 809 ~IF_COMM_TXRQST); 810 msg_ctrl_save = priv->read_reg(priv, 811 C_CAN_IFACE(MSGCTRL_REG, 0)); 812 813 if (msg_ctrl_save & IF_MCONT_EOB) 814 return num_rx_pkts; 815 816 if (msg_ctrl_save & IF_MCONT_MSGLST) { 817 c_can_handle_lost_msg_obj(dev, 0, msg_obj); 818 num_rx_pkts++; 819 quota--; 820 continue; 821 } 822 823 if (!(msg_ctrl_save & IF_MCONT_NEWDAT)) 824 continue; 825 826 /* read the data from the message object */ 827 c_can_read_msg_object(dev, 0, msg_ctrl_save); 828 829 if (msg_obj < C_CAN_MSG_RX_LOW_LAST) 830 c_can_mark_rx_msg_obj(dev, 0, 831 msg_ctrl_save, msg_obj); 832 else if (msg_obj > C_CAN_MSG_RX_LOW_LAST) 833 /* activate this msg obj */ 834 c_can_activate_rx_msg_obj(dev, 0, 835 msg_ctrl_save, msg_obj); 836 else if (msg_obj == C_CAN_MSG_RX_LOW_LAST) 837 /* activate all lower message objects */ 838 c_can_activate_all_lower_rx_msg_obj(dev, 839 0, msg_ctrl_save); 840 841 num_rx_pkts++; 842 quota--; 843 } 844 } 845 846 return num_rx_pkts; 847} 848 849static inline int c_can_has_and_handle_berr(struct c_can_priv *priv) 850{ 851 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 852 (priv->current_status & LEC_UNUSED); 853} 854 855static int c_can_handle_state_change(struct net_device *dev, 856 enum c_can_bus_error_types error_type) 857{ 858 unsigned int reg_err_counter; 859 unsigned int rx_err_passive; 860 struct c_can_priv *priv = netdev_priv(dev); 861 struct net_device_stats *stats = &dev->stats; 862 struct can_frame *cf; 863 struct sk_buff *skb; 864 struct can_berr_counter bec; 865 866 /* propagate the error condition to the CAN stack */ 867 skb = alloc_can_err_skb(dev, &cf); 868 if (unlikely(!skb)) 869 return 0; 870 871 c_can_get_berr_counter(dev, &bec); 872 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 873 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 874 ERR_CNT_RP_SHIFT; 875 876 switch (error_type) { 877 case C_CAN_ERROR_WARNING: 878 /* error warning state */ 879 priv->can.can_stats.error_warning++; 880 priv->can.state = CAN_STATE_ERROR_WARNING; 881 cf->can_id |= CAN_ERR_CRTL; 882 cf->data[1] = (bec.txerr > bec.rxerr) ? 883 CAN_ERR_CRTL_TX_WARNING : 884 CAN_ERR_CRTL_RX_WARNING; 885 cf->data[6] = bec.txerr; 886 cf->data[7] = bec.rxerr; 887 888 break; 889 case C_CAN_ERROR_PASSIVE: 890 /* error passive state */ 891 priv->can.can_stats.error_passive++; 892 priv->can.state = CAN_STATE_ERROR_PASSIVE; 893 cf->can_id |= CAN_ERR_CRTL; 894 if (rx_err_passive) 895 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 896 if (bec.txerr > 127) 897 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 898 899 cf->data[6] = bec.txerr; 900 cf->data[7] = bec.rxerr; 901 break; 902 case C_CAN_BUS_OFF: 903 /* bus-off state */ 904 priv->can.state = CAN_STATE_BUS_OFF; 905 cf->can_id |= CAN_ERR_BUSOFF; 906 /* 907 * disable all interrupts in bus-off mode to ensure that 908 * the CPU is not hogged down 909 */ 910 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 911 can_bus_off(dev); 912 break; 913 default: 914 break; 915 } 916 917 netif_receive_skb(skb); 918 stats->rx_packets++; 919 stats->rx_bytes += cf->can_dlc; 920 921 return 1; 922} 923 924static int c_can_handle_bus_err(struct net_device *dev, 925 enum c_can_lec_type lec_type) 926{ 927 struct c_can_priv *priv = netdev_priv(dev); 928 struct net_device_stats *stats = &dev->stats; 929 struct can_frame *cf; 930 struct sk_buff *skb; 931 932 /* 933 * early exit if no lec update or no error. 934 * no lec update means that no CAN bus event has been detected 935 * since CPU wrote 0x7 value to status reg. 936 */ 937 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 938 return 0; 939 940 /* propagate the error condition to the CAN stack */ 941 skb = alloc_can_err_skb(dev, &cf); 942 if (unlikely(!skb)) 943 return 0; 944 945 /* 946 * check for 'last error code' which tells us the 947 * type of the last error to occur on the CAN bus 948 */ 949 950 /* common for all type of bus errors */ 951 priv->can.can_stats.bus_error++; 952 stats->rx_errors++; 953 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 954 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 955 956 switch (lec_type) { 957 case LEC_STUFF_ERROR: 958 netdev_dbg(dev, "stuff error\n"); 959 cf->data[2] |= CAN_ERR_PROT_STUFF; 960 break; 961 case LEC_FORM_ERROR: 962 netdev_dbg(dev, "form error\n"); 963 cf->data[2] |= CAN_ERR_PROT_FORM; 964 break; 965 case LEC_ACK_ERROR: 966 netdev_dbg(dev, "ack error\n"); 967 cf->data[2] |= (CAN_ERR_PROT_LOC_ACK | 968 CAN_ERR_PROT_LOC_ACK_DEL); 969 break; 970 case LEC_BIT1_ERROR: 971 netdev_dbg(dev, "bit1 error\n"); 972 cf->data[2] |= CAN_ERR_PROT_BIT1; 973 break; 974 case LEC_BIT0_ERROR: 975 netdev_dbg(dev, "bit0 error\n"); 976 cf->data[2] |= CAN_ERR_PROT_BIT0; 977 break; 978 case LEC_CRC_ERROR: 979 netdev_dbg(dev, "CRC error\n"); 980 cf->data[2] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 981 CAN_ERR_PROT_LOC_CRC_DEL); 982 break; 983 default: 984 break; 985 } 986 987 /* set a `lec` value so that we can check for updates later */ 988 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 989 990 netif_receive_skb(skb); 991 stats->rx_packets++; 992 stats->rx_bytes += cf->can_dlc; 993 994 return 1; 995} 996 997static int c_can_poll(struct napi_struct *napi, int quota) 998{ 999 u16 irqstatus; 1000 int lec_type = 0; 1001 int work_done = 0; 1002 struct net_device *dev = napi->dev; 1003 struct c_can_priv *priv = netdev_priv(dev); 1004 1005 irqstatus = priv->irqstatus; 1006 if (!irqstatus) 1007 goto end; 1008 1009 /* status events have the highest priority */ 1010 if (irqstatus == STATUS_INTERRUPT) { 1011 priv->current_status = priv->read_reg(priv, 1012 C_CAN_STS_REG); 1013 1014 /* handle Tx/Rx events */ 1015 if (priv->current_status & STATUS_TXOK) 1016 priv->write_reg(priv, C_CAN_STS_REG, 1017 priv->current_status & ~STATUS_TXOK); 1018 1019 if (priv->current_status & STATUS_RXOK) 1020 priv->write_reg(priv, C_CAN_STS_REG, 1021 priv->current_status & ~STATUS_RXOK); 1022 1023 /* handle state changes */ 1024 if ((priv->current_status & STATUS_EWARN) && 1025 (!(priv->last_status & STATUS_EWARN))) { 1026 netdev_dbg(dev, "entered error warning state\n"); 1027 work_done += c_can_handle_state_change(dev, 1028 C_CAN_ERROR_WARNING); 1029 } 1030 if ((priv->current_status & STATUS_EPASS) && 1031 (!(priv->last_status & STATUS_EPASS))) { 1032 netdev_dbg(dev, "entered error passive state\n"); 1033 work_done += c_can_handle_state_change(dev, 1034 C_CAN_ERROR_PASSIVE); 1035 } 1036 if ((priv->current_status & STATUS_BOFF) && 1037 (!(priv->last_status & STATUS_BOFF))) { 1038 netdev_dbg(dev, "entered bus off state\n"); 1039 work_done += c_can_handle_state_change(dev, 1040 C_CAN_BUS_OFF); 1041 } 1042 1043 /* handle bus recovery events */ 1044 if ((!(priv->current_status & STATUS_BOFF)) && 1045 (priv->last_status & STATUS_BOFF)) { 1046 netdev_dbg(dev, "left bus off state\n"); 1047 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1048 } 1049 if ((!(priv->current_status & STATUS_EPASS)) && 1050 (priv->last_status & STATUS_EPASS)) { 1051 netdev_dbg(dev, "left error passive state\n"); 1052 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1053 } 1054 1055 priv->last_status = priv->current_status; 1056 1057 /* handle lec errors on the bus */ 1058 lec_type = c_can_has_and_handle_berr(priv); 1059 if (lec_type) 1060 work_done += c_can_handle_bus_err(dev, lec_type); 1061 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && 1062 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { 1063 /* handle events corresponding to receive message objects */ 1064 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1065 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && 1066 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { 1067 /* handle events corresponding to transmit message objects */ 1068 c_can_do_tx(dev); 1069 } 1070 1071end: 1072 if (work_done < quota) { 1073 napi_complete(napi); 1074 /* enable all IRQs */ 1075 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1076 } 1077 1078 return work_done; 1079} 1080 1081static irqreturn_t c_can_isr(int irq, void *dev_id) 1082{ 1083 struct net_device *dev = (struct net_device *)dev_id; 1084 struct c_can_priv *priv = netdev_priv(dev); 1085 1086 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); 1087 if (!priv->irqstatus) 1088 return IRQ_NONE; 1089 1090 /* disable all interrupts and schedule the NAPI */ 1091 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1092 napi_schedule(&priv->napi); 1093 1094 return IRQ_HANDLED; 1095} 1096 1097static int c_can_open(struct net_device *dev) 1098{ 1099 int err; 1100 struct c_can_priv *priv = netdev_priv(dev); 1101 1102 c_can_pm_runtime_get_sync(priv); 1103 c_can_reset_ram(priv, true); 1104 1105 /* open the can device */ 1106 err = open_candev(dev); 1107 if (err) { 1108 netdev_err(dev, "failed to open can device\n"); 1109 goto exit_open_fail; 1110 } 1111 1112 /* register interrupt handler */ 1113 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1114 dev); 1115 if (err < 0) { 1116 netdev_err(dev, "failed to request interrupt\n"); 1117 goto exit_irq_fail; 1118 } 1119 1120 napi_enable(&priv->napi); 1121 1122 can_led_event(dev, CAN_LED_EVENT_OPEN); 1123 1124 /* start the c_can controller */ 1125 c_can_start(dev); 1126 1127 netif_start_queue(dev); 1128 1129 return 0; 1130 1131exit_irq_fail: 1132 close_candev(dev); 1133exit_open_fail: 1134 c_can_reset_ram(priv, false); 1135 c_can_pm_runtime_put_sync(priv); 1136 return err; 1137} 1138 1139static int c_can_close(struct net_device *dev) 1140{ 1141 struct c_can_priv *priv = netdev_priv(dev); 1142 1143 netif_stop_queue(dev); 1144 napi_disable(&priv->napi); 1145 c_can_stop(dev); 1146 free_irq(dev->irq, dev); 1147 close_candev(dev); 1148 1149 c_can_reset_ram(priv, false); 1150 c_can_pm_runtime_put_sync(priv); 1151 1152 can_led_event(dev, CAN_LED_EVENT_STOP); 1153 1154 return 0; 1155} 1156 1157struct net_device *alloc_c_can_dev(void) 1158{ 1159 struct net_device *dev; 1160 struct c_can_priv *priv; 1161 1162 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1163 if (!dev) 1164 return NULL; 1165 1166 priv = netdev_priv(dev); 1167 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1168 1169 priv->dev = dev; 1170 priv->can.bittiming_const = &c_can_bittiming_const; 1171 priv->can.do_set_mode = c_can_set_mode; 1172 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1173 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1174 CAN_CTRLMODE_LISTENONLY | 1175 CAN_CTRLMODE_BERR_REPORTING; 1176 1177 return dev; 1178} 1179EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1180 1181#ifdef CONFIG_PM 1182int c_can_power_down(struct net_device *dev) 1183{ 1184 u32 val; 1185 unsigned long time_out; 1186 struct c_can_priv *priv = netdev_priv(dev); 1187 1188 if (!(dev->flags & IFF_UP)) 1189 return 0; 1190 1191 WARN_ON(priv->type != BOSCH_D_CAN); 1192 1193 /* set PDR value so the device goes to power down mode */ 1194 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1195 val |= CONTROL_EX_PDR; 1196 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1197 1198 /* Wait for the PDA bit to get set */ 1199 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1200 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1201 time_after(time_out, jiffies)) 1202 cpu_relax(); 1203 1204 if (time_after(jiffies, time_out)) 1205 return -ETIMEDOUT; 1206 1207 c_can_stop(dev); 1208 1209 c_can_reset_ram(priv, false); 1210 c_can_pm_runtime_put_sync(priv); 1211 1212 return 0; 1213} 1214EXPORT_SYMBOL_GPL(c_can_power_down); 1215 1216int c_can_power_up(struct net_device *dev) 1217{ 1218 u32 val; 1219 unsigned long time_out; 1220 struct c_can_priv *priv = netdev_priv(dev); 1221 1222 if (!(dev->flags & IFF_UP)) 1223 return 0; 1224 1225 WARN_ON(priv->type != BOSCH_D_CAN); 1226 1227 c_can_pm_runtime_get_sync(priv); 1228 c_can_reset_ram(priv, true); 1229 1230 /* Clear PDR and INIT bits */ 1231 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1232 val &= ~CONTROL_EX_PDR; 1233 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1234 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1235 val &= ~CONTROL_INIT; 1236 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1237 1238 /* Wait for the PDA bit to get clear */ 1239 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1240 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1241 time_after(time_out, jiffies)) 1242 cpu_relax(); 1243 1244 if (time_after(jiffies, time_out)) 1245 return -ETIMEDOUT; 1246 1247 c_can_start(dev); 1248 1249 return 0; 1250} 1251EXPORT_SYMBOL_GPL(c_can_power_up); 1252#endif 1253 1254void free_c_can_dev(struct net_device *dev) 1255{ 1256 free_candev(dev); 1257} 1258EXPORT_SYMBOL_GPL(free_c_can_dev); 1259 1260static const struct net_device_ops c_can_netdev_ops = { 1261 .ndo_open = c_can_open, 1262 .ndo_stop = c_can_close, 1263 .ndo_start_xmit = c_can_start_xmit, 1264}; 1265 1266int register_c_can_dev(struct net_device *dev) 1267{ 1268 struct c_can_priv *priv = netdev_priv(dev); 1269 int err; 1270 1271 c_can_pm_runtime_enable(priv); 1272 1273 dev->flags |= IFF_ECHO; /* we support local echo */ 1274 dev->netdev_ops = &c_can_netdev_ops; 1275 1276 err = register_candev(dev); 1277 if (err) 1278 c_can_pm_runtime_disable(priv); 1279 else 1280 devm_can_led_init(dev); 1281 1282 return err; 1283} 1284EXPORT_SYMBOL_GPL(register_c_can_dev); 1285 1286void unregister_c_can_dev(struct net_device *dev) 1287{ 1288 struct c_can_priv *priv = netdev_priv(dev); 1289 1290 unregister_candev(dev); 1291 1292 c_can_pm_runtime_disable(priv); 1293} 1294EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1295 1296MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1297MODULE_LICENSE("GPL v2"); 1298MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1299