c_can.c revision 5a7513adab521909e836fa5b9aaabbf22b48859f
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42#include <linux/can/led.h> 43 44#include "c_can.h" 45 46/* Number of interface registers */ 47#define IF_ENUM_REG_LEN 11 48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 49 50/* control extension register D_CAN specific */ 51#define CONTROL_EX_PDR BIT(8) 52 53/* control register */ 54#define CONTROL_TEST BIT(7) 55#define CONTROL_CCE BIT(6) 56#define CONTROL_DISABLE_AR BIT(5) 57#define CONTROL_ENABLE_AR (0 << 5) 58#define CONTROL_EIE BIT(3) 59#define CONTROL_SIE BIT(2) 60#define CONTROL_IE BIT(1) 61#define CONTROL_INIT BIT(0) 62 63/* test register */ 64#define TEST_RX BIT(7) 65#define TEST_TX1 BIT(6) 66#define TEST_TX2 BIT(5) 67#define TEST_LBACK BIT(4) 68#define TEST_SILENT BIT(3) 69#define TEST_BASIC BIT(2) 70 71/* status register */ 72#define STATUS_PDA BIT(10) 73#define STATUS_BOFF BIT(7) 74#define STATUS_EWARN BIT(6) 75#define STATUS_EPASS BIT(5) 76#define STATUS_RXOK BIT(4) 77#define STATUS_TXOK BIT(3) 78 79/* error counter register */ 80#define ERR_CNT_TEC_MASK 0xff 81#define ERR_CNT_TEC_SHIFT 0 82#define ERR_CNT_REC_SHIFT 8 83#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 84#define ERR_CNT_RP_SHIFT 15 85#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 86 87/* bit-timing register */ 88#define BTR_BRP_MASK 0x3f 89#define BTR_BRP_SHIFT 0 90#define BTR_SJW_SHIFT 6 91#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 92#define BTR_TSEG1_SHIFT 8 93#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 94#define BTR_TSEG2_SHIFT 12 95#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 96 97/* brp extension register */ 98#define BRP_EXT_BRPE_MASK 0x0f 99#define BRP_EXT_BRPE_SHIFT 0 100 101/* IFx command request */ 102#define IF_COMR_BUSY BIT(15) 103 104/* IFx command mask */ 105#define IF_COMM_WR BIT(7) 106#define IF_COMM_MASK BIT(6) 107#define IF_COMM_ARB BIT(5) 108#define IF_COMM_CONTROL BIT(4) 109#define IF_COMM_CLR_INT_PND BIT(3) 110#define IF_COMM_TXRQST BIT(2) 111#define IF_COMM_DATAA BIT(1) 112#define IF_COMM_DATAB BIT(0) 113#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ 114 IF_COMM_CONTROL | IF_COMM_TXRQST | \ 115 IF_COMM_DATAA | IF_COMM_DATAB) 116 117/* For the low buffers we clear the interrupt bit, but keep newdat */ 118#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 119 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 120 IF_COMM_DATAA | IF_COMM_DATAB) 121 122/* For the high buffers we clear the interrupt bit and newdat */ 123#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_TXRQST) 124 125/* IFx arbitration */ 126#define IF_ARB_MSGVAL BIT(15) 127#define IF_ARB_MSGXTD BIT(14) 128#define IF_ARB_TRANSMIT BIT(13) 129 130/* IFx message control */ 131#define IF_MCONT_NEWDAT BIT(15) 132#define IF_MCONT_MSGLST BIT(14) 133#define IF_MCONT_INTPND BIT(13) 134#define IF_MCONT_UMASK BIT(12) 135#define IF_MCONT_TXIE BIT(11) 136#define IF_MCONT_RXIE BIT(10) 137#define IF_MCONT_RMTEN BIT(9) 138#define IF_MCONT_TXRQST BIT(8) 139#define IF_MCONT_EOB BIT(7) 140#define IF_MCONT_DLC_MASK 0xf 141 142/* 143 * Use IF1 for RX and IF2 for TX 144 */ 145#define IF_RX 0 146#define IF_TX 1 147 148/* status interrupt */ 149#define STATUS_INTERRUPT 0x8000 150 151/* global interrupt masks */ 152#define ENABLE_ALL_INTERRUPTS 1 153#define DISABLE_ALL_INTERRUPTS 0 154 155/* minimum timeout for checking BUSY status */ 156#define MIN_TIMEOUT_VALUE 6 157 158/* Wait for ~1 sec for INIT bit */ 159#define INIT_WAIT_MS 1000 160 161/* napi related */ 162#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 163 164/* c_can lec values */ 165enum c_can_lec_type { 166 LEC_NO_ERROR = 0, 167 LEC_STUFF_ERROR, 168 LEC_FORM_ERROR, 169 LEC_ACK_ERROR, 170 LEC_BIT1_ERROR, 171 LEC_BIT0_ERROR, 172 LEC_CRC_ERROR, 173 LEC_UNUSED, 174}; 175 176/* 177 * c_can error types: 178 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 179 */ 180enum c_can_bus_error_types { 181 C_CAN_NO_ERROR = 0, 182 C_CAN_BUS_OFF, 183 C_CAN_ERROR_WARNING, 184 C_CAN_ERROR_PASSIVE, 185}; 186 187static const struct can_bittiming_const c_can_bittiming_const = { 188 .name = KBUILD_MODNAME, 189 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 190 .tseg1_max = 16, 191 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 192 .tseg2_max = 8, 193 .sjw_max = 4, 194 .brp_min = 1, 195 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 196 .brp_inc = 1, 197}; 198 199static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 200{ 201 if (priv->device) 202 pm_runtime_enable(priv->device); 203} 204 205static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 206{ 207 if (priv->device) 208 pm_runtime_disable(priv->device); 209} 210 211static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 212{ 213 if (priv->device) 214 pm_runtime_get_sync(priv->device); 215} 216 217static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 218{ 219 if (priv->device) 220 pm_runtime_put_sync(priv->device); 221} 222 223static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 224{ 225 if (priv->raminit) 226 priv->raminit(priv, enable); 227} 228 229static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 230{ 231 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + 232 C_CAN_MSG_OBJ_TX_FIRST; 233} 234 235static inline int get_tx_echo_msg_obj(int txecho) 236{ 237 return (txecho & C_CAN_NEXT_MSG_OBJ_MASK) + C_CAN_MSG_OBJ_TX_FIRST; 238} 239 240static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) 241{ 242 u32 val = priv->read_reg(priv, index); 243 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 244 return val; 245} 246 247static void c_can_enable_all_interrupts(struct c_can_priv *priv, 248 int enable) 249{ 250 unsigned int cntrl_save = priv->read_reg(priv, 251 C_CAN_CTRL_REG); 252 253 if (enable) 254 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 255 else 256 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); 257 258 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); 259} 260 261static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 262{ 263 int count = MIN_TIMEOUT_VALUE; 264 265 while (count && priv->read_reg(priv, 266 C_CAN_IFACE(COMREQ_REG, iface)) & 267 IF_COMR_BUSY) { 268 count--; 269 udelay(1); 270 } 271 272 if (!count) 273 return 1; 274 275 return 0; 276} 277 278static inline void c_can_object_get(struct net_device *dev, 279 int iface, int objno, int mask) 280{ 281 struct c_can_priv *priv = netdev_priv(dev); 282 283 /* 284 * As per specs, after writting the message object number in the 285 * IF command request register the transfer b/w interface 286 * register and message RAM must be complete in 6 CAN-CLK 287 * period. 288 */ 289 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 290 IFX_WRITE_LOW_16BIT(mask)); 291 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 292 IFX_WRITE_LOW_16BIT(objno)); 293 294 if (c_can_msg_obj_is_busy(priv, iface)) 295 netdev_err(dev, "timed out in object get\n"); 296} 297 298static inline void c_can_object_put(struct net_device *dev, 299 int iface, int objno, int mask) 300{ 301 struct c_can_priv *priv = netdev_priv(dev); 302 303 /* 304 * As per specs, after writting the message object number in the 305 * IF command request register the transfer b/w interface 306 * register and message RAM must be complete in 6 CAN-CLK 307 * period. 308 */ 309 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 310 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); 311 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 312 IFX_WRITE_LOW_16BIT(objno)); 313 314 if (c_can_msg_obj_is_busy(priv, iface)) 315 netdev_err(dev, "timed out in object put\n"); 316} 317 318static void c_can_write_msg_object(struct net_device *dev, 319 int iface, struct can_frame *frame, int objno) 320{ 321 int i; 322 u16 flags = 0; 323 unsigned int id; 324 struct c_can_priv *priv = netdev_priv(dev); 325 326 if (!(frame->can_id & CAN_RTR_FLAG)) 327 flags |= IF_ARB_TRANSMIT; 328 329 if (frame->can_id & CAN_EFF_FLAG) { 330 id = frame->can_id & CAN_EFF_MASK; 331 flags |= IF_ARB_MSGXTD; 332 } else 333 id = ((frame->can_id & CAN_SFF_MASK) << 18); 334 335 flags |= IF_ARB_MSGVAL; 336 337 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 338 IFX_WRITE_LOW_16BIT(id)); 339 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | 340 IFX_WRITE_HIGH_16BIT(id)); 341 342 for (i = 0; i < frame->can_dlc; i += 2) { 343 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 344 frame->data[i] | (frame->data[i + 1] << 8)); 345 } 346 347 /* enable interrupt for this message object */ 348 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 349 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | 350 frame->can_dlc); 351 c_can_object_put(dev, iface, objno, IF_COMM_ALL); 352} 353 354static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 355 int iface, 356 int ctrl_mask) 357{ 358 int i; 359 struct c_can_priv *priv = netdev_priv(dev); 360 361 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { 362 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 363 ctrl_mask & ~IF_MCONT_NEWDAT); 364 c_can_object_put(dev, iface, i, IF_COMM_CONTROL); 365 } 366} 367 368static int c_can_handle_lost_msg_obj(struct net_device *dev, 369 int iface, int objno, u32 ctrl) 370{ 371 struct net_device_stats *stats = &dev->stats; 372 struct c_can_priv *priv = netdev_priv(dev); 373 struct can_frame *frame; 374 struct sk_buff *skb; 375 376 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 377 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 378 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 379 380 /* create an error msg */ 381 skb = alloc_can_err_skb(dev, &frame); 382 if (unlikely(!skb)) 383 return 0; 384 385 frame->can_id |= CAN_ERR_CRTL; 386 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 387 stats->rx_errors++; 388 stats->rx_over_errors++; 389 390 netif_receive_skb(skb); 391 return 1; 392} 393 394static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) 395{ 396 u16 flags, data; 397 int i; 398 unsigned int val; 399 struct c_can_priv *priv = netdev_priv(dev); 400 struct net_device_stats *stats = &dev->stats; 401 struct sk_buff *skb; 402 struct can_frame *frame; 403 404 skb = alloc_can_skb(dev, &frame); 405 if (!skb) { 406 stats->rx_dropped++; 407 return -ENOMEM; 408 } 409 410 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 411 412 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); 413 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | 414 (flags << 16); 415 416 if (flags & IF_ARB_MSGXTD) 417 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; 418 else 419 frame->can_id = (val >> 18) & CAN_SFF_MASK; 420 421 if (flags & IF_ARB_TRANSMIT) 422 frame->can_id |= CAN_RTR_FLAG; 423 else { 424 for (i = 0; i < frame->can_dlc; i += 2) { 425 data = priv->read_reg(priv, 426 C_CAN_IFACE(DATA1_REG, iface) + i / 2); 427 frame->data[i] = data; 428 frame->data[i + 1] = data >> 8; 429 } 430 } 431 432 netif_receive_skb(skb); 433 434 stats->rx_packets++; 435 stats->rx_bytes += frame->can_dlc; 436 437 can_led_event(dev, CAN_LED_EVENT_RX); 438 439 return 0; 440} 441 442static void c_can_setup_receive_object(struct net_device *dev, int iface, 443 int objno, unsigned int mask, 444 unsigned int id, unsigned int mcont) 445{ 446 struct c_can_priv *priv = netdev_priv(dev); 447 448 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), 449 IFX_WRITE_LOW_16BIT(mask)); 450 451 /* According to C_CAN documentation, the reserved bit 452 * in IFx_MASK2 register is fixed 1 453 */ 454 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), 455 IFX_WRITE_HIGH_16BIT(mask) | BIT(13)); 456 457 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 458 IFX_WRITE_LOW_16BIT(id)); 459 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 460 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); 461 462 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 463 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 464 465 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 466 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 467} 468 469static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) 470{ 471 struct c_can_priv *priv = netdev_priv(dev); 472 473 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 474 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 475 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 476 477 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); 478 479 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 480 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 481} 482 483static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 484{ 485 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 486 487 /* 488 * as transmission request register's bit n-1 corresponds to 489 * message object n, we need to handle the same properly. 490 */ 491 if (val & (1 << (objno - 1))) 492 return 1; 493 494 return 0; 495} 496 497static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 498 struct net_device *dev) 499{ 500 u32 msg_obj_no; 501 struct c_can_priv *priv = netdev_priv(dev); 502 struct can_frame *frame = (struct can_frame *)skb->data; 503 504 if (can_dropped_invalid_skb(dev, skb)) 505 return NETDEV_TX_OK; 506 507 spin_lock_bh(&priv->xmit_lock); 508 msg_obj_no = get_tx_next_msg_obj(priv); 509 510 /* prepare message object for transmission */ 511 c_can_write_msg_object(dev, IF_TX, frame, msg_obj_no); 512 priv->dlc[msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST] = frame->can_dlc; 513 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 514 515 /* 516 * we have to stop the queue in case of a wrap around or 517 * if the next TX message object is still in use 518 */ 519 priv->tx_next++; 520 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 521 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 522 netif_stop_queue(dev); 523 spin_unlock_bh(&priv->xmit_lock); 524 525 return NETDEV_TX_OK; 526} 527 528static int c_can_wait_for_ctrl_init(struct net_device *dev, 529 struct c_can_priv *priv, u32 init) 530{ 531 int retry = 0; 532 533 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 534 udelay(10); 535 if (retry++ > 1000) { 536 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 537 return -EIO; 538 } 539 } 540 return 0; 541} 542 543static int c_can_set_bittiming(struct net_device *dev) 544{ 545 unsigned int reg_btr, reg_brpe, ctrl_save; 546 u8 brp, brpe, sjw, tseg1, tseg2; 547 u32 ten_bit_brp; 548 struct c_can_priv *priv = netdev_priv(dev); 549 const struct can_bittiming *bt = &priv->can.bittiming; 550 int res; 551 552 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 553 ten_bit_brp = bt->brp - 1; 554 brp = ten_bit_brp & BTR_BRP_MASK; 555 brpe = ten_bit_brp >> 6; 556 557 sjw = bt->sjw - 1; 558 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 559 tseg2 = bt->phase_seg2 - 1; 560 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 561 (tseg2 << BTR_TSEG2_SHIFT); 562 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 563 564 netdev_info(dev, 565 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 566 567 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 568 ctrl_save &= ~CONTROL_INIT; 569 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 570 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 571 if (res) 572 return res; 573 574 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 575 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 576 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 577 578 return c_can_wait_for_ctrl_init(dev, priv, 0); 579} 580 581/* 582 * Configure C_CAN message objects for Tx and Rx purposes: 583 * C_CAN provides a total of 32 message objects that can be configured 584 * either for Tx or Rx purposes. Here the first 16 message objects are used as 585 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 586 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 587 * See user guide document for further details on configuring message 588 * objects. 589 */ 590static void c_can_configure_msg_objects(struct net_device *dev) 591{ 592 int i; 593 594 /* first invalidate all message objects */ 595 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 596 c_can_inval_msg_object(dev, IF_RX, i); 597 598 /* setup receive message objects */ 599 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 600 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, 601 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); 602 603 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 604 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); 605} 606 607/* 608 * Configure C_CAN chip: 609 * - enable/disable auto-retransmission 610 * - set operating mode 611 * - configure message objects 612 */ 613static int c_can_chip_config(struct net_device *dev) 614{ 615 struct c_can_priv *priv = netdev_priv(dev); 616 617 /* enable automatic retransmission */ 618 priv->write_reg(priv, C_CAN_CTRL_REG, 619 CONTROL_ENABLE_AR); 620 621 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 622 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 623 /* loopback + silent mode : useful for hot self-test */ 624 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 625 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 626 priv->write_reg(priv, C_CAN_TEST_REG, 627 TEST_LBACK | TEST_SILENT); 628 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 629 /* loopback mode : useful for self-test function */ 630 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 631 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 632 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 633 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 634 /* silent mode : bus-monitoring mode */ 635 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 636 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 637 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 638 } else 639 /* normal mode*/ 640 priv->write_reg(priv, C_CAN_CTRL_REG, 641 CONTROL_EIE | CONTROL_SIE | CONTROL_IE); 642 643 /* configure message objects */ 644 c_can_configure_msg_objects(dev); 645 646 /* set a `lec` value so that we can check for updates later */ 647 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 648 649 /* set bittiming params */ 650 return c_can_set_bittiming(dev); 651} 652 653static int c_can_start(struct net_device *dev) 654{ 655 struct c_can_priv *priv = netdev_priv(dev); 656 int err; 657 658 /* basic c_can configuration */ 659 err = c_can_chip_config(dev); 660 if (err) 661 return err; 662 663 priv->can.state = CAN_STATE_ERROR_ACTIVE; 664 665 /* reset tx helper pointers */ 666 priv->tx_next = priv->tx_echo = 0; 667 668 /* enable status change, error and module interrupts */ 669 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 670 671 return 0; 672} 673 674static void c_can_stop(struct net_device *dev) 675{ 676 struct c_can_priv *priv = netdev_priv(dev); 677 678 /* disable all interrupts */ 679 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 680 681 /* set the state as STOPPED */ 682 priv->can.state = CAN_STATE_STOPPED; 683} 684 685static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 686{ 687 int err; 688 689 switch (mode) { 690 case CAN_MODE_START: 691 err = c_can_start(dev); 692 if (err) 693 return err; 694 netif_wake_queue(dev); 695 break; 696 default: 697 return -EOPNOTSUPP; 698 } 699 700 return 0; 701} 702 703static int __c_can_get_berr_counter(const struct net_device *dev, 704 struct can_berr_counter *bec) 705{ 706 unsigned int reg_err_counter; 707 struct c_can_priv *priv = netdev_priv(dev); 708 709 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 710 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 711 ERR_CNT_REC_SHIFT; 712 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 713 714 return 0; 715} 716 717static int c_can_get_berr_counter(const struct net_device *dev, 718 struct can_berr_counter *bec) 719{ 720 struct c_can_priv *priv = netdev_priv(dev); 721 int err; 722 723 c_can_pm_runtime_get_sync(priv); 724 err = __c_can_get_berr_counter(dev, bec); 725 c_can_pm_runtime_put_sync(priv); 726 727 return err; 728} 729 730/* 731 * priv->tx_echo holds the number of the oldest can_frame put for 732 * transmission into the hardware, but not yet ACKed by the CAN tx 733 * complete IRQ. 734 * 735 * We iterate from priv->tx_echo to priv->tx_next and check if the 736 * packet has been transmitted, echo it back to the CAN framework. 737 * If we discover a not yet transmitted packet, stop looking for more. 738 */ 739static void c_can_do_tx(struct net_device *dev) 740{ 741 struct c_can_priv *priv = netdev_priv(dev); 742 struct net_device_stats *stats = &dev->stats; 743 u32 val, obj, pkts = 0, bytes = 0; 744 745 spin_lock_bh(&priv->xmit_lock); 746 747 for (; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 748 obj = get_tx_echo_msg_obj(priv->tx_echo); 749 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 750 751 if (val & (1 << (obj - 1))) 752 break; 753 754 can_get_echo_skb(dev, obj - C_CAN_MSG_OBJ_TX_FIRST); 755 bytes += priv->dlc[obj - C_CAN_MSG_OBJ_TX_FIRST]; 756 pkts++; 757 c_can_inval_msg_object(dev, IF_TX, obj); 758 } 759 760 /* restart queue if wrap-up or if queue stalled on last pkt */ 761 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 762 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) 763 netif_wake_queue(dev); 764 765 spin_unlock_bh(&priv->xmit_lock); 766 767 if (pkts) { 768 stats->tx_bytes += bytes; 769 stats->tx_packets += pkts; 770 can_led_event(dev, CAN_LED_EVENT_TX); 771 } 772} 773 774/* 775 * If we have a gap in the pending bits, that means we either 776 * raced with the hardware or failed to readout all upper 777 * objects in the last run due to quota limit. 778 */ 779static u32 c_can_adjust_pending(u32 pend) 780{ 781 u32 weight, lasts; 782 783 if (pend == RECEIVE_OBJECT_BITS) 784 return pend; 785 786 /* 787 * If the last set bit is larger than the number of pending 788 * bits we have a gap. 789 */ 790 weight = hweight32(pend); 791 lasts = fls(pend); 792 793 /* If the bits are linear, nothing to do */ 794 if (lasts == weight) 795 return pend; 796 797 /* 798 * Find the first set bit after the gap. We walk backwards 799 * from the last set bit. 800 */ 801 for (lasts--; pend & (1 << (lasts - 1)); lasts--); 802 803 return pend & ~((1 << lasts) - 1); 804} 805 806static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 807 u32 pend, int quota) 808{ 809 u32 pkts = 0, ctrl, obj, mcmd; 810 811 while ((obj = ffs(pend)) && quota > 0) { 812 pend &= ~BIT(obj - 1); 813 814 mcmd = obj < C_CAN_MSG_RX_LOW_LAST ? 815 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 816 817 c_can_object_get(dev, IF_RX, obj, mcmd); 818 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 819 820 if (ctrl & IF_MCONT_MSGLST) { 821 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); 822 823 pkts += n; 824 quota -= n; 825 continue; 826 } 827 828 /* 829 * This really should not happen, but this covers some 830 * odd HW behaviour. Do not remove that unless you 831 * want to brick your machine. 832 */ 833 if (!(ctrl & IF_MCONT_NEWDAT)) 834 continue; 835 836 /* read the data from the message object */ 837 c_can_read_msg_object(dev, IF_RX, ctrl); 838 839 if (obj == C_CAN_MSG_RX_LOW_LAST) 840 /* activate all lower message objects */ 841 c_can_activate_all_lower_rx_msg_obj(dev, IF_RX, ctrl); 842 843 pkts++; 844 quota--; 845 } 846 847 return pkts; 848} 849 850/* 851 * theory of operation: 852 * 853 * c_can core saves a received CAN message into the first free message 854 * object it finds free (starting with the lowest). Bits NEWDAT and 855 * INTPND are set for this message object indicating that a new message 856 * has arrived. To work-around this issue, we keep two groups of message 857 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 858 * 859 * To ensure in-order frame reception we use the following 860 * approach while re-activating a message object to receive further 861 * frames: 862 * - if the current message object number is lower than 863 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 864 * the INTPND bit. 865 * - if the current message object number is equal to 866 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 867 * receive message objects. 868 * - if the current message object number is greater than 869 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 870 * only this message object. 871 */ 872static int c_can_do_rx_poll(struct net_device *dev, int quota) 873{ 874 struct c_can_priv *priv = netdev_priv(dev); 875 u32 pkts = 0, pend = 0, toread, n; 876 877 /* 878 * It is faster to read only one 16bit register. This is only possible 879 * for a maximum number of 16 objects. 880 */ 881 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, 882 "Implementation does not support more message objects than 16"); 883 884 while (quota > 0) { 885 if (!pend) { 886 pend = priv->read_reg(priv, C_CAN_INTPND1_REG); 887 if (!pend) 888 break; 889 /* 890 * If the pending field has a gap, handle the 891 * bits above the gap first. 892 */ 893 toread = c_can_adjust_pending(pend); 894 } else { 895 toread = pend; 896 } 897 /* Remove the bits from pend */ 898 pend &= ~toread; 899 /* Read the objects */ 900 n = c_can_read_objects(dev, priv, toread, quota); 901 pkts += n; 902 quota -= n; 903 } 904 return pkts; 905} 906 907static inline int c_can_has_and_handle_berr(struct c_can_priv *priv) 908{ 909 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 910 (priv->current_status & LEC_UNUSED); 911} 912 913static int c_can_handle_state_change(struct net_device *dev, 914 enum c_can_bus_error_types error_type) 915{ 916 unsigned int reg_err_counter; 917 unsigned int rx_err_passive; 918 struct c_can_priv *priv = netdev_priv(dev); 919 struct net_device_stats *stats = &dev->stats; 920 struct can_frame *cf; 921 struct sk_buff *skb; 922 struct can_berr_counter bec; 923 924 /* propagate the error condition to the CAN stack */ 925 skb = alloc_can_err_skb(dev, &cf); 926 if (unlikely(!skb)) 927 return 0; 928 929 __c_can_get_berr_counter(dev, &bec); 930 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 931 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 932 ERR_CNT_RP_SHIFT; 933 934 switch (error_type) { 935 case C_CAN_ERROR_WARNING: 936 /* error warning state */ 937 priv->can.can_stats.error_warning++; 938 priv->can.state = CAN_STATE_ERROR_WARNING; 939 cf->can_id |= CAN_ERR_CRTL; 940 cf->data[1] = (bec.txerr > bec.rxerr) ? 941 CAN_ERR_CRTL_TX_WARNING : 942 CAN_ERR_CRTL_RX_WARNING; 943 cf->data[6] = bec.txerr; 944 cf->data[7] = bec.rxerr; 945 946 break; 947 case C_CAN_ERROR_PASSIVE: 948 /* error passive state */ 949 priv->can.can_stats.error_passive++; 950 priv->can.state = CAN_STATE_ERROR_PASSIVE; 951 cf->can_id |= CAN_ERR_CRTL; 952 if (rx_err_passive) 953 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 954 if (bec.txerr > 127) 955 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 956 957 cf->data[6] = bec.txerr; 958 cf->data[7] = bec.rxerr; 959 break; 960 case C_CAN_BUS_OFF: 961 /* bus-off state */ 962 priv->can.state = CAN_STATE_BUS_OFF; 963 cf->can_id |= CAN_ERR_BUSOFF; 964 /* 965 * disable all interrupts in bus-off mode to ensure that 966 * the CPU is not hogged down 967 */ 968 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 969 can_bus_off(dev); 970 break; 971 default: 972 break; 973 } 974 975 netif_receive_skb(skb); 976 stats->rx_packets++; 977 stats->rx_bytes += cf->can_dlc; 978 979 return 1; 980} 981 982static int c_can_handle_bus_err(struct net_device *dev, 983 enum c_can_lec_type lec_type) 984{ 985 struct c_can_priv *priv = netdev_priv(dev); 986 struct net_device_stats *stats = &dev->stats; 987 struct can_frame *cf; 988 struct sk_buff *skb; 989 990 /* 991 * early exit if no lec update or no error. 992 * no lec update means that no CAN bus event has been detected 993 * since CPU wrote 0x7 value to status reg. 994 */ 995 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 996 return 0; 997 998 /* propagate the error condition to the CAN stack */ 999 skb = alloc_can_err_skb(dev, &cf); 1000 if (unlikely(!skb)) 1001 return 0; 1002 1003 /* 1004 * check for 'last error code' which tells us the 1005 * type of the last error to occur on the CAN bus 1006 */ 1007 1008 /* common for all type of bus errors */ 1009 priv->can.can_stats.bus_error++; 1010 stats->rx_errors++; 1011 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1012 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 1013 1014 switch (lec_type) { 1015 case LEC_STUFF_ERROR: 1016 netdev_dbg(dev, "stuff error\n"); 1017 cf->data[2] |= CAN_ERR_PROT_STUFF; 1018 break; 1019 case LEC_FORM_ERROR: 1020 netdev_dbg(dev, "form error\n"); 1021 cf->data[2] |= CAN_ERR_PROT_FORM; 1022 break; 1023 case LEC_ACK_ERROR: 1024 netdev_dbg(dev, "ack error\n"); 1025 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 1026 CAN_ERR_PROT_LOC_ACK_DEL); 1027 break; 1028 case LEC_BIT1_ERROR: 1029 netdev_dbg(dev, "bit1 error\n"); 1030 cf->data[2] |= CAN_ERR_PROT_BIT1; 1031 break; 1032 case LEC_BIT0_ERROR: 1033 netdev_dbg(dev, "bit0 error\n"); 1034 cf->data[2] |= CAN_ERR_PROT_BIT0; 1035 break; 1036 case LEC_CRC_ERROR: 1037 netdev_dbg(dev, "CRC error\n"); 1038 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 1039 CAN_ERR_PROT_LOC_CRC_DEL); 1040 break; 1041 default: 1042 break; 1043 } 1044 1045 /* set a `lec` value so that we can check for updates later */ 1046 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1047 1048 netif_receive_skb(skb); 1049 stats->rx_packets++; 1050 stats->rx_bytes += cf->can_dlc; 1051 1052 return 1; 1053} 1054 1055static int c_can_poll(struct napi_struct *napi, int quota) 1056{ 1057 u16 irqstatus; 1058 int lec_type = 0; 1059 int work_done = 0; 1060 struct net_device *dev = napi->dev; 1061 struct c_can_priv *priv = netdev_priv(dev); 1062 1063 irqstatus = priv->irqstatus; 1064 if (!irqstatus) 1065 goto end; 1066 1067 /* status events have the highest priority */ 1068 if (irqstatus == STATUS_INTERRUPT) { 1069 priv->current_status = priv->read_reg(priv, 1070 C_CAN_STS_REG); 1071 1072 /* handle Tx/Rx events */ 1073 if (priv->current_status & STATUS_TXOK) 1074 priv->write_reg(priv, C_CAN_STS_REG, 1075 priv->current_status & ~STATUS_TXOK); 1076 1077 if (priv->current_status & STATUS_RXOK) 1078 priv->write_reg(priv, C_CAN_STS_REG, 1079 priv->current_status & ~STATUS_RXOK); 1080 1081 /* handle state changes */ 1082 if ((priv->current_status & STATUS_EWARN) && 1083 (!(priv->last_status & STATUS_EWARN))) { 1084 netdev_dbg(dev, "entered error warning state\n"); 1085 work_done += c_can_handle_state_change(dev, 1086 C_CAN_ERROR_WARNING); 1087 } 1088 if ((priv->current_status & STATUS_EPASS) && 1089 (!(priv->last_status & STATUS_EPASS))) { 1090 netdev_dbg(dev, "entered error passive state\n"); 1091 work_done += c_can_handle_state_change(dev, 1092 C_CAN_ERROR_PASSIVE); 1093 } 1094 if ((priv->current_status & STATUS_BOFF) && 1095 (!(priv->last_status & STATUS_BOFF))) { 1096 netdev_dbg(dev, "entered bus off state\n"); 1097 work_done += c_can_handle_state_change(dev, 1098 C_CAN_BUS_OFF); 1099 } 1100 1101 /* handle bus recovery events */ 1102 if ((!(priv->current_status & STATUS_BOFF)) && 1103 (priv->last_status & STATUS_BOFF)) { 1104 netdev_dbg(dev, "left bus off state\n"); 1105 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1106 } 1107 if ((!(priv->current_status & STATUS_EPASS)) && 1108 (priv->last_status & STATUS_EPASS)) { 1109 netdev_dbg(dev, "left error passive state\n"); 1110 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1111 } 1112 1113 priv->last_status = priv->current_status; 1114 1115 /* handle lec errors on the bus */ 1116 lec_type = c_can_has_and_handle_berr(priv); 1117 if (lec_type) 1118 work_done += c_can_handle_bus_err(dev, lec_type); 1119 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && 1120 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { 1121 /* handle events corresponding to receive message objects */ 1122 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1123 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && 1124 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { 1125 /* handle events corresponding to transmit message objects */ 1126 c_can_do_tx(dev); 1127 } 1128 1129end: 1130 if (work_done < quota) { 1131 napi_complete(napi); 1132 /* enable all IRQs */ 1133 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1134 } 1135 1136 return work_done; 1137} 1138 1139static irqreturn_t c_can_isr(int irq, void *dev_id) 1140{ 1141 struct net_device *dev = (struct net_device *)dev_id; 1142 struct c_can_priv *priv = netdev_priv(dev); 1143 1144 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); 1145 if (!priv->irqstatus) 1146 return IRQ_NONE; 1147 1148 /* disable all interrupts and schedule the NAPI */ 1149 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1150 napi_schedule(&priv->napi); 1151 1152 return IRQ_HANDLED; 1153} 1154 1155static int c_can_open(struct net_device *dev) 1156{ 1157 int err; 1158 struct c_can_priv *priv = netdev_priv(dev); 1159 1160 c_can_pm_runtime_get_sync(priv); 1161 c_can_reset_ram(priv, true); 1162 1163 /* open the can device */ 1164 err = open_candev(dev); 1165 if (err) { 1166 netdev_err(dev, "failed to open can device\n"); 1167 goto exit_open_fail; 1168 } 1169 1170 /* register interrupt handler */ 1171 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1172 dev); 1173 if (err < 0) { 1174 netdev_err(dev, "failed to request interrupt\n"); 1175 goto exit_irq_fail; 1176 } 1177 1178 /* start the c_can controller */ 1179 err = c_can_start(dev); 1180 if (err) 1181 goto exit_start_fail; 1182 1183 can_led_event(dev, CAN_LED_EVENT_OPEN); 1184 1185 napi_enable(&priv->napi); 1186 netif_start_queue(dev); 1187 1188 return 0; 1189 1190exit_start_fail: 1191 free_irq(dev->irq, dev); 1192exit_irq_fail: 1193 close_candev(dev); 1194exit_open_fail: 1195 c_can_reset_ram(priv, false); 1196 c_can_pm_runtime_put_sync(priv); 1197 return err; 1198} 1199 1200static int c_can_close(struct net_device *dev) 1201{ 1202 struct c_can_priv *priv = netdev_priv(dev); 1203 1204 netif_stop_queue(dev); 1205 napi_disable(&priv->napi); 1206 c_can_stop(dev); 1207 free_irq(dev->irq, dev); 1208 close_candev(dev); 1209 1210 c_can_reset_ram(priv, false); 1211 c_can_pm_runtime_put_sync(priv); 1212 1213 can_led_event(dev, CAN_LED_EVENT_STOP); 1214 1215 return 0; 1216} 1217 1218struct net_device *alloc_c_can_dev(void) 1219{ 1220 struct net_device *dev; 1221 struct c_can_priv *priv; 1222 1223 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1224 if (!dev) 1225 return NULL; 1226 1227 priv = netdev_priv(dev); 1228 spin_lock_init(&priv->xmit_lock); 1229 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1230 1231 priv->dev = dev; 1232 priv->can.bittiming_const = &c_can_bittiming_const; 1233 priv->can.do_set_mode = c_can_set_mode; 1234 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1235 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1236 CAN_CTRLMODE_LISTENONLY | 1237 CAN_CTRLMODE_BERR_REPORTING; 1238 1239 return dev; 1240} 1241EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1242 1243#ifdef CONFIG_PM 1244int c_can_power_down(struct net_device *dev) 1245{ 1246 u32 val; 1247 unsigned long time_out; 1248 struct c_can_priv *priv = netdev_priv(dev); 1249 1250 if (!(dev->flags & IFF_UP)) 1251 return 0; 1252 1253 WARN_ON(priv->type != BOSCH_D_CAN); 1254 1255 /* set PDR value so the device goes to power down mode */ 1256 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1257 val |= CONTROL_EX_PDR; 1258 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1259 1260 /* Wait for the PDA bit to get set */ 1261 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1262 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1263 time_after(time_out, jiffies)) 1264 cpu_relax(); 1265 1266 if (time_after(jiffies, time_out)) 1267 return -ETIMEDOUT; 1268 1269 c_can_stop(dev); 1270 1271 c_can_reset_ram(priv, false); 1272 c_can_pm_runtime_put_sync(priv); 1273 1274 return 0; 1275} 1276EXPORT_SYMBOL_GPL(c_can_power_down); 1277 1278int c_can_power_up(struct net_device *dev) 1279{ 1280 u32 val; 1281 unsigned long time_out; 1282 struct c_can_priv *priv = netdev_priv(dev); 1283 1284 if (!(dev->flags & IFF_UP)) 1285 return 0; 1286 1287 WARN_ON(priv->type != BOSCH_D_CAN); 1288 1289 c_can_pm_runtime_get_sync(priv); 1290 c_can_reset_ram(priv, true); 1291 1292 /* Clear PDR and INIT bits */ 1293 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1294 val &= ~CONTROL_EX_PDR; 1295 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1296 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1297 val &= ~CONTROL_INIT; 1298 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1299 1300 /* Wait for the PDA bit to get clear */ 1301 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1302 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1303 time_after(time_out, jiffies)) 1304 cpu_relax(); 1305 1306 if (time_after(jiffies, time_out)) 1307 return -ETIMEDOUT; 1308 1309 return c_can_start(dev); 1310} 1311EXPORT_SYMBOL_GPL(c_can_power_up); 1312#endif 1313 1314void free_c_can_dev(struct net_device *dev) 1315{ 1316 struct c_can_priv *priv = netdev_priv(dev); 1317 1318 netif_napi_del(&priv->napi); 1319 free_candev(dev); 1320} 1321EXPORT_SYMBOL_GPL(free_c_can_dev); 1322 1323static const struct net_device_ops c_can_netdev_ops = { 1324 .ndo_open = c_can_open, 1325 .ndo_stop = c_can_close, 1326 .ndo_start_xmit = c_can_start_xmit, 1327}; 1328 1329int register_c_can_dev(struct net_device *dev) 1330{ 1331 struct c_can_priv *priv = netdev_priv(dev); 1332 int err; 1333 1334 c_can_pm_runtime_enable(priv); 1335 1336 dev->flags |= IFF_ECHO; /* we support local echo */ 1337 dev->netdev_ops = &c_can_netdev_ops; 1338 1339 err = register_candev(dev); 1340 if (err) 1341 c_can_pm_runtime_disable(priv); 1342 else 1343 devm_can_led_init(dev); 1344 1345 return err; 1346} 1347EXPORT_SYMBOL_GPL(register_c_can_dev); 1348 1349void unregister_c_can_dev(struct net_device *dev) 1350{ 1351 struct c_can_priv *priv = netdev_priv(dev); 1352 1353 unregister_candev(dev); 1354 1355 c_can_pm_runtime_disable(priv); 1356} 1357EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1358 1359MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1360MODULE_LICENSE("GPL v2"); 1361MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1362