c_can.c revision 64f08f2f3544eb8b6b14fd35e6087d7d3ede77cd
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42#include <linux/can/led.h> 43 44#include "c_can.h" 45 46/* Number of interface registers */ 47#define IF_ENUM_REG_LEN 11 48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 49 50/* control extension register D_CAN specific */ 51#define CONTROL_EX_PDR BIT(8) 52 53/* control register */ 54#define CONTROL_TEST BIT(7) 55#define CONTROL_CCE BIT(6) 56#define CONTROL_DISABLE_AR BIT(5) 57#define CONTROL_ENABLE_AR (0 << 5) 58#define CONTROL_EIE BIT(3) 59#define CONTROL_SIE BIT(2) 60#define CONTROL_IE BIT(1) 61#define CONTROL_INIT BIT(0) 62 63/* test register */ 64#define TEST_RX BIT(7) 65#define TEST_TX1 BIT(6) 66#define TEST_TX2 BIT(5) 67#define TEST_LBACK BIT(4) 68#define TEST_SILENT BIT(3) 69#define TEST_BASIC BIT(2) 70 71/* status register */ 72#define STATUS_PDA BIT(10) 73#define STATUS_BOFF BIT(7) 74#define STATUS_EWARN BIT(6) 75#define STATUS_EPASS BIT(5) 76#define STATUS_RXOK BIT(4) 77#define STATUS_TXOK BIT(3) 78 79/* error counter register */ 80#define ERR_CNT_TEC_MASK 0xff 81#define ERR_CNT_TEC_SHIFT 0 82#define ERR_CNT_REC_SHIFT 8 83#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 84#define ERR_CNT_RP_SHIFT 15 85#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 86 87/* bit-timing register */ 88#define BTR_BRP_MASK 0x3f 89#define BTR_BRP_SHIFT 0 90#define BTR_SJW_SHIFT 6 91#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 92#define BTR_TSEG1_SHIFT 8 93#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 94#define BTR_TSEG2_SHIFT 12 95#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 96 97/* brp extension register */ 98#define BRP_EXT_BRPE_MASK 0x0f 99#define BRP_EXT_BRPE_SHIFT 0 100 101/* IFx command request */ 102#define IF_COMR_BUSY BIT(15) 103 104/* IFx command mask */ 105#define IF_COMM_WR BIT(7) 106#define IF_COMM_MASK BIT(6) 107#define IF_COMM_ARB BIT(5) 108#define IF_COMM_CONTROL BIT(4) 109#define IF_COMM_CLR_INT_PND BIT(3) 110#define IF_COMM_TXRQST BIT(2) 111#define IF_COMM_DATAA BIT(1) 112#define IF_COMM_DATAB BIT(0) 113#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ 114 IF_COMM_CONTROL | IF_COMM_TXRQST | \ 115 IF_COMM_DATAA | IF_COMM_DATAB) 116 117/* IFx arbitration */ 118#define IF_ARB_MSGVAL BIT(15) 119#define IF_ARB_MSGXTD BIT(14) 120#define IF_ARB_TRANSMIT BIT(13) 121 122/* IFx message control */ 123#define IF_MCONT_NEWDAT BIT(15) 124#define IF_MCONT_MSGLST BIT(14) 125#define IF_MCONT_CLR_MSGLST (0 << 14) 126#define IF_MCONT_INTPND BIT(13) 127#define IF_MCONT_UMASK BIT(12) 128#define IF_MCONT_TXIE BIT(11) 129#define IF_MCONT_RXIE BIT(10) 130#define IF_MCONT_RMTEN BIT(9) 131#define IF_MCONT_TXRQST BIT(8) 132#define IF_MCONT_EOB BIT(7) 133#define IF_MCONT_DLC_MASK 0xf 134 135/* 136 * Use IF1 for RX and IF2 for TX 137 */ 138#define IF_RX 0 139#define IF_TX 1 140 141/* 142 * IFx register masks: 143 * allow easy operation on 16-bit registers when the 144 * argument is 32-bit instead 145 */ 146#define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF) 147#define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16) 148 149/* message object split */ 150#define C_CAN_NO_OF_OBJECTS 32 151#define C_CAN_MSG_OBJ_RX_NUM 16 152#define C_CAN_MSG_OBJ_TX_NUM 16 153 154#define C_CAN_MSG_OBJ_RX_FIRST 1 155#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \ 156 C_CAN_MSG_OBJ_RX_NUM - 1) 157 158#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1) 159#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \ 160 C_CAN_MSG_OBJ_TX_NUM - 1) 161 162#define C_CAN_MSG_OBJ_RX_SPLIT 9 163#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1) 164 165#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1) 166#define RECEIVE_OBJECT_BITS 0x0000ffff 167 168/* status interrupt */ 169#define STATUS_INTERRUPT 0x8000 170 171/* global interrupt masks */ 172#define ENABLE_ALL_INTERRUPTS 1 173#define DISABLE_ALL_INTERRUPTS 0 174 175/* minimum timeout for checking BUSY status */ 176#define MIN_TIMEOUT_VALUE 6 177 178/* Wait for ~1 sec for INIT bit */ 179#define INIT_WAIT_MS 1000 180 181/* napi related */ 182#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 183 184/* c_can lec values */ 185enum c_can_lec_type { 186 LEC_NO_ERROR = 0, 187 LEC_STUFF_ERROR, 188 LEC_FORM_ERROR, 189 LEC_ACK_ERROR, 190 LEC_BIT1_ERROR, 191 LEC_BIT0_ERROR, 192 LEC_CRC_ERROR, 193 LEC_UNUSED, 194}; 195 196/* 197 * c_can error types: 198 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 199 */ 200enum c_can_bus_error_types { 201 C_CAN_NO_ERROR = 0, 202 C_CAN_BUS_OFF, 203 C_CAN_ERROR_WARNING, 204 C_CAN_ERROR_PASSIVE, 205}; 206 207static const struct can_bittiming_const c_can_bittiming_const = { 208 .name = KBUILD_MODNAME, 209 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 210 .tseg1_max = 16, 211 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 212 .tseg2_max = 8, 213 .sjw_max = 4, 214 .brp_min = 1, 215 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 216 .brp_inc = 1, 217}; 218 219static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 220{ 221 if (priv->device) 222 pm_runtime_enable(priv->device); 223} 224 225static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 226{ 227 if (priv->device) 228 pm_runtime_disable(priv->device); 229} 230 231static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 232{ 233 if (priv->device) 234 pm_runtime_get_sync(priv->device); 235} 236 237static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 238{ 239 if (priv->device) 240 pm_runtime_put_sync(priv->device); 241} 242 243static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 244{ 245 if (priv->raminit) 246 priv->raminit(priv, enable); 247} 248 249static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 250{ 251 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + 252 C_CAN_MSG_OBJ_TX_FIRST; 253} 254 255static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv) 256{ 257 return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) + 258 C_CAN_MSG_OBJ_TX_FIRST; 259} 260 261static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) 262{ 263 u32 val = priv->read_reg(priv, index); 264 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 265 return val; 266} 267 268static void c_can_enable_all_interrupts(struct c_can_priv *priv, 269 int enable) 270{ 271 unsigned int cntrl_save = priv->read_reg(priv, 272 C_CAN_CTRL_REG); 273 274 if (enable) 275 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 276 else 277 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); 278 279 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); 280} 281 282static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 283{ 284 int count = MIN_TIMEOUT_VALUE; 285 286 while (count && priv->read_reg(priv, 287 C_CAN_IFACE(COMREQ_REG, iface)) & 288 IF_COMR_BUSY) { 289 count--; 290 udelay(1); 291 } 292 293 if (!count) 294 return 1; 295 296 return 0; 297} 298 299static inline void c_can_object_get(struct net_device *dev, 300 int iface, int objno, int mask) 301{ 302 struct c_can_priv *priv = netdev_priv(dev); 303 304 /* 305 * As per specs, after writting the message object number in the 306 * IF command request register the transfer b/w interface 307 * register and message RAM must be complete in 6 CAN-CLK 308 * period. 309 */ 310 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 311 IFX_WRITE_LOW_16BIT(mask)); 312 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 313 IFX_WRITE_LOW_16BIT(objno)); 314 315 if (c_can_msg_obj_is_busy(priv, iface)) 316 netdev_err(dev, "timed out in object get\n"); 317} 318 319static inline void c_can_object_put(struct net_device *dev, 320 int iface, int objno, int mask) 321{ 322 struct c_can_priv *priv = netdev_priv(dev); 323 324 /* 325 * As per specs, after writting the message object number in the 326 * IF command request register the transfer b/w interface 327 * register and message RAM must be complete in 6 CAN-CLK 328 * period. 329 */ 330 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 331 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); 332 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 333 IFX_WRITE_LOW_16BIT(objno)); 334 335 if (c_can_msg_obj_is_busy(priv, iface)) 336 netdev_err(dev, "timed out in object put\n"); 337} 338 339static void c_can_write_msg_object(struct net_device *dev, 340 int iface, struct can_frame *frame, int objno) 341{ 342 int i; 343 u16 flags = 0; 344 unsigned int id; 345 struct c_can_priv *priv = netdev_priv(dev); 346 347 if (!(frame->can_id & CAN_RTR_FLAG)) 348 flags |= IF_ARB_TRANSMIT; 349 350 if (frame->can_id & CAN_EFF_FLAG) { 351 id = frame->can_id & CAN_EFF_MASK; 352 flags |= IF_ARB_MSGXTD; 353 } else 354 id = ((frame->can_id & CAN_SFF_MASK) << 18); 355 356 flags |= IF_ARB_MSGVAL; 357 358 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 359 IFX_WRITE_LOW_16BIT(id)); 360 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | 361 IFX_WRITE_HIGH_16BIT(id)); 362 363 for (i = 0; i < frame->can_dlc; i += 2) { 364 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 365 frame->data[i] | (frame->data[i + 1] << 8)); 366 } 367 368 /* enable interrupt for this message object */ 369 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 370 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | 371 frame->can_dlc); 372 c_can_object_put(dev, iface, objno, IF_COMM_ALL); 373} 374 375static inline void c_can_mark_rx_msg_obj(struct net_device *dev, 376 int iface, int ctrl_mask, 377 int obj) 378{ 379 struct c_can_priv *priv = netdev_priv(dev); 380 381 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 382 ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND)); 383 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); 384 385} 386 387static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 388 int iface, 389 int ctrl_mask) 390{ 391 int i; 392 struct c_can_priv *priv = netdev_priv(dev); 393 394 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { 395 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 396 ctrl_mask & ~(IF_MCONT_MSGLST | 397 IF_MCONT_INTPND | IF_MCONT_NEWDAT)); 398 c_can_object_put(dev, iface, i, IF_COMM_CONTROL); 399 } 400} 401 402static inline void c_can_activate_rx_msg_obj(struct net_device *dev, 403 int iface, int ctrl_mask, 404 int obj) 405{ 406 struct c_can_priv *priv = netdev_priv(dev); 407 408 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 409 ctrl_mask & ~(IF_MCONT_MSGLST | 410 IF_MCONT_INTPND | IF_MCONT_NEWDAT)); 411 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); 412} 413 414static void c_can_handle_lost_msg_obj(struct net_device *dev, 415 int iface, int objno) 416{ 417 struct c_can_priv *priv = netdev_priv(dev); 418 struct net_device_stats *stats = &dev->stats; 419 struct sk_buff *skb; 420 struct can_frame *frame; 421 422 netdev_err(dev, "msg lost in buffer %d\n", objno); 423 424 c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 425 426 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 427 IF_MCONT_CLR_MSGLST); 428 429 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 430 431 /* create an error msg */ 432 skb = alloc_can_err_skb(dev, &frame); 433 if (unlikely(!skb)) 434 return; 435 436 frame->can_id |= CAN_ERR_CRTL; 437 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 438 stats->rx_errors++; 439 stats->rx_over_errors++; 440 441 netif_receive_skb(skb); 442} 443 444static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) 445{ 446 u16 flags, data; 447 int i; 448 unsigned int val; 449 struct c_can_priv *priv = netdev_priv(dev); 450 struct net_device_stats *stats = &dev->stats; 451 struct sk_buff *skb; 452 struct can_frame *frame; 453 454 skb = alloc_can_skb(dev, &frame); 455 if (!skb) { 456 stats->rx_dropped++; 457 return -ENOMEM; 458 } 459 460 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 461 462 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); 463 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | 464 (flags << 16); 465 466 if (flags & IF_ARB_MSGXTD) 467 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; 468 else 469 frame->can_id = (val >> 18) & CAN_SFF_MASK; 470 471 if (flags & IF_ARB_TRANSMIT) 472 frame->can_id |= CAN_RTR_FLAG; 473 else { 474 for (i = 0; i < frame->can_dlc; i += 2) { 475 data = priv->read_reg(priv, 476 C_CAN_IFACE(DATA1_REG, iface) + i / 2); 477 frame->data[i] = data; 478 frame->data[i + 1] = data >> 8; 479 } 480 } 481 482 netif_receive_skb(skb); 483 484 stats->rx_packets++; 485 stats->rx_bytes += frame->can_dlc; 486 487 can_led_event(dev, CAN_LED_EVENT_RX); 488 489 return 0; 490} 491 492static void c_can_setup_receive_object(struct net_device *dev, int iface, 493 int objno, unsigned int mask, 494 unsigned int id, unsigned int mcont) 495{ 496 struct c_can_priv *priv = netdev_priv(dev); 497 498 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), 499 IFX_WRITE_LOW_16BIT(mask)); 500 501 /* According to C_CAN documentation, the reserved bit 502 * in IFx_MASK2 register is fixed 1 503 */ 504 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), 505 IFX_WRITE_HIGH_16BIT(mask) | BIT(13)); 506 507 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 508 IFX_WRITE_LOW_16BIT(id)); 509 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 510 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); 511 512 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 513 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 514 515 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 516 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 517} 518 519static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) 520{ 521 struct c_can_priv *priv = netdev_priv(dev); 522 523 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 524 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 525 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 526 527 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); 528 529 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 530 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 531} 532 533static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 534{ 535 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 536 537 /* 538 * as transmission request register's bit n-1 corresponds to 539 * message object n, we need to handle the same properly. 540 */ 541 if (val & (1 << (objno - 1))) 542 return 1; 543 544 return 0; 545} 546 547static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 548 struct net_device *dev) 549{ 550 u32 msg_obj_no; 551 struct c_can_priv *priv = netdev_priv(dev); 552 struct can_frame *frame = (struct can_frame *)skb->data; 553 554 if (can_dropped_invalid_skb(dev, skb)) 555 return NETDEV_TX_OK; 556 557 msg_obj_no = get_tx_next_msg_obj(priv); 558 559 /* prepare message object for transmission */ 560 c_can_write_msg_object(dev, IF_TX, frame, msg_obj_no); 561 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 562 563 /* 564 * we have to stop the queue in case of a wrap around or 565 * if the next TX message object is still in use 566 */ 567 priv->tx_next++; 568 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 569 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 570 netif_stop_queue(dev); 571 572 return NETDEV_TX_OK; 573} 574 575static int c_can_wait_for_ctrl_init(struct net_device *dev, 576 struct c_can_priv *priv, u32 init) 577{ 578 int retry = 0; 579 580 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 581 udelay(10); 582 if (retry++ > 1000) { 583 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 584 return -EIO; 585 } 586 } 587 return 0; 588} 589 590static int c_can_set_bittiming(struct net_device *dev) 591{ 592 unsigned int reg_btr, reg_brpe, ctrl_save; 593 u8 brp, brpe, sjw, tseg1, tseg2; 594 u32 ten_bit_brp; 595 struct c_can_priv *priv = netdev_priv(dev); 596 const struct can_bittiming *bt = &priv->can.bittiming; 597 int res; 598 599 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 600 ten_bit_brp = bt->brp - 1; 601 brp = ten_bit_brp & BTR_BRP_MASK; 602 brpe = ten_bit_brp >> 6; 603 604 sjw = bt->sjw - 1; 605 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 606 tseg2 = bt->phase_seg2 - 1; 607 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 608 (tseg2 << BTR_TSEG2_SHIFT); 609 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 610 611 netdev_info(dev, 612 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 613 614 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 615 ctrl_save &= ~CONTROL_INIT; 616 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 617 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 618 if (res) 619 return res; 620 621 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 622 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 623 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 624 625 return c_can_wait_for_ctrl_init(dev, priv, 0); 626} 627 628/* 629 * Configure C_CAN message objects for Tx and Rx purposes: 630 * C_CAN provides a total of 32 message objects that can be configured 631 * either for Tx or Rx purposes. Here the first 16 message objects are used as 632 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 633 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 634 * See user guide document for further details on configuring message 635 * objects. 636 */ 637static void c_can_configure_msg_objects(struct net_device *dev) 638{ 639 int i; 640 641 /* first invalidate all message objects */ 642 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 643 c_can_inval_msg_object(dev, IF_RX, i); 644 645 /* setup receive message objects */ 646 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 647 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, 648 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); 649 650 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 651 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); 652} 653 654/* 655 * Configure C_CAN chip: 656 * - enable/disable auto-retransmission 657 * - set operating mode 658 * - configure message objects 659 */ 660static int c_can_chip_config(struct net_device *dev) 661{ 662 struct c_can_priv *priv = netdev_priv(dev); 663 664 /* enable automatic retransmission */ 665 priv->write_reg(priv, C_CAN_CTRL_REG, 666 CONTROL_ENABLE_AR); 667 668 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 669 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 670 /* loopback + silent mode : useful for hot self-test */ 671 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 672 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 673 priv->write_reg(priv, C_CAN_TEST_REG, 674 TEST_LBACK | TEST_SILENT); 675 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 676 /* loopback mode : useful for self-test function */ 677 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 678 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 679 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 680 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 681 /* silent mode : bus-monitoring mode */ 682 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 683 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 684 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 685 } else 686 /* normal mode*/ 687 priv->write_reg(priv, C_CAN_CTRL_REG, 688 CONTROL_EIE | CONTROL_SIE | CONTROL_IE); 689 690 /* configure message objects */ 691 c_can_configure_msg_objects(dev); 692 693 /* set a `lec` value so that we can check for updates later */ 694 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 695 696 /* set bittiming params */ 697 return c_can_set_bittiming(dev); 698} 699 700static int c_can_start(struct net_device *dev) 701{ 702 struct c_can_priv *priv = netdev_priv(dev); 703 int err; 704 705 /* basic c_can configuration */ 706 err = c_can_chip_config(dev); 707 if (err) 708 return err; 709 710 priv->can.state = CAN_STATE_ERROR_ACTIVE; 711 712 /* reset tx helper pointers */ 713 priv->tx_next = priv->tx_echo = 0; 714 715 /* enable status change, error and module interrupts */ 716 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 717 718 return 0; 719} 720 721static void c_can_stop(struct net_device *dev) 722{ 723 struct c_can_priv *priv = netdev_priv(dev); 724 725 /* disable all interrupts */ 726 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 727 728 /* set the state as STOPPED */ 729 priv->can.state = CAN_STATE_STOPPED; 730} 731 732static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 733{ 734 int err; 735 736 switch (mode) { 737 case CAN_MODE_START: 738 err = c_can_start(dev); 739 if (err) 740 return err; 741 netif_wake_queue(dev); 742 break; 743 default: 744 return -EOPNOTSUPP; 745 } 746 747 return 0; 748} 749 750static int __c_can_get_berr_counter(const struct net_device *dev, 751 struct can_berr_counter *bec) 752{ 753 unsigned int reg_err_counter; 754 struct c_can_priv *priv = netdev_priv(dev); 755 756 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 757 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 758 ERR_CNT_REC_SHIFT; 759 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 760 761 return 0; 762} 763 764static int c_can_get_berr_counter(const struct net_device *dev, 765 struct can_berr_counter *bec) 766{ 767 struct c_can_priv *priv = netdev_priv(dev); 768 int err; 769 770 c_can_pm_runtime_get_sync(priv); 771 err = __c_can_get_berr_counter(dev, bec); 772 c_can_pm_runtime_put_sync(priv); 773 774 return err; 775} 776 777/* 778 * theory of operation: 779 * 780 * priv->tx_echo holds the number of the oldest can_frame put for 781 * transmission into the hardware, but not yet ACKed by the CAN tx 782 * complete IRQ. 783 * 784 * We iterate from priv->tx_echo to priv->tx_next and check if the 785 * packet has been transmitted, echo it back to the CAN framework. 786 * If we discover a not yet transmitted packet, stop looking for more. 787 */ 788static void c_can_do_tx(struct net_device *dev) 789{ 790 u32 val; 791 u32 msg_obj_no; 792 struct c_can_priv *priv = netdev_priv(dev); 793 struct net_device_stats *stats = &dev->stats; 794 795 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 796 msg_obj_no = get_tx_echo_msg_obj(priv); 797 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 798 if (!(val & (1 << (msg_obj_no - 1)))) { 799 can_get_echo_skb(dev, 800 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 801 c_can_object_get(dev, IF_TX, msg_obj_no, IF_COMM_ALL); 802 stats->tx_bytes += priv->read_reg(priv, 803 C_CAN_IFACE(MSGCTRL_REG, IF_TX)) 804 & IF_MCONT_DLC_MASK; 805 stats->tx_packets++; 806 can_led_event(dev, CAN_LED_EVENT_TX); 807 c_can_inval_msg_object(dev, IF_TX, msg_obj_no); 808 } else { 809 break; 810 } 811 } 812 813 /* restart queue if wrap-up or if queue stalled on last pkt */ 814 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 815 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) 816 netif_wake_queue(dev); 817} 818 819/* 820 * If we have a gap in the pending bits, that means we either 821 * raced with the hardware or failed to readout all upper 822 * objects in the last run due to quota limit. 823 */ 824static u32 c_can_adjust_pending(u32 pend) 825{ 826 u32 weight, lasts; 827 828 if (pend == RECEIVE_OBJECT_BITS) 829 return pend; 830 831 /* 832 * If the last set bit is larger than the number of pending 833 * bits we have a gap. 834 */ 835 weight = hweight32(pend); 836 lasts = fls(pend); 837 838 /* If the bits are linear, nothing to do */ 839 if (lasts == weight) 840 return pend; 841 842 /* 843 * Find the first set bit after the gap. We walk backwards 844 * from the last set bit. 845 */ 846 for (lasts--; pend & (1 << (lasts - 1)); lasts--); 847 848 return pend & ~((1 << lasts) - 1); 849} 850 851/* 852 * theory of operation: 853 * 854 * c_can core saves a received CAN message into the first free message 855 * object it finds free (starting with the lowest). Bits NEWDAT and 856 * INTPND are set for this message object indicating that a new message 857 * has arrived. To work-around this issue, we keep two groups of message 858 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 859 * 860 * To ensure in-order frame reception we use the following 861 * approach while re-activating a message object to receive further 862 * frames: 863 * - if the current message object number is lower than 864 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 865 * the INTPND bit. 866 * - if the current message object number is equal to 867 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 868 * receive message objects. 869 * - if the current message object number is greater than 870 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 871 * only this message object. 872 */ 873static int c_can_do_rx_poll(struct net_device *dev, int quota) 874{ 875 u32 num_rx_pkts = 0; 876 unsigned int msg_obj, msg_ctrl_save; 877 struct c_can_priv *priv = netdev_priv(dev); 878 u32 val, pend = 0; 879 880 /* 881 * It is faster to read only one 16bit register. This is only possible 882 * for a maximum number of 16 objects. 883 */ 884 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, 885 "Implementation does not support more message objects than 16"); 886 887 while (quota > 0) { 888 889 if (!pend) { 890 pend = priv->read_reg(priv, C_CAN_INTPND1_REG); 891 if (!pend) 892 return num_rx_pkts; 893 /* 894 * If the pending field has a gap, handle the 895 * bits above the gap first. 896 */ 897 val = c_can_adjust_pending(pend); 898 } else { 899 val = pend; 900 } 901 /* Remove the bits from pend */ 902 pend &= ~val; 903 904 while ((msg_obj = ffs(val)) && quota > 0) { 905 val &= ~BIT(msg_obj - 1); 906 907 c_can_object_get(dev, IF_RX, msg_obj, IF_COMM_ALL & 908 ~IF_COMM_TXRQST); 909 msg_ctrl_save = priv->read_reg(priv, 910 C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 911 912 if (msg_ctrl_save & IF_MCONT_MSGLST) { 913 c_can_handle_lost_msg_obj(dev, IF_RX, msg_obj); 914 num_rx_pkts++; 915 quota--; 916 continue; 917 } 918 919 if (msg_ctrl_save & IF_MCONT_EOB) 920 return num_rx_pkts; 921 922 if (!(msg_ctrl_save & IF_MCONT_NEWDAT)) 923 continue; 924 925 /* read the data from the message object */ 926 c_can_read_msg_object(dev, IF_RX, msg_ctrl_save); 927 928 if (msg_obj < C_CAN_MSG_RX_LOW_LAST) 929 c_can_mark_rx_msg_obj(dev, IF_RX, 930 msg_ctrl_save, msg_obj); 931 else if (msg_obj > C_CAN_MSG_RX_LOW_LAST) 932 /* activate this msg obj */ 933 c_can_activate_rx_msg_obj(dev, IF_RX, 934 msg_ctrl_save, msg_obj); 935 else if (msg_obj == C_CAN_MSG_RX_LOW_LAST) 936 /* activate all lower message objects */ 937 c_can_activate_all_lower_rx_msg_obj(dev, 938 IF_RX, msg_ctrl_save); 939 940 num_rx_pkts++; 941 quota--; 942 } 943 } 944 945 return num_rx_pkts; 946} 947 948static inline int c_can_has_and_handle_berr(struct c_can_priv *priv) 949{ 950 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 951 (priv->current_status & LEC_UNUSED); 952} 953 954static int c_can_handle_state_change(struct net_device *dev, 955 enum c_can_bus_error_types error_type) 956{ 957 unsigned int reg_err_counter; 958 unsigned int rx_err_passive; 959 struct c_can_priv *priv = netdev_priv(dev); 960 struct net_device_stats *stats = &dev->stats; 961 struct can_frame *cf; 962 struct sk_buff *skb; 963 struct can_berr_counter bec; 964 965 /* propagate the error condition to the CAN stack */ 966 skb = alloc_can_err_skb(dev, &cf); 967 if (unlikely(!skb)) 968 return 0; 969 970 __c_can_get_berr_counter(dev, &bec); 971 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 972 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 973 ERR_CNT_RP_SHIFT; 974 975 switch (error_type) { 976 case C_CAN_ERROR_WARNING: 977 /* error warning state */ 978 priv->can.can_stats.error_warning++; 979 priv->can.state = CAN_STATE_ERROR_WARNING; 980 cf->can_id |= CAN_ERR_CRTL; 981 cf->data[1] = (bec.txerr > bec.rxerr) ? 982 CAN_ERR_CRTL_TX_WARNING : 983 CAN_ERR_CRTL_RX_WARNING; 984 cf->data[6] = bec.txerr; 985 cf->data[7] = bec.rxerr; 986 987 break; 988 case C_CAN_ERROR_PASSIVE: 989 /* error passive state */ 990 priv->can.can_stats.error_passive++; 991 priv->can.state = CAN_STATE_ERROR_PASSIVE; 992 cf->can_id |= CAN_ERR_CRTL; 993 if (rx_err_passive) 994 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 995 if (bec.txerr > 127) 996 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 997 998 cf->data[6] = bec.txerr; 999 cf->data[7] = bec.rxerr; 1000 break; 1001 case C_CAN_BUS_OFF: 1002 /* bus-off state */ 1003 priv->can.state = CAN_STATE_BUS_OFF; 1004 cf->can_id |= CAN_ERR_BUSOFF; 1005 /* 1006 * disable all interrupts in bus-off mode to ensure that 1007 * the CPU is not hogged down 1008 */ 1009 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1010 can_bus_off(dev); 1011 break; 1012 default: 1013 break; 1014 } 1015 1016 netif_receive_skb(skb); 1017 stats->rx_packets++; 1018 stats->rx_bytes += cf->can_dlc; 1019 1020 return 1; 1021} 1022 1023static int c_can_handle_bus_err(struct net_device *dev, 1024 enum c_can_lec_type lec_type) 1025{ 1026 struct c_can_priv *priv = netdev_priv(dev); 1027 struct net_device_stats *stats = &dev->stats; 1028 struct can_frame *cf; 1029 struct sk_buff *skb; 1030 1031 /* 1032 * early exit if no lec update or no error. 1033 * no lec update means that no CAN bus event has been detected 1034 * since CPU wrote 0x7 value to status reg. 1035 */ 1036 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 1037 return 0; 1038 1039 /* propagate the error condition to the CAN stack */ 1040 skb = alloc_can_err_skb(dev, &cf); 1041 if (unlikely(!skb)) 1042 return 0; 1043 1044 /* 1045 * check for 'last error code' which tells us the 1046 * type of the last error to occur on the CAN bus 1047 */ 1048 1049 /* common for all type of bus errors */ 1050 priv->can.can_stats.bus_error++; 1051 stats->rx_errors++; 1052 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1053 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 1054 1055 switch (lec_type) { 1056 case LEC_STUFF_ERROR: 1057 netdev_dbg(dev, "stuff error\n"); 1058 cf->data[2] |= CAN_ERR_PROT_STUFF; 1059 break; 1060 case LEC_FORM_ERROR: 1061 netdev_dbg(dev, "form error\n"); 1062 cf->data[2] |= CAN_ERR_PROT_FORM; 1063 break; 1064 case LEC_ACK_ERROR: 1065 netdev_dbg(dev, "ack error\n"); 1066 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 1067 CAN_ERR_PROT_LOC_ACK_DEL); 1068 break; 1069 case LEC_BIT1_ERROR: 1070 netdev_dbg(dev, "bit1 error\n"); 1071 cf->data[2] |= CAN_ERR_PROT_BIT1; 1072 break; 1073 case LEC_BIT0_ERROR: 1074 netdev_dbg(dev, "bit0 error\n"); 1075 cf->data[2] |= CAN_ERR_PROT_BIT0; 1076 break; 1077 case LEC_CRC_ERROR: 1078 netdev_dbg(dev, "CRC error\n"); 1079 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 1080 CAN_ERR_PROT_LOC_CRC_DEL); 1081 break; 1082 default: 1083 break; 1084 } 1085 1086 /* set a `lec` value so that we can check for updates later */ 1087 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1088 1089 netif_receive_skb(skb); 1090 stats->rx_packets++; 1091 stats->rx_bytes += cf->can_dlc; 1092 1093 return 1; 1094} 1095 1096static int c_can_poll(struct napi_struct *napi, int quota) 1097{ 1098 u16 irqstatus; 1099 int lec_type = 0; 1100 int work_done = 0; 1101 struct net_device *dev = napi->dev; 1102 struct c_can_priv *priv = netdev_priv(dev); 1103 1104 irqstatus = priv->irqstatus; 1105 if (!irqstatus) 1106 goto end; 1107 1108 /* status events have the highest priority */ 1109 if (irqstatus == STATUS_INTERRUPT) { 1110 priv->current_status = priv->read_reg(priv, 1111 C_CAN_STS_REG); 1112 1113 /* handle Tx/Rx events */ 1114 if (priv->current_status & STATUS_TXOK) 1115 priv->write_reg(priv, C_CAN_STS_REG, 1116 priv->current_status & ~STATUS_TXOK); 1117 1118 if (priv->current_status & STATUS_RXOK) 1119 priv->write_reg(priv, C_CAN_STS_REG, 1120 priv->current_status & ~STATUS_RXOK); 1121 1122 /* handle state changes */ 1123 if ((priv->current_status & STATUS_EWARN) && 1124 (!(priv->last_status & STATUS_EWARN))) { 1125 netdev_dbg(dev, "entered error warning state\n"); 1126 work_done += c_can_handle_state_change(dev, 1127 C_CAN_ERROR_WARNING); 1128 } 1129 if ((priv->current_status & STATUS_EPASS) && 1130 (!(priv->last_status & STATUS_EPASS))) { 1131 netdev_dbg(dev, "entered error passive state\n"); 1132 work_done += c_can_handle_state_change(dev, 1133 C_CAN_ERROR_PASSIVE); 1134 } 1135 if ((priv->current_status & STATUS_BOFF) && 1136 (!(priv->last_status & STATUS_BOFF))) { 1137 netdev_dbg(dev, "entered bus off state\n"); 1138 work_done += c_can_handle_state_change(dev, 1139 C_CAN_BUS_OFF); 1140 } 1141 1142 /* handle bus recovery events */ 1143 if ((!(priv->current_status & STATUS_BOFF)) && 1144 (priv->last_status & STATUS_BOFF)) { 1145 netdev_dbg(dev, "left bus off state\n"); 1146 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1147 } 1148 if ((!(priv->current_status & STATUS_EPASS)) && 1149 (priv->last_status & STATUS_EPASS)) { 1150 netdev_dbg(dev, "left error passive state\n"); 1151 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1152 } 1153 1154 priv->last_status = priv->current_status; 1155 1156 /* handle lec errors on the bus */ 1157 lec_type = c_can_has_and_handle_berr(priv); 1158 if (lec_type) 1159 work_done += c_can_handle_bus_err(dev, lec_type); 1160 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && 1161 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { 1162 /* handle events corresponding to receive message objects */ 1163 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1164 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && 1165 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { 1166 /* handle events corresponding to transmit message objects */ 1167 c_can_do_tx(dev); 1168 } 1169 1170end: 1171 if (work_done < quota) { 1172 napi_complete(napi); 1173 /* enable all IRQs */ 1174 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1175 } 1176 1177 return work_done; 1178} 1179 1180static irqreturn_t c_can_isr(int irq, void *dev_id) 1181{ 1182 struct net_device *dev = (struct net_device *)dev_id; 1183 struct c_can_priv *priv = netdev_priv(dev); 1184 1185 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); 1186 if (!priv->irqstatus) 1187 return IRQ_NONE; 1188 1189 /* disable all interrupts and schedule the NAPI */ 1190 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1191 napi_schedule(&priv->napi); 1192 1193 return IRQ_HANDLED; 1194} 1195 1196static int c_can_open(struct net_device *dev) 1197{ 1198 int err; 1199 struct c_can_priv *priv = netdev_priv(dev); 1200 1201 c_can_pm_runtime_get_sync(priv); 1202 c_can_reset_ram(priv, true); 1203 1204 /* open the can device */ 1205 err = open_candev(dev); 1206 if (err) { 1207 netdev_err(dev, "failed to open can device\n"); 1208 goto exit_open_fail; 1209 } 1210 1211 /* register interrupt handler */ 1212 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1213 dev); 1214 if (err < 0) { 1215 netdev_err(dev, "failed to request interrupt\n"); 1216 goto exit_irq_fail; 1217 } 1218 1219 /* start the c_can controller */ 1220 err = c_can_start(dev); 1221 if (err) 1222 goto exit_start_fail; 1223 1224 can_led_event(dev, CAN_LED_EVENT_OPEN); 1225 1226 napi_enable(&priv->napi); 1227 netif_start_queue(dev); 1228 1229 return 0; 1230 1231exit_start_fail: 1232 free_irq(dev->irq, dev); 1233exit_irq_fail: 1234 close_candev(dev); 1235exit_open_fail: 1236 c_can_reset_ram(priv, false); 1237 c_can_pm_runtime_put_sync(priv); 1238 return err; 1239} 1240 1241static int c_can_close(struct net_device *dev) 1242{ 1243 struct c_can_priv *priv = netdev_priv(dev); 1244 1245 netif_stop_queue(dev); 1246 napi_disable(&priv->napi); 1247 c_can_stop(dev); 1248 free_irq(dev->irq, dev); 1249 close_candev(dev); 1250 1251 c_can_reset_ram(priv, false); 1252 c_can_pm_runtime_put_sync(priv); 1253 1254 can_led_event(dev, CAN_LED_EVENT_STOP); 1255 1256 return 0; 1257} 1258 1259struct net_device *alloc_c_can_dev(void) 1260{ 1261 struct net_device *dev; 1262 struct c_can_priv *priv; 1263 1264 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1265 if (!dev) 1266 return NULL; 1267 1268 priv = netdev_priv(dev); 1269 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1270 1271 priv->dev = dev; 1272 priv->can.bittiming_const = &c_can_bittiming_const; 1273 priv->can.do_set_mode = c_can_set_mode; 1274 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1275 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1276 CAN_CTRLMODE_LISTENONLY | 1277 CAN_CTRLMODE_BERR_REPORTING; 1278 1279 return dev; 1280} 1281EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1282 1283#ifdef CONFIG_PM 1284int c_can_power_down(struct net_device *dev) 1285{ 1286 u32 val; 1287 unsigned long time_out; 1288 struct c_can_priv *priv = netdev_priv(dev); 1289 1290 if (!(dev->flags & IFF_UP)) 1291 return 0; 1292 1293 WARN_ON(priv->type != BOSCH_D_CAN); 1294 1295 /* set PDR value so the device goes to power down mode */ 1296 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1297 val |= CONTROL_EX_PDR; 1298 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1299 1300 /* Wait for the PDA bit to get set */ 1301 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1302 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1303 time_after(time_out, jiffies)) 1304 cpu_relax(); 1305 1306 if (time_after(jiffies, time_out)) 1307 return -ETIMEDOUT; 1308 1309 c_can_stop(dev); 1310 1311 c_can_reset_ram(priv, false); 1312 c_can_pm_runtime_put_sync(priv); 1313 1314 return 0; 1315} 1316EXPORT_SYMBOL_GPL(c_can_power_down); 1317 1318int c_can_power_up(struct net_device *dev) 1319{ 1320 u32 val; 1321 unsigned long time_out; 1322 struct c_can_priv *priv = netdev_priv(dev); 1323 1324 if (!(dev->flags & IFF_UP)) 1325 return 0; 1326 1327 WARN_ON(priv->type != BOSCH_D_CAN); 1328 1329 c_can_pm_runtime_get_sync(priv); 1330 c_can_reset_ram(priv, true); 1331 1332 /* Clear PDR and INIT bits */ 1333 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1334 val &= ~CONTROL_EX_PDR; 1335 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1336 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1337 val &= ~CONTROL_INIT; 1338 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1339 1340 /* Wait for the PDA bit to get clear */ 1341 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1342 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1343 time_after(time_out, jiffies)) 1344 cpu_relax(); 1345 1346 if (time_after(jiffies, time_out)) 1347 return -ETIMEDOUT; 1348 1349 return c_can_start(dev); 1350} 1351EXPORT_SYMBOL_GPL(c_can_power_up); 1352#endif 1353 1354void free_c_can_dev(struct net_device *dev) 1355{ 1356 struct c_can_priv *priv = netdev_priv(dev); 1357 1358 netif_napi_del(&priv->napi); 1359 free_candev(dev); 1360} 1361EXPORT_SYMBOL_GPL(free_c_can_dev); 1362 1363static const struct net_device_ops c_can_netdev_ops = { 1364 .ndo_open = c_can_open, 1365 .ndo_stop = c_can_close, 1366 .ndo_start_xmit = c_can_start_xmit, 1367}; 1368 1369int register_c_can_dev(struct net_device *dev) 1370{ 1371 struct c_can_priv *priv = netdev_priv(dev); 1372 int err; 1373 1374 c_can_pm_runtime_enable(priv); 1375 1376 dev->flags |= IFF_ECHO; /* we support local echo */ 1377 dev->netdev_ops = &c_can_netdev_ops; 1378 1379 err = register_candev(dev); 1380 if (err) 1381 c_can_pm_runtime_disable(priv); 1382 else 1383 devm_can_led_init(dev); 1384 1385 return err; 1386} 1387EXPORT_SYMBOL_GPL(register_c_can_dev); 1388 1389void unregister_c_can_dev(struct net_device *dev) 1390{ 1391 struct c_can_priv *priv = netdev_priv(dev); 1392 1393 unregister_candev(dev); 1394 1395 c_can_pm_runtime_disable(priv); 1396} 1397EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1398 1399MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1400MODULE_LICENSE("GPL v2"); 1401MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1402