c_can.c revision 6ea45886865c1abb01bb861f7f6bdd5d0f398cb3
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42 43#include "c_can.h" 44 45/* Number of interface registers */ 46#define IF_ENUM_REG_LEN 11 47#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 48 49/* control extension register D_CAN specific */ 50#define CONTROL_EX_PDR BIT(8) 51 52/* control register */ 53#define CONTROL_TEST BIT(7) 54#define CONTROL_CCE BIT(6) 55#define CONTROL_DISABLE_AR BIT(5) 56#define CONTROL_ENABLE_AR (0 << 5) 57#define CONTROL_EIE BIT(3) 58#define CONTROL_SIE BIT(2) 59#define CONTROL_IE BIT(1) 60#define CONTROL_INIT BIT(0) 61 62/* test register */ 63#define TEST_RX BIT(7) 64#define TEST_TX1 BIT(6) 65#define TEST_TX2 BIT(5) 66#define TEST_LBACK BIT(4) 67#define TEST_SILENT BIT(3) 68#define TEST_BASIC BIT(2) 69 70/* status register */ 71#define STATUS_PDA BIT(10) 72#define STATUS_BOFF BIT(7) 73#define STATUS_EWARN BIT(6) 74#define STATUS_EPASS BIT(5) 75#define STATUS_RXOK BIT(4) 76#define STATUS_TXOK BIT(3) 77 78/* error counter register */ 79#define ERR_CNT_TEC_MASK 0xff 80#define ERR_CNT_TEC_SHIFT 0 81#define ERR_CNT_REC_SHIFT 8 82#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 83#define ERR_CNT_RP_SHIFT 15 84#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 85 86/* bit-timing register */ 87#define BTR_BRP_MASK 0x3f 88#define BTR_BRP_SHIFT 0 89#define BTR_SJW_SHIFT 6 90#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 91#define BTR_TSEG1_SHIFT 8 92#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 93#define BTR_TSEG2_SHIFT 12 94#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 95 96/* brp extension register */ 97#define BRP_EXT_BRPE_MASK 0x0f 98#define BRP_EXT_BRPE_SHIFT 0 99 100/* IFx command request */ 101#define IF_COMR_BUSY BIT(15) 102 103/* IFx command mask */ 104#define IF_COMM_WR BIT(7) 105#define IF_COMM_MASK BIT(6) 106#define IF_COMM_ARB BIT(5) 107#define IF_COMM_CONTROL BIT(4) 108#define IF_COMM_CLR_INT_PND BIT(3) 109#define IF_COMM_TXRQST BIT(2) 110#define IF_COMM_DATAA BIT(1) 111#define IF_COMM_DATAB BIT(0) 112#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ 113 IF_COMM_CONTROL | IF_COMM_TXRQST | \ 114 IF_COMM_DATAA | IF_COMM_DATAB) 115 116/* IFx arbitration */ 117#define IF_ARB_MSGVAL BIT(15) 118#define IF_ARB_MSGXTD BIT(14) 119#define IF_ARB_TRANSMIT BIT(13) 120 121/* IFx message control */ 122#define IF_MCONT_NEWDAT BIT(15) 123#define IF_MCONT_MSGLST BIT(14) 124#define IF_MCONT_CLR_MSGLST (0 << 14) 125#define IF_MCONT_INTPND BIT(13) 126#define IF_MCONT_UMASK BIT(12) 127#define IF_MCONT_TXIE BIT(11) 128#define IF_MCONT_RXIE BIT(10) 129#define IF_MCONT_RMTEN BIT(9) 130#define IF_MCONT_TXRQST BIT(8) 131#define IF_MCONT_EOB BIT(7) 132#define IF_MCONT_DLC_MASK 0xf 133 134/* 135 * IFx register masks: 136 * allow easy operation on 16-bit registers when the 137 * argument is 32-bit instead 138 */ 139#define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF) 140#define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16) 141 142/* message object split */ 143#define C_CAN_NO_OF_OBJECTS 32 144#define C_CAN_MSG_OBJ_RX_NUM 16 145#define C_CAN_MSG_OBJ_TX_NUM 16 146 147#define C_CAN_MSG_OBJ_RX_FIRST 1 148#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \ 149 C_CAN_MSG_OBJ_RX_NUM - 1) 150 151#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1) 152#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \ 153 C_CAN_MSG_OBJ_TX_NUM - 1) 154 155#define C_CAN_MSG_OBJ_RX_SPLIT 9 156#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1) 157 158#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1) 159#define RECEIVE_OBJECT_BITS 0x0000ffff 160 161/* status interrupt */ 162#define STATUS_INTERRUPT 0x8000 163 164/* global interrupt masks */ 165#define ENABLE_ALL_INTERRUPTS 1 166#define DISABLE_ALL_INTERRUPTS 0 167 168/* minimum timeout for checking BUSY status */ 169#define MIN_TIMEOUT_VALUE 6 170 171/* Wait for ~1 sec for INIT bit */ 172#define INIT_WAIT_MS 1000 173 174/* napi related */ 175#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 176 177/* c_can lec values */ 178enum c_can_lec_type { 179 LEC_NO_ERROR = 0, 180 LEC_STUFF_ERROR, 181 LEC_FORM_ERROR, 182 LEC_ACK_ERROR, 183 LEC_BIT1_ERROR, 184 LEC_BIT0_ERROR, 185 LEC_CRC_ERROR, 186 LEC_UNUSED, 187}; 188 189/* 190 * c_can error types: 191 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 192 */ 193enum c_can_bus_error_types { 194 C_CAN_NO_ERROR = 0, 195 C_CAN_BUS_OFF, 196 C_CAN_ERROR_WARNING, 197 C_CAN_ERROR_PASSIVE, 198}; 199 200static const struct can_bittiming_const c_can_bittiming_const = { 201 .name = KBUILD_MODNAME, 202 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 203 .tseg1_max = 16, 204 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 205 .tseg2_max = 8, 206 .sjw_max = 4, 207 .brp_min = 1, 208 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 209 .brp_inc = 1, 210}; 211 212static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 213{ 214 if (priv->device) 215 pm_runtime_enable(priv->device); 216} 217 218static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 219{ 220 if (priv->device) 221 pm_runtime_disable(priv->device); 222} 223 224static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 225{ 226 if (priv->device) 227 pm_runtime_get_sync(priv->device); 228} 229 230static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 231{ 232 if (priv->device) 233 pm_runtime_put_sync(priv->device); 234} 235 236static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 237{ 238 if (priv->raminit) 239 priv->raminit(priv, enable); 240} 241 242static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 243{ 244 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + 245 C_CAN_MSG_OBJ_TX_FIRST; 246} 247 248static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv) 249{ 250 return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) + 251 C_CAN_MSG_OBJ_TX_FIRST; 252} 253 254static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) 255{ 256 u32 val = priv->read_reg(priv, index); 257 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 258 return val; 259} 260 261static void c_can_enable_all_interrupts(struct c_can_priv *priv, 262 int enable) 263{ 264 unsigned int cntrl_save = priv->read_reg(priv, 265 C_CAN_CTRL_REG); 266 267 if (enable) 268 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 269 else 270 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); 271 272 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); 273} 274 275static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 276{ 277 int count = MIN_TIMEOUT_VALUE; 278 279 while (count && priv->read_reg(priv, 280 C_CAN_IFACE(COMREQ_REG, iface)) & 281 IF_COMR_BUSY) { 282 count--; 283 udelay(1); 284 } 285 286 if (!count) 287 return 1; 288 289 return 0; 290} 291 292static inline void c_can_object_get(struct net_device *dev, 293 int iface, int objno, int mask) 294{ 295 struct c_can_priv *priv = netdev_priv(dev); 296 297 /* 298 * As per specs, after writting the message object number in the 299 * IF command request register the transfer b/w interface 300 * register and message RAM must be complete in 6 CAN-CLK 301 * period. 302 */ 303 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 304 IFX_WRITE_LOW_16BIT(mask)); 305 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 306 IFX_WRITE_LOW_16BIT(objno)); 307 308 if (c_can_msg_obj_is_busy(priv, iface)) 309 netdev_err(dev, "timed out in object get\n"); 310} 311 312static inline void c_can_object_put(struct net_device *dev, 313 int iface, int objno, int mask) 314{ 315 struct c_can_priv *priv = netdev_priv(dev); 316 317 /* 318 * As per specs, after writting the message object number in the 319 * IF command request register the transfer b/w interface 320 * register and message RAM must be complete in 6 CAN-CLK 321 * period. 322 */ 323 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 324 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); 325 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 326 IFX_WRITE_LOW_16BIT(objno)); 327 328 if (c_can_msg_obj_is_busy(priv, iface)) 329 netdev_err(dev, "timed out in object put\n"); 330} 331 332static void c_can_write_msg_object(struct net_device *dev, 333 int iface, struct can_frame *frame, int objno) 334{ 335 int i; 336 u16 flags = 0; 337 unsigned int id; 338 struct c_can_priv *priv = netdev_priv(dev); 339 340 if (!(frame->can_id & CAN_RTR_FLAG)) 341 flags |= IF_ARB_TRANSMIT; 342 343 if (frame->can_id & CAN_EFF_FLAG) { 344 id = frame->can_id & CAN_EFF_MASK; 345 flags |= IF_ARB_MSGXTD; 346 } else 347 id = ((frame->can_id & CAN_SFF_MASK) << 18); 348 349 flags |= IF_ARB_MSGVAL; 350 351 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 352 IFX_WRITE_LOW_16BIT(id)); 353 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | 354 IFX_WRITE_HIGH_16BIT(id)); 355 356 for (i = 0; i < frame->can_dlc; i += 2) { 357 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 358 frame->data[i] | (frame->data[i + 1] << 8)); 359 } 360 361 /* enable interrupt for this message object */ 362 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 363 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | 364 frame->can_dlc); 365 c_can_object_put(dev, iface, objno, IF_COMM_ALL); 366} 367 368static inline void c_can_mark_rx_msg_obj(struct net_device *dev, 369 int iface, int ctrl_mask, 370 int obj) 371{ 372 struct c_can_priv *priv = netdev_priv(dev); 373 374 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 375 ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND)); 376 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); 377 378} 379 380static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 381 int iface, 382 int ctrl_mask) 383{ 384 int i; 385 struct c_can_priv *priv = netdev_priv(dev); 386 387 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { 388 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 389 ctrl_mask & ~(IF_MCONT_MSGLST | 390 IF_MCONT_INTPND | IF_MCONT_NEWDAT)); 391 c_can_object_put(dev, iface, i, IF_COMM_CONTROL); 392 } 393} 394 395static inline void c_can_activate_rx_msg_obj(struct net_device *dev, 396 int iface, int ctrl_mask, 397 int obj) 398{ 399 struct c_can_priv *priv = netdev_priv(dev); 400 401 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 402 ctrl_mask & ~(IF_MCONT_MSGLST | 403 IF_MCONT_INTPND | IF_MCONT_NEWDAT)); 404 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); 405} 406 407static void c_can_handle_lost_msg_obj(struct net_device *dev, 408 int iface, int objno) 409{ 410 struct c_can_priv *priv = netdev_priv(dev); 411 struct net_device_stats *stats = &dev->stats; 412 struct sk_buff *skb; 413 struct can_frame *frame; 414 415 netdev_err(dev, "msg lost in buffer %d\n", objno); 416 417 c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 418 419 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 420 IF_MCONT_CLR_MSGLST); 421 422 c_can_object_put(dev, 0, objno, IF_COMM_CONTROL); 423 424 /* create an error msg */ 425 skb = alloc_can_err_skb(dev, &frame); 426 if (unlikely(!skb)) 427 return; 428 429 frame->can_id |= CAN_ERR_CRTL; 430 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 431 stats->rx_errors++; 432 stats->rx_over_errors++; 433 434 netif_receive_skb(skb); 435} 436 437static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) 438{ 439 u16 flags, data; 440 int i; 441 unsigned int val; 442 struct c_can_priv *priv = netdev_priv(dev); 443 struct net_device_stats *stats = &dev->stats; 444 struct sk_buff *skb; 445 struct can_frame *frame; 446 447 skb = alloc_can_skb(dev, &frame); 448 if (!skb) { 449 stats->rx_dropped++; 450 return -ENOMEM; 451 } 452 453 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 454 455 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); 456 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | 457 (flags << 16); 458 459 if (flags & IF_ARB_MSGXTD) 460 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; 461 else 462 frame->can_id = (val >> 18) & CAN_SFF_MASK; 463 464 if (flags & IF_ARB_TRANSMIT) 465 frame->can_id |= CAN_RTR_FLAG; 466 else { 467 for (i = 0; i < frame->can_dlc; i += 2) { 468 data = priv->read_reg(priv, 469 C_CAN_IFACE(DATA1_REG, iface) + i / 2); 470 frame->data[i] = data; 471 frame->data[i + 1] = data >> 8; 472 } 473 } 474 475 netif_receive_skb(skb); 476 477 stats->rx_packets++; 478 stats->rx_bytes += frame->can_dlc; 479 480 return 0; 481} 482 483static void c_can_setup_receive_object(struct net_device *dev, int iface, 484 int objno, unsigned int mask, 485 unsigned int id, unsigned int mcont) 486{ 487 struct c_can_priv *priv = netdev_priv(dev); 488 489 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), 490 IFX_WRITE_LOW_16BIT(mask)); 491 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), 492 IFX_WRITE_HIGH_16BIT(mask)); 493 494 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 495 IFX_WRITE_LOW_16BIT(id)); 496 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 497 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); 498 499 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 500 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 501 502 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 503 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 504} 505 506static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) 507{ 508 struct c_can_priv *priv = netdev_priv(dev); 509 510 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 511 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 512 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 513 514 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); 515 516 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 517 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 518} 519 520static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 521{ 522 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 523 524 /* 525 * as transmission request register's bit n-1 corresponds to 526 * message object n, we need to handle the same properly. 527 */ 528 if (val & (1 << (objno - 1))) 529 return 1; 530 531 return 0; 532} 533 534static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 535 struct net_device *dev) 536{ 537 u32 msg_obj_no; 538 struct c_can_priv *priv = netdev_priv(dev); 539 struct can_frame *frame = (struct can_frame *)skb->data; 540 541 if (can_dropped_invalid_skb(dev, skb)) 542 return NETDEV_TX_OK; 543 544 msg_obj_no = get_tx_next_msg_obj(priv); 545 546 /* prepare message object for transmission */ 547 c_can_write_msg_object(dev, 0, frame, msg_obj_no); 548 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 549 550 /* 551 * we have to stop the queue in case of a wrap around or 552 * if the next TX message object is still in use 553 */ 554 priv->tx_next++; 555 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 556 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 557 netif_stop_queue(dev); 558 559 return NETDEV_TX_OK; 560} 561 562static int c_can_set_bittiming(struct net_device *dev) 563{ 564 unsigned int reg_btr, reg_brpe, ctrl_save; 565 u8 brp, brpe, sjw, tseg1, tseg2; 566 u32 ten_bit_brp; 567 struct c_can_priv *priv = netdev_priv(dev); 568 const struct can_bittiming *bt = &priv->can.bittiming; 569 570 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 571 ten_bit_brp = bt->brp - 1; 572 brp = ten_bit_brp & BTR_BRP_MASK; 573 brpe = ten_bit_brp >> 6; 574 575 sjw = bt->sjw - 1; 576 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 577 tseg2 = bt->phase_seg2 - 1; 578 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 579 (tseg2 << BTR_TSEG2_SHIFT); 580 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 581 582 netdev_info(dev, 583 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 584 585 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 586 priv->write_reg(priv, C_CAN_CTRL_REG, 587 ctrl_save | CONTROL_CCE | CONTROL_INIT); 588 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 589 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 590 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 591 592 return 0; 593} 594 595/* 596 * Configure C_CAN message objects for Tx and Rx purposes: 597 * C_CAN provides a total of 32 message objects that can be configured 598 * either for Tx or Rx purposes. Here the first 16 message objects are used as 599 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 600 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 601 * See user guide document for further details on configuring message 602 * objects. 603 */ 604static void c_can_configure_msg_objects(struct net_device *dev) 605{ 606 int i; 607 608 /* first invalidate all message objects */ 609 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 610 c_can_inval_msg_object(dev, 0, i); 611 612 /* setup receive message objects */ 613 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 614 c_can_setup_receive_object(dev, 0, i, 0, 0, 615 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); 616 617 c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 618 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); 619} 620 621/* 622 * Configure C_CAN chip: 623 * - enable/disable auto-retransmission 624 * - set operating mode 625 * - configure message objects 626 */ 627static void c_can_chip_config(struct net_device *dev) 628{ 629 struct c_can_priv *priv = netdev_priv(dev); 630 631 /* enable automatic retransmission */ 632 priv->write_reg(priv, C_CAN_CTRL_REG, 633 CONTROL_ENABLE_AR); 634 635 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 636 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 637 /* loopback + silent mode : useful for hot self-test */ 638 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 639 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 640 priv->write_reg(priv, C_CAN_TEST_REG, 641 TEST_LBACK | TEST_SILENT); 642 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 643 /* loopback mode : useful for self-test function */ 644 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 645 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 646 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 647 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 648 /* silent mode : bus-monitoring mode */ 649 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 650 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 651 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 652 } else 653 /* normal mode*/ 654 priv->write_reg(priv, C_CAN_CTRL_REG, 655 CONTROL_EIE | CONTROL_SIE | CONTROL_IE); 656 657 /* configure message objects */ 658 c_can_configure_msg_objects(dev); 659 660 /* set a `lec` value so that we can check for updates later */ 661 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 662 663 /* set bittiming params */ 664 c_can_set_bittiming(dev); 665} 666 667static void c_can_start(struct net_device *dev) 668{ 669 struct c_can_priv *priv = netdev_priv(dev); 670 671 /* basic c_can configuration */ 672 c_can_chip_config(dev); 673 674 priv->can.state = CAN_STATE_ERROR_ACTIVE; 675 676 /* reset tx helper pointers */ 677 priv->tx_next = priv->tx_echo = 0; 678 679 /* enable status change, error and module interrupts */ 680 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 681} 682 683static void c_can_stop(struct net_device *dev) 684{ 685 struct c_can_priv *priv = netdev_priv(dev); 686 687 /* disable all interrupts */ 688 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 689 690 /* set the state as STOPPED */ 691 priv->can.state = CAN_STATE_STOPPED; 692} 693 694static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 695{ 696 switch (mode) { 697 case CAN_MODE_START: 698 c_can_start(dev); 699 netif_wake_queue(dev); 700 break; 701 default: 702 return -EOPNOTSUPP; 703 } 704 705 return 0; 706} 707 708static int c_can_get_berr_counter(const struct net_device *dev, 709 struct can_berr_counter *bec) 710{ 711 unsigned int reg_err_counter; 712 struct c_can_priv *priv = netdev_priv(dev); 713 714 c_can_pm_runtime_get_sync(priv); 715 716 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 717 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 718 ERR_CNT_REC_SHIFT; 719 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 720 721 c_can_pm_runtime_put_sync(priv); 722 723 return 0; 724} 725 726/* 727 * theory of operation: 728 * 729 * priv->tx_echo holds the number of the oldest can_frame put for 730 * transmission into the hardware, but not yet ACKed by the CAN tx 731 * complete IRQ. 732 * 733 * We iterate from priv->tx_echo to priv->tx_next and check if the 734 * packet has been transmitted, echo it back to the CAN framework. 735 * If we discover a not yet transmitted packet, stop looking for more. 736 */ 737static void c_can_do_tx(struct net_device *dev) 738{ 739 u32 val; 740 u32 msg_obj_no; 741 struct c_can_priv *priv = netdev_priv(dev); 742 struct net_device_stats *stats = &dev->stats; 743 744 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 745 msg_obj_no = get_tx_echo_msg_obj(priv); 746 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 747 if (!(val & (1 << (msg_obj_no - 1)))) { 748 can_get_echo_skb(dev, 749 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 750 stats->tx_bytes += priv->read_reg(priv, 751 C_CAN_IFACE(MSGCTRL_REG, 0)) 752 & IF_MCONT_DLC_MASK; 753 stats->tx_packets++; 754 c_can_inval_msg_object(dev, 0, msg_obj_no); 755 } else { 756 break; 757 } 758 } 759 760 /* restart queue if wrap-up or if queue stalled on last pkt */ 761 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 762 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) 763 netif_wake_queue(dev); 764} 765 766/* 767 * theory of operation: 768 * 769 * c_can core saves a received CAN message into the first free message 770 * object it finds free (starting with the lowest). Bits NEWDAT and 771 * INTPND are set for this message object indicating that a new message 772 * has arrived. To work-around this issue, we keep two groups of message 773 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 774 * 775 * To ensure in-order frame reception we use the following 776 * approach while re-activating a message object to receive further 777 * frames: 778 * - if the current message object number is lower than 779 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 780 * the INTPND bit. 781 * - if the current message object number is equal to 782 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 783 * receive message objects. 784 * - if the current message object number is greater than 785 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 786 * only this message object. 787 */ 788static int c_can_do_rx_poll(struct net_device *dev, int quota) 789{ 790 u32 num_rx_pkts = 0; 791 unsigned int msg_obj, msg_ctrl_save; 792 struct c_can_priv *priv = netdev_priv(dev); 793 u32 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG); 794 795 for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST; 796 msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0; 797 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG), 798 msg_obj++) { 799 /* 800 * as interrupt pending register's bit n-1 corresponds to 801 * message object n, we need to handle the same properly. 802 */ 803 if (val & (1 << (msg_obj - 1))) { 804 c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL & 805 ~IF_COMM_TXRQST); 806 msg_ctrl_save = priv->read_reg(priv, 807 C_CAN_IFACE(MSGCTRL_REG, 0)); 808 809 if (msg_ctrl_save & IF_MCONT_EOB) 810 return num_rx_pkts; 811 812 if (msg_ctrl_save & IF_MCONT_MSGLST) { 813 c_can_handle_lost_msg_obj(dev, 0, msg_obj); 814 num_rx_pkts++; 815 quota--; 816 continue; 817 } 818 819 if (!(msg_ctrl_save & IF_MCONT_NEWDAT)) 820 continue; 821 822 /* read the data from the message object */ 823 c_can_read_msg_object(dev, 0, msg_ctrl_save); 824 825 if (msg_obj < C_CAN_MSG_RX_LOW_LAST) 826 c_can_mark_rx_msg_obj(dev, 0, 827 msg_ctrl_save, msg_obj); 828 else if (msg_obj > C_CAN_MSG_RX_LOW_LAST) 829 /* activate this msg obj */ 830 c_can_activate_rx_msg_obj(dev, 0, 831 msg_ctrl_save, msg_obj); 832 else if (msg_obj == C_CAN_MSG_RX_LOW_LAST) 833 /* activate all lower message objects */ 834 c_can_activate_all_lower_rx_msg_obj(dev, 835 0, msg_ctrl_save); 836 837 num_rx_pkts++; 838 quota--; 839 } 840 } 841 842 return num_rx_pkts; 843} 844 845static inline int c_can_has_and_handle_berr(struct c_can_priv *priv) 846{ 847 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 848 (priv->current_status & LEC_UNUSED); 849} 850 851static int c_can_handle_state_change(struct net_device *dev, 852 enum c_can_bus_error_types error_type) 853{ 854 unsigned int reg_err_counter; 855 unsigned int rx_err_passive; 856 struct c_can_priv *priv = netdev_priv(dev); 857 struct net_device_stats *stats = &dev->stats; 858 struct can_frame *cf; 859 struct sk_buff *skb; 860 struct can_berr_counter bec; 861 862 /* propagate the error condition to the CAN stack */ 863 skb = alloc_can_err_skb(dev, &cf); 864 if (unlikely(!skb)) 865 return 0; 866 867 c_can_get_berr_counter(dev, &bec); 868 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 869 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 870 ERR_CNT_RP_SHIFT; 871 872 switch (error_type) { 873 case C_CAN_ERROR_WARNING: 874 /* error warning state */ 875 priv->can.can_stats.error_warning++; 876 priv->can.state = CAN_STATE_ERROR_WARNING; 877 cf->can_id |= CAN_ERR_CRTL; 878 cf->data[1] = (bec.txerr > bec.rxerr) ? 879 CAN_ERR_CRTL_TX_WARNING : 880 CAN_ERR_CRTL_RX_WARNING; 881 cf->data[6] = bec.txerr; 882 cf->data[7] = bec.rxerr; 883 884 break; 885 case C_CAN_ERROR_PASSIVE: 886 /* error passive state */ 887 priv->can.can_stats.error_passive++; 888 priv->can.state = CAN_STATE_ERROR_PASSIVE; 889 cf->can_id |= CAN_ERR_CRTL; 890 if (rx_err_passive) 891 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 892 if (bec.txerr > 127) 893 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 894 895 cf->data[6] = bec.txerr; 896 cf->data[7] = bec.rxerr; 897 break; 898 case C_CAN_BUS_OFF: 899 /* bus-off state */ 900 priv->can.state = CAN_STATE_BUS_OFF; 901 cf->can_id |= CAN_ERR_BUSOFF; 902 /* 903 * disable all interrupts in bus-off mode to ensure that 904 * the CPU is not hogged down 905 */ 906 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 907 can_bus_off(dev); 908 break; 909 default: 910 break; 911 } 912 913 netif_receive_skb(skb); 914 stats->rx_packets++; 915 stats->rx_bytes += cf->can_dlc; 916 917 return 1; 918} 919 920static int c_can_handle_bus_err(struct net_device *dev, 921 enum c_can_lec_type lec_type) 922{ 923 struct c_can_priv *priv = netdev_priv(dev); 924 struct net_device_stats *stats = &dev->stats; 925 struct can_frame *cf; 926 struct sk_buff *skb; 927 928 /* 929 * early exit if no lec update or no error. 930 * no lec update means that no CAN bus event has been detected 931 * since CPU wrote 0x7 value to status reg. 932 */ 933 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 934 return 0; 935 936 /* propagate the error condition to the CAN stack */ 937 skb = alloc_can_err_skb(dev, &cf); 938 if (unlikely(!skb)) 939 return 0; 940 941 /* 942 * check for 'last error code' which tells us the 943 * type of the last error to occur on the CAN bus 944 */ 945 946 /* common for all type of bus errors */ 947 priv->can.can_stats.bus_error++; 948 stats->rx_errors++; 949 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 950 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 951 952 switch (lec_type) { 953 case LEC_STUFF_ERROR: 954 netdev_dbg(dev, "stuff error\n"); 955 cf->data[2] |= CAN_ERR_PROT_STUFF; 956 break; 957 case LEC_FORM_ERROR: 958 netdev_dbg(dev, "form error\n"); 959 cf->data[2] |= CAN_ERR_PROT_FORM; 960 break; 961 case LEC_ACK_ERROR: 962 netdev_dbg(dev, "ack error\n"); 963 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 964 CAN_ERR_PROT_LOC_ACK_DEL); 965 break; 966 case LEC_BIT1_ERROR: 967 netdev_dbg(dev, "bit1 error\n"); 968 cf->data[2] |= CAN_ERR_PROT_BIT1; 969 break; 970 case LEC_BIT0_ERROR: 971 netdev_dbg(dev, "bit0 error\n"); 972 cf->data[2] |= CAN_ERR_PROT_BIT0; 973 break; 974 case LEC_CRC_ERROR: 975 netdev_dbg(dev, "CRC error\n"); 976 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 977 CAN_ERR_PROT_LOC_CRC_DEL); 978 break; 979 default: 980 break; 981 } 982 983 /* set a `lec` value so that we can check for updates later */ 984 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 985 986 netif_receive_skb(skb); 987 stats->rx_packets++; 988 stats->rx_bytes += cf->can_dlc; 989 990 return 1; 991} 992 993static int c_can_poll(struct napi_struct *napi, int quota) 994{ 995 u16 irqstatus; 996 int lec_type = 0; 997 int work_done = 0; 998 struct net_device *dev = napi->dev; 999 struct c_can_priv *priv = netdev_priv(dev); 1000 1001 irqstatus = priv->irqstatus; 1002 if (!irqstatus) 1003 goto end; 1004 1005 /* status events have the highest priority */ 1006 if (irqstatus == STATUS_INTERRUPT) { 1007 priv->current_status = priv->read_reg(priv, 1008 C_CAN_STS_REG); 1009 1010 /* handle Tx/Rx events */ 1011 if (priv->current_status & STATUS_TXOK) 1012 priv->write_reg(priv, C_CAN_STS_REG, 1013 priv->current_status & ~STATUS_TXOK); 1014 1015 if (priv->current_status & STATUS_RXOK) 1016 priv->write_reg(priv, C_CAN_STS_REG, 1017 priv->current_status & ~STATUS_RXOK); 1018 1019 /* handle state changes */ 1020 if ((priv->current_status & STATUS_EWARN) && 1021 (!(priv->last_status & STATUS_EWARN))) { 1022 netdev_dbg(dev, "entered error warning state\n"); 1023 work_done += c_can_handle_state_change(dev, 1024 C_CAN_ERROR_WARNING); 1025 } 1026 if ((priv->current_status & STATUS_EPASS) && 1027 (!(priv->last_status & STATUS_EPASS))) { 1028 netdev_dbg(dev, "entered error passive state\n"); 1029 work_done += c_can_handle_state_change(dev, 1030 C_CAN_ERROR_PASSIVE); 1031 } 1032 if ((priv->current_status & STATUS_BOFF) && 1033 (!(priv->last_status & STATUS_BOFF))) { 1034 netdev_dbg(dev, "entered bus off state\n"); 1035 work_done += c_can_handle_state_change(dev, 1036 C_CAN_BUS_OFF); 1037 } 1038 1039 /* handle bus recovery events */ 1040 if ((!(priv->current_status & STATUS_BOFF)) && 1041 (priv->last_status & STATUS_BOFF)) { 1042 netdev_dbg(dev, "left bus off state\n"); 1043 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1044 } 1045 if ((!(priv->current_status & STATUS_EPASS)) && 1046 (priv->last_status & STATUS_EPASS)) { 1047 netdev_dbg(dev, "left error passive state\n"); 1048 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1049 } 1050 1051 priv->last_status = priv->current_status; 1052 1053 /* handle lec errors on the bus */ 1054 lec_type = c_can_has_and_handle_berr(priv); 1055 if (lec_type) 1056 work_done += c_can_handle_bus_err(dev, lec_type); 1057 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && 1058 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { 1059 /* handle events corresponding to receive message objects */ 1060 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1061 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && 1062 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { 1063 /* handle events corresponding to transmit message objects */ 1064 c_can_do_tx(dev); 1065 } 1066 1067end: 1068 if (work_done < quota) { 1069 napi_complete(napi); 1070 /* enable all IRQs */ 1071 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1072 } 1073 1074 return work_done; 1075} 1076 1077static irqreturn_t c_can_isr(int irq, void *dev_id) 1078{ 1079 struct net_device *dev = (struct net_device *)dev_id; 1080 struct c_can_priv *priv = netdev_priv(dev); 1081 1082 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); 1083 if (!priv->irqstatus) 1084 return IRQ_NONE; 1085 1086 /* disable all interrupts and schedule the NAPI */ 1087 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1088 napi_schedule(&priv->napi); 1089 1090 return IRQ_HANDLED; 1091} 1092 1093static int c_can_open(struct net_device *dev) 1094{ 1095 int err; 1096 struct c_can_priv *priv = netdev_priv(dev); 1097 1098 c_can_pm_runtime_get_sync(priv); 1099 c_can_reset_ram(priv, true); 1100 1101 /* open the can device */ 1102 err = open_candev(dev); 1103 if (err) { 1104 netdev_err(dev, "failed to open can device\n"); 1105 goto exit_open_fail; 1106 } 1107 1108 /* register interrupt handler */ 1109 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1110 dev); 1111 if (err < 0) { 1112 netdev_err(dev, "failed to request interrupt\n"); 1113 goto exit_irq_fail; 1114 } 1115 1116 napi_enable(&priv->napi); 1117 1118 /* start the c_can controller */ 1119 c_can_start(dev); 1120 1121 netif_start_queue(dev); 1122 1123 return 0; 1124 1125exit_irq_fail: 1126 close_candev(dev); 1127exit_open_fail: 1128 c_can_reset_ram(priv, false); 1129 c_can_pm_runtime_put_sync(priv); 1130 return err; 1131} 1132 1133static int c_can_close(struct net_device *dev) 1134{ 1135 struct c_can_priv *priv = netdev_priv(dev); 1136 1137 netif_stop_queue(dev); 1138 napi_disable(&priv->napi); 1139 c_can_stop(dev); 1140 free_irq(dev->irq, dev); 1141 close_candev(dev); 1142 1143 c_can_reset_ram(priv, false); 1144 c_can_pm_runtime_put_sync(priv); 1145 1146 return 0; 1147} 1148 1149struct net_device *alloc_c_can_dev(void) 1150{ 1151 struct net_device *dev; 1152 struct c_can_priv *priv; 1153 1154 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1155 if (!dev) 1156 return NULL; 1157 1158 priv = netdev_priv(dev); 1159 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1160 1161 priv->dev = dev; 1162 priv->can.bittiming_const = &c_can_bittiming_const; 1163 priv->can.do_set_mode = c_can_set_mode; 1164 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1165 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1166 CAN_CTRLMODE_LISTENONLY | 1167 CAN_CTRLMODE_BERR_REPORTING; 1168 1169 return dev; 1170} 1171EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1172 1173#ifdef CONFIG_PM 1174int c_can_power_down(struct net_device *dev) 1175{ 1176 u32 val; 1177 unsigned long time_out; 1178 struct c_can_priv *priv = netdev_priv(dev); 1179 1180 if (!(dev->flags & IFF_UP)) 1181 return 0; 1182 1183 WARN_ON(priv->type != BOSCH_D_CAN); 1184 1185 /* set PDR value so the device goes to power down mode */ 1186 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1187 val |= CONTROL_EX_PDR; 1188 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1189 1190 /* Wait for the PDA bit to get set */ 1191 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1192 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1193 time_after(time_out, jiffies)) 1194 cpu_relax(); 1195 1196 if (time_after(jiffies, time_out)) 1197 return -ETIMEDOUT; 1198 1199 c_can_stop(dev); 1200 1201 c_can_reset_ram(priv, false); 1202 c_can_pm_runtime_put_sync(priv); 1203 1204 return 0; 1205} 1206EXPORT_SYMBOL_GPL(c_can_power_down); 1207 1208int c_can_power_up(struct net_device *dev) 1209{ 1210 u32 val; 1211 unsigned long time_out; 1212 struct c_can_priv *priv = netdev_priv(dev); 1213 1214 if (!(dev->flags & IFF_UP)) 1215 return 0; 1216 1217 WARN_ON(priv->type != BOSCH_D_CAN); 1218 1219 c_can_pm_runtime_get_sync(priv); 1220 c_can_reset_ram(priv, true); 1221 1222 /* Clear PDR and INIT bits */ 1223 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1224 val &= ~CONTROL_EX_PDR; 1225 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1226 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1227 val &= ~CONTROL_INIT; 1228 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1229 1230 /* Wait for the PDA bit to get clear */ 1231 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1232 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1233 time_after(time_out, jiffies)) 1234 cpu_relax(); 1235 1236 if (time_after(jiffies, time_out)) 1237 return -ETIMEDOUT; 1238 1239 c_can_start(dev); 1240 1241 return 0; 1242} 1243EXPORT_SYMBOL_GPL(c_can_power_up); 1244#endif 1245 1246void free_c_can_dev(struct net_device *dev) 1247{ 1248 free_candev(dev); 1249} 1250EXPORT_SYMBOL_GPL(free_c_can_dev); 1251 1252static const struct net_device_ops c_can_netdev_ops = { 1253 .ndo_open = c_can_open, 1254 .ndo_stop = c_can_close, 1255 .ndo_start_xmit = c_can_start_xmit, 1256}; 1257 1258int register_c_can_dev(struct net_device *dev) 1259{ 1260 struct c_can_priv *priv = netdev_priv(dev); 1261 int err; 1262 1263 c_can_pm_runtime_enable(priv); 1264 1265 dev->flags |= IFF_ECHO; /* we support local echo */ 1266 dev->netdev_ops = &c_can_netdev_ops; 1267 1268 err = register_candev(dev); 1269 if (err) 1270 c_can_pm_runtime_disable(priv); 1271 1272 return err; 1273} 1274EXPORT_SYMBOL_GPL(register_c_can_dev); 1275 1276void unregister_c_can_dev(struct net_device *dev) 1277{ 1278 struct c_can_priv *priv = netdev_priv(dev); 1279 1280 unregister_candev(dev); 1281 1282 c_can_pm_runtime_disable(priv); 1283} 1284EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1285 1286MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1287MODULE_LICENSE("GPL v2"); 1288MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1289