c_can.c revision 902470085406934d3f20c4af02de7d79c01b6b93
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42#include <linux/can/led.h> 43 44#include "c_can.h" 45 46/* Number of interface registers */ 47#define IF_ENUM_REG_LEN 11 48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 49 50/* control extension register D_CAN specific */ 51#define CONTROL_EX_PDR BIT(8) 52 53/* control register */ 54#define CONTROL_TEST BIT(7) 55#define CONTROL_CCE BIT(6) 56#define CONTROL_DISABLE_AR BIT(5) 57#define CONTROL_ENABLE_AR (0 << 5) 58#define CONTROL_EIE BIT(3) 59#define CONTROL_SIE BIT(2) 60#define CONTROL_IE BIT(1) 61#define CONTROL_INIT BIT(0) 62 63/* test register */ 64#define TEST_RX BIT(7) 65#define TEST_TX1 BIT(6) 66#define TEST_TX2 BIT(5) 67#define TEST_LBACK BIT(4) 68#define TEST_SILENT BIT(3) 69#define TEST_BASIC BIT(2) 70 71/* status register */ 72#define STATUS_PDA BIT(10) 73#define STATUS_BOFF BIT(7) 74#define STATUS_EWARN BIT(6) 75#define STATUS_EPASS BIT(5) 76#define STATUS_RXOK BIT(4) 77#define STATUS_TXOK BIT(3) 78 79/* error counter register */ 80#define ERR_CNT_TEC_MASK 0xff 81#define ERR_CNT_TEC_SHIFT 0 82#define ERR_CNT_REC_SHIFT 8 83#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 84#define ERR_CNT_RP_SHIFT 15 85#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 86 87/* bit-timing register */ 88#define BTR_BRP_MASK 0x3f 89#define BTR_BRP_SHIFT 0 90#define BTR_SJW_SHIFT 6 91#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 92#define BTR_TSEG1_SHIFT 8 93#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 94#define BTR_TSEG2_SHIFT 12 95#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 96 97/* brp extension register */ 98#define BRP_EXT_BRPE_MASK 0x0f 99#define BRP_EXT_BRPE_SHIFT 0 100 101/* IFx command request */ 102#define IF_COMR_BUSY BIT(15) 103 104/* IFx command mask */ 105#define IF_COMM_WR BIT(7) 106#define IF_COMM_MASK BIT(6) 107#define IF_COMM_ARB BIT(5) 108#define IF_COMM_CONTROL BIT(4) 109#define IF_COMM_CLR_INT_PND BIT(3) 110#define IF_COMM_TXRQST BIT(2) 111#define IF_COMM_DATAA BIT(1) 112#define IF_COMM_DATAB BIT(0) 113#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ 114 IF_COMM_CONTROL | IF_COMM_TXRQST | \ 115 IF_COMM_DATAA | IF_COMM_DATAB) 116 117/* For the low buffers we clear the interrupt bit, but keep newdat */ 118#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 119 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 120 IF_COMM_DATAA | IF_COMM_DATAB) 121 122/* For the high buffers we clear the interrupt bit and newdat */ 123#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_TXRQST) 124 125/* IFx arbitration */ 126#define IF_ARB_MSGVAL BIT(15) 127#define IF_ARB_MSGXTD BIT(14) 128#define IF_ARB_TRANSMIT BIT(13) 129 130/* IFx message control */ 131#define IF_MCONT_NEWDAT BIT(15) 132#define IF_MCONT_MSGLST BIT(14) 133#define IF_MCONT_INTPND BIT(13) 134#define IF_MCONT_UMASK BIT(12) 135#define IF_MCONT_TXIE BIT(11) 136#define IF_MCONT_RXIE BIT(10) 137#define IF_MCONT_RMTEN BIT(9) 138#define IF_MCONT_TXRQST BIT(8) 139#define IF_MCONT_EOB BIT(7) 140#define IF_MCONT_DLC_MASK 0xf 141 142/* 143 * Use IF1 for RX and IF2 for TX 144 */ 145#define IF_RX 0 146#define IF_TX 1 147 148/* status interrupt */ 149#define STATUS_INTERRUPT 0x8000 150 151/* global interrupt masks */ 152#define ENABLE_ALL_INTERRUPTS 1 153#define DISABLE_ALL_INTERRUPTS 0 154 155/* minimum timeout for checking BUSY status */ 156#define MIN_TIMEOUT_VALUE 6 157 158/* Wait for ~1 sec for INIT bit */ 159#define INIT_WAIT_MS 1000 160 161/* napi related */ 162#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 163 164/* c_can lec values */ 165enum c_can_lec_type { 166 LEC_NO_ERROR = 0, 167 LEC_STUFF_ERROR, 168 LEC_FORM_ERROR, 169 LEC_ACK_ERROR, 170 LEC_BIT1_ERROR, 171 LEC_BIT0_ERROR, 172 LEC_CRC_ERROR, 173 LEC_UNUSED, 174}; 175 176/* 177 * c_can error types: 178 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 179 */ 180enum c_can_bus_error_types { 181 C_CAN_NO_ERROR = 0, 182 C_CAN_BUS_OFF, 183 C_CAN_ERROR_WARNING, 184 C_CAN_ERROR_PASSIVE, 185}; 186 187static const struct can_bittiming_const c_can_bittiming_const = { 188 .name = KBUILD_MODNAME, 189 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 190 .tseg1_max = 16, 191 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 192 .tseg2_max = 8, 193 .sjw_max = 4, 194 .brp_min = 1, 195 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 196 .brp_inc = 1, 197}; 198 199static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 200{ 201 if (priv->device) 202 pm_runtime_enable(priv->device); 203} 204 205static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 206{ 207 if (priv->device) 208 pm_runtime_disable(priv->device); 209} 210 211static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 212{ 213 if (priv->device) 214 pm_runtime_get_sync(priv->device); 215} 216 217static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 218{ 219 if (priv->device) 220 pm_runtime_put_sync(priv->device); 221} 222 223static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 224{ 225 if (priv->raminit) 226 priv->raminit(priv, enable); 227} 228 229static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 230{ 231 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + 232 C_CAN_MSG_OBJ_TX_FIRST; 233} 234 235static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv) 236{ 237 return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) + 238 C_CAN_MSG_OBJ_TX_FIRST; 239} 240 241static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) 242{ 243 u32 val = priv->read_reg(priv, index); 244 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 245 return val; 246} 247 248static void c_can_enable_all_interrupts(struct c_can_priv *priv, 249 int enable) 250{ 251 unsigned int cntrl_save = priv->read_reg(priv, 252 C_CAN_CTRL_REG); 253 254 if (enable) 255 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 256 else 257 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); 258 259 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); 260} 261 262static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 263{ 264 int count = MIN_TIMEOUT_VALUE; 265 266 while (count && priv->read_reg(priv, 267 C_CAN_IFACE(COMREQ_REG, iface)) & 268 IF_COMR_BUSY) { 269 count--; 270 udelay(1); 271 } 272 273 if (!count) 274 return 1; 275 276 return 0; 277} 278 279static inline void c_can_object_get(struct net_device *dev, 280 int iface, int objno, int mask) 281{ 282 struct c_can_priv *priv = netdev_priv(dev); 283 284 /* 285 * As per specs, after writting the message object number in the 286 * IF command request register the transfer b/w interface 287 * register and message RAM must be complete in 6 CAN-CLK 288 * period. 289 */ 290 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 291 IFX_WRITE_LOW_16BIT(mask)); 292 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 293 IFX_WRITE_LOW_16BIT(objno)); 294 295 if (c_can_msg_obj_is_busy(priv, iface)) 296 netdev_err(dev, "timed out in object get\n"); 297} 298 299static inline void c_can_object_put(struct net_device *dev, 300 int iface, int objno, int mask) 301{ 302 struct c_can_priv *priv = netdev_priv(dev); 303 304 /* 305 * As per specs, after writting the message object number in the 306 * IF command request register the transfer b/w interface 307 * register and message RAM must be complete in 6 CAN-CLK 308 * period. 309 */ 310 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 311 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); 312 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 313 IFX_WRITE_LOW_16BIT(objno)); 314 315 if (c_can_msg_obj_is_busy(priv, iface)) 316 netdev_err(dev, "timed out in object put\n"); 317} 318 319static void c_can_write_msg_object(struct net_device *dev, 320 int iface, struct can_frame *frame, int objno) 321{ 322 int i; 323 u16 flags = 0; 324 unsigned int id; 325 struct c_can_priv *priv = netdev_priv(dev); 326 327 if (!(frame->can_id & CAN_RTR_FLAG)) 328 flags |= IF_ARB_TRANSMIT; 329 330 if (frame->can_id & CAN_EFF_FLAG) { 331 id = frame->can_id & CAN_EFF_MASK; 332 flags |= IF_ARB_MSGXTD; 333 } else 334 id = ((frame->can_id & CAN_SFF_MASK) << 18); 335 336 flags |= IF_ARB_MSGVAL; 337 338 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 339 IFX_WRITE_LOW_16BIT(id)); 340 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | 341 IFX_WRITE_HIGH_16BIT(id)); 342 343 for (i = 0; i < frame->can_dlc; i += 2) { 344 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 345 frame->data[i] | (frame->data[i + 1] << 8)); 346 } 347 348 /* enable interrupt for this message object */ 349 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 350 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | 351 frame->can_dlc); 352 c_can_object_put(dev, iface, objno, IF_COMM_ALL); 353} 354 355static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 356 int iface, 357 int ctrl_mask) 358{ 359 int i; 360 struct c_can_priv *priv = netdev_priv(dev); 361 362 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { 363 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 364 ctrl_mask & ~IF_MCONT_NEWDAT); 365 c_can_object_put(dev, iface, i, IF_COMM_CONTROL); 366 } 367} 368 369static int c_can_handle_lost_msg_obj(struct net_device *dev, 370 int iface, int objno, u32 ctrl) 371{ 372 struct net_device_stats *stats = &dev->stats; 373 struct c_can_priv *priv = netdev_priv(dev); 374 struct can_frame *frame; 375 struct sk_buff *skb; 376 377 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 378 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 379 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 380 381 /* create an error msg */ 382 skb = alloc_can_err_skb(dev, &frame); 383 if (unlikely(!skb)) 384 return 0; 385 386 frame->can_id |= CAN_ERR_CRTL; 387 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 388 stats->rx_errors++; 389 stats->rx_over_errors++; 390 391 netif_receive_skb(skb); 392 return 1; 393} 394 395static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) 396{ 397 u16 flags, data; 398 int i; 399 unsigned int val; 400 struct c_can_priv *priv = netdev_priv(dev); 401 struct net_device_stats *stats = &dev->stats; 402 struct sk_buff *skb; 403 struct can_frame *frame; 404 405 skb = alloc_can_skb(dev, &frame); 406 if (!skb) { 407 stats->rx_dropped++; 408 return -ENOMEM; 409 } 410 411 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 412 413 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); 414 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | 415 (flags << 16); 416 417 if (flags & IF_ARB_MSGXTD) 418 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; 419 else 420 frame->can_id = (val >> 18) & CAN_SFF_MASK; 421 422 if (flags & IF_ARB_TRANSMIT) 423 frame->can_id |= CAN_RTR_FLAG; 424 else { 425 for (i = 0; i < frame->can_dlc; i += 2) { 426 data = priv->read_reg(priv, 427 C_CAN_IFACE(DATA1_REG, iface) + i / 2); 428 frame->data[i] = data; 429 frame->data[i + 1] = data >> 8; 430 } 431 } 432 433 netif_receive_skb(skb); 434 435 stats->rx_packets++; 436 stats->rx_bytes += frame->can_dlc; 437 438 can_led_event(dev, CAN_LED_EVENT_RX); 439 440 return 0; 441} 442 443static void c_can_setup_receive_object(struct net_device *dev, int iface, 444 int objno, unsigned int mask, 445 unsigned int id, unsigned int mcont) 446{ 447 struct c_can_priv *priv = netdev_priv(dev); 448 449 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), 450 IFX_WRITE_LOW_16BIT(mask)); 451 452 /* According to C_CAN documentation, the reserved bit 453 * in IFx_MASK2 register is fixed 1 454 */ 455 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), 456 IFX_WRITE_HIGH_16BIT(mask) | BIT(13)); 457 458 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 459 IFX_WRITE_LOW_16BIT(id)); 460 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 461 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); 462 463 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 464 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 465 466 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 467 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 468} 469 470static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) 471{ 472 struct c_can_priv *priv = netdev_priv(dev); 473 474 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 475 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 476 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 477 478 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); 479 480 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 481 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 482} 483 484static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 485{ 486 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 487 488 /* 489 * as transmission request register's bit n-1 corresponds to 490 * message object n, we need to handle the same properly. 491 */ 492 if (val & (1 << (objno - 1))) 493 return 1; 494 495 return 0; 496} 497 498static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 499 struct net_device *dev) 500{ 501 u32 msg_obj_no; 502 struct c_can_priv *priv = netdev_priv(dev); 503 struct can_frame *frame = (struct can_frame *)skb->data; 504 505 if (can_dropped_invalid_skb(dev, skb)) 506 return NETDEV_TX_OK; 507 508 spin_lock_bh(&priv->xmit_lock); 509 msg_obj_no = get_tx_next_msg_obj(priv); 510 511 /* prepare message object for transmission */ 512 c_can_write_msg_object(dev, IF_TX, frame, msg_obj_no); 513 priv->dlc[msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST] = frame->can_dlc; 514 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 515 516 /* 517 * we have to stop the queue in case of a wrap around or 518 * if the next TX message object is still in use 519 */ 520 priv->tx_next++; 521 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 522 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 523 netif_stop_queue(dev); 524 spin_unlock_bh(&priv->xmit_lock); 525 526 return NETDEV_TX_OK; 527} 528 529static int c_can_wait_for_ctrl_init(struct net_device *dev, 530 struct c_can_priv *priv, u32 init) 531{ 532 int retry = 0; 533 534 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 535 udelay(10); 536 if (retry++ > 1000) { 537 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 538 return -EIO; 539 } 540 } 541 return 0; 542} 543 544static int c_can_set_bittiming(struct net_device *dev) 545{ 546 unsigned int reg_btr, reg_brpe, ctrl_save; 547 u8 brp, brpe, sjw, tseg1, tseg2; 548 u32 ten_bit_brp; 549 struct c_can_priv *priv = netdev_priv(dev); 550 const struct can_bittiming *bt = &priv->can.bittiming; 551 int res; 552 553 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 554 ten_bit_brp = bt->brp - 1; 555 brp = ten_bit_brp & BTR_BRP_MASK; 556 brpe = ten_bit_brp >> 6; 557 558 sjw = bt->sjw - 1; 559 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 560 tseg2 = bt->phase_seg2 - 1; 561 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 562 (tseg2 << BTR_TSEG2_SHIFT); 563 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 564 565 netdev_info(dev, 566 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 567 568 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 569 ctrl_save &= ~CONTROL_INIT; 570 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 571 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 572 if (res) 573 return res; 574 575 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 576 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 577 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 578 579 return c_can_wait_for_ctrl_init(dev, priv, 0); 580} 581 582/* 583 * Configure C_CAN message objects for Tx and Rx purposes: 584 * C_CAN provides a total of 32 message objects that can be configured 585 * either for Tx or Rx purposes. Here the first 16 message objects are used as 586 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 587 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 588 * See user guide document for further details on configuring message 589 * objects. 590 */ 591static void c_can_configure_msg_objects(struct net_device *dev) 592{ 593 int i; 594 595 /* first invalidate all message objects */ 596 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 597 c_can_inval_msg_object(dev, IF_RX, i); 598 599 /* setup receive message objects */ 600 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 601 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, 602 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); 603 604 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 605 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); 606} 607 608/* 609 * Configure C_CAN chip: 610 * - enable/disable auto-retransmission 611 * - set operating mode 612 * - configure message objects 613 */ 614static int c_can_chip_config(struct net_device *dev) 615{ 616 struct c_can_priv *priv = netdev_priv(dev); 617 618 /* enable automatic retransmission */ 619 priv->write_reg(priv, C_CAN_CTRL_REG, 620 CONTROL_ENABLE_AR); 621 622 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 623 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 624 /* loopback + silent mode : useful for hot self-test */ 625 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 626 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 627 priv->write_reg(priv, C_CAN_TEST_REG, 628 TEST_LBACK | TEST_SILENT); 629 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 630 /* loopback mode : useful for self-test function */ 631 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 632 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 633 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 634 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 635 /* silent mode : bus-monitoring mode */ 636 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 637 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 638 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 639 } else 640 /* normal mode*/ 641 priv->write_reg(priv, C_CAN_CTRL_REG, 642 CONTROL_EIE | CONTROL_SIE | CONTROL_IE); 643 644 /* configure message objects */ 645 c_can_configure_msg_objects(dev); 646 647 /* set a `lec` value so that we can check for updates later */ 648 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 649 650 /* set bittiming params */ 651 return c_can_set_bittiming(dev); 652} 653 654static int c_can_start(struct net_device *dev) 655{ 656 struct c_can_priv *priv = netdev_priv(dev); 657 int err; 658 659 /* basic c_can configuration */ 660 err = c_can_chip_config(dev); 661 if (err) 662 return err; 663 664 priv->can.state = CAN_STATE_ERROR_ACTIVE; 665 666 /* reset tx helper pointers */ 667 priv->tx_next = priv->tx_echo = 0; 668 669 /* enable status change, error and module interrupts */ 670 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 671 672 return 0; 673} 674 675static void c_can_stop(struct net_device *dev) 676{ 677 struct c_can_priv *priv = netdev_priv(dev); 678 679 /* disable all interrupts */ 680 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 681 682 /* set the state as STOPPED */ 683 priv->can.state = CAN_STATE_STOPPED; 684} 685 686static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 687{ 688 int err; 689 690 switch (mode) { 691 case CAN_MODE_START: 692 err = c_can_start(dev); 693 if (err) 694 return err; 695 netif_wake_queue(dev); 696 break; 697 default: 698 return -EOPNOTSUPP; 699 } 700 701 return 0; 702} 703 704static int __c_can_get_berr_counter(const struct net_device *dev, 705 struct can_berr_counter *bec) 706{ 707 unsigned int reg_err_counter; 708 struct c_can_priv *priv = netdev_priv(dev); 709 710 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 711 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 712 ERR_CNT_REC_SHIFT; 713 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 714 715 return 0; 716} 717 718static int c_can_get_berr_counter(const struct net_device *dev, 719 struct can_berr_counter *bec) 720{ 721 struct c_can_priv *priv = netdev_priv(dev); 722 int err; 723 724 c_can_pm_runtime_get_sync(priv); 725 err = __c_can_get_berr_counter(dev, bec); 726 c_can_pm_runtime_put_sync(priv); 727 728 return err; 729} 730 731/* 732 * theory of operation: 733 * 734 * priv->tx_echo holds the number of the oldest can_frame put for 735 * transmission into the hardware, but not yet ACKed by the CAN tx 736 * complete IRQ. 737 * 738 * We iterate from priv->tx_echo to priv->tx_next and check if the 739 * packet has been transmitted, echo it back to the CAN framework. 740 * If we discover a not yet transmitted packet, stop looking for more. 741 */ 742static void c_can_do_tx(struct net_device *dev) 743{ 744 u32 val; 745 u32 msg_obj_no; 746 struct c_can_priv *priv = netdev_priv(dev); 747 struct net_device_stats *stats = &dev->stats; 748 749 spin_lock_bh(&priv->xmit_lock); 750 751 for (; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 752 msg_obj_no = get_tx_echo_msg_obj(priv); 753 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 754 if (!(val & (1 << (msg_obj_no - 1)))) { 755 can_get_echo_skb(dev, 756 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 757 c_can_object_get(dev, IF_TX, msg_obj_no, IF_COMM_ALL); 758 stats->tx_bytes += priv->read_reg(priv, 759 C_CAN_IFACE(MSGCTRL_REG, IF_TX)) 760 & IF_MCONT_DLC_MASK; 761 stats->tx_packets++; 762 can_led_event(dev, CAN_LED_EVENT_TX); 763 c_can_inval_msg_object(dev, IF_TX, msg_obj_no); 764 } else { 765 break; 766 } 767 } 768 769 /* restart queue if wrap-up or if queue stalled on last pkt */ 770 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 771 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) 772 netif_wake_queue(dev); 773 774 spin_unlock_bh(&priv->xmit_lock); 775} 776 777/* 778 * If we have a gap in the pending bits, that means we either 779 * raced with the hardware or failed to readout all upper 780 * objects in the last run due to quota limit. 781 */ 782static u32 c_can_adjust_pending(u32 pend) 783{ 784 u32 weight, lasts; 785 786 if (pend == RECEIVE_OBJECT_BITS) 787 return pend; 788 789 /* 790 * If the last set bit is larger than the number of pending 791 * bits we have a gap. 792 */ 793 weight = hweight32(pend); 794 lasts = fls(pend); 795 796 /* If the bits are linear, nothing to do */ 797 if (lasts == weight) 798 return pend; 799 800 /* 801 * Find the first set bit after the gap. We walk backwards 802 * from the last set bit. 803 */ 804 for (lasts--; pend & (1 << (lasts - 1)); lasts--); 805 806 return pend & ~((1 << lasts) - 1); 807} 808 809static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 810 u32 pend, int quota) 811{ 812 u32 pkts = 0, ctrl, obj, mcmd; 813 814 while ((obj = ffs(pend)) && quota > 0) { 815 pend &= ~BIT(obj - 1); 816 817 mcmd = obj < C_CAN_MSG_RX_LOW_LAST ? 818 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 819 820 c_can_object_get(dev, IF_RX, obj, mcmd); 821 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 822 823 if (ctrl & IF_MCONT_MSGLST) { 824 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); 825 826 pkts += n; 827 quota -= n; 828 continue; 829 } 830 831 /* 832 * This really should not happen, but this covers some 833 * odd HW behaviour. Do not remove that unless you 834 * want to brick your machine. 835 */ 836 if (!(ctrl & IF_MCONT_NEWDAT)) 837 continue; 838 839 /* read the data from the message object */ 840 c_can_read_msg_object(dev, IF_RX, ctrl); 841 842 if (obj == C_CAN_MSG_RX_LOW_LAST) 843 /* activate all lower message objects */ 844 c_can_activate_all_lower_rx_msg_obj(dev, IF_RX, ctrl); 845 846 pkts++; 847 quota--; 848 } 849 850 return pkts; 851} 852 853/* 854 * theory of operation: 855 * 856 * c_can core saves a received CAN message into the first free message 857 * object it finds free (starting with the lowest). Bits NEWDAT and 858 * INTPND are set for this message object indicating that a new message 859 * has arrived. To work-around this issue, we keep two groups of message 860 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 861 * 862 * To ensure in-order frame reception we use the following 863 * approach while re-activating a message object to receive further 864 * frames: 865 * - if the current message object number is lower than 866 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 867 * the INTPND bit. 868 * - if the current message object number is equal to 869 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 870 * receive message objects. 871 * - if the current message object number is greater than 872 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 873 * only this message object. 874 */ 875static int c_can_do_rx_poll(struct net_device *dev, int quota) 876{ 877 struct c_can_priv *priv = netdev_priv(dev); 878 u32 pkts = 0, pend = 0, toread, n; 879 880 /* 881 * It is faster to read only one 16bit register. This is only possible 882 * for a maximum number of 16 objects. 883 */ 884 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, 885 "Implementation does not support more message objects than 16"); 886 887 while (quota > 0) { 888 if (!pend) { 889 pend = priv->read_reg(priv, C_CAN_INTPND1_REG); 890 if (!pend) 891 break; 892 /* 893 * If the pending field has a gap, handle the 894 * bits above the gap first. 895 */ 896 toread = c_can_adjust_pending(pend); 897 } else { 898 toread = pend; 899 } 900 /* Remove the bits from pend */ 901 pend &= ~toread; 902 /* Read the objects */ 903 n = c_can_read_objects(dev, priv, toread, quota); 904 pkts += n; 905 quota -= n; 906 } 907 return pkts; 908} 909 910static inline int c_can_has_and_handle_berr(struct c_can_priv *priv) 911{ 912 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 913 (priv->current_status & LEC_UNUSED); 914} 915 916static int c_can_handle_state_change(struct net_device *dev, 917 enum c_can_bus_error_types error_type) 918{ 919 unsigned int reg_err_counter; 920 unsigned int rx_err_passive; 921 struct c_can_priv *priv = netdev_priv(dev); 922 struct net_device_stats *stats = &dev->stats; 923 struct can_frame *cf; 924 struct sk_buff *skb; 925 struct can_berr_counter bec; 926 927 /* propagate the error condition to the CAN stack */ 928 skb = alloc_can_err_skb(dev, &cf); 929 if (unlikely(!skb)) 930 return 0; 931 932 __c_can_get_berr_counter(dev, &bec); 933 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 934 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 935 ERR_CNT_RP_SHIFT; 936 937 switch (error_type) { 938 case C_CAN_ERROR_WARNING: 939 /* error warning state */ 940 priv->can.can_stats.error_warning++; 941 priv->can.state = CAN_STATE_ERROR_WARNING; 942 cf->can_id |= CAN_ERR_CRTL; 943 cf->data[1] = (bec.txerr > bec.rxerr) ? 944 CAN_ERR_CRTL_TX_WARNING : 945 CAN_ERR_CRTL_RX_WARNING; 946 cf->data[6] = bec.txerr; 947 cf->data[7] = bec.rxerr; 948 949 break; 950 case C_CAN_ERROR_PASSIVE: 951 /* error passive state */ 952 priv->can.can_stats.error_passive++; 953 priv->can.state = CAN_STATE_ERROR_PASSIVE; 954 cf->can_id |= CAN_ERR_CRTL; 955 if (rx_err_passive) 956 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 957 if (bec.txerr > 127) 958 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 959 960 cf->data[6] = bec.txerr; 961 cf->data[7] = bec.rxerr; 962 break; 963 case C_CAN_BUS_OFF: 964 /* bus-off state */ 965 priv->can.state = CAN_STATE_BUS_OFF; 966 cf->can_id |= CAN_ERR_BUSOFF; 967 /* 968 * disable all interrupts in bus-off mode to ensure that 969 * the CPU is not hogged down 970 */ 971 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 972 can_bus_off(dev); 973 break; 974 default: 975 break; 976 } 977 978 netif_receive_skb(skb); 979 stats->rx_packets++; 980 stats->rx_bytes += cf->can_dlc; 981 982 return 1; 983} 984 985static int c_can_handle_bus_err(struct net_device *dev, 986 enum c_can_lec_type lec_type) 987{ 988 struct c_can_priv *priv = netdev_priv(dev); 989 struct net_device_stats *stats = &dev->stats; 990 struct can_frame *cf; 991 struct sk_buff *skb; 992 993 /* 994 * early exit if no lec update or no error. 995 * no lec update means that no CAN bus event has been detected 996 * since CPU wrote 0x7 value to status reg. 997 */ 998 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 999 return 0; 1000 1001 /* propagate the error condition to the CAN stack */ 1002 skb = alloc_can_err_skb(dev, &cf); 1003 if (unlikely(!skb)) 1004 return 0; 1005 1006 /* 1007 * check for 'last error code' which tells us the 1008 * type of the last error to occur on the CAN bus 1009 */ 1010 1011 /* common for all type of bus errors */ 1012 priv->can.can_stats.bus_error++; 1013 stats->rx_errors++; 1014 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1015 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 1016 1017 switch (lec_type) { 1018 case LEC_STUFF_ERROR: 1019 netdev_dbg(dev, "stuff error\n"); 1020 cf->data[2] |= CAN_ERR_PROT_STUFF; 1021 break; 1022 case LEC_FORM_ERROR: 1023 netdev_dbg(dev, "form error\n"); 1024 cf->data[2] |= CAN_ERR_PROT_FORM; 1025 break; 1026 case LEC_ACK_ERROR: 1027 netdev_dbg(dev, "ack error\n"); 1028 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 1029 CAN_ERR_PROT_LOC_ACK_DEL); 1030 break; 1031 case LEC_BIT1_ERROR: 1032 netdev_dbg(dev, "bit1 error\n"); 1033 cf->data[2] |= CAN_ERR_PROT_BIT1; 1034 break; 1035 case LEC_BIT0_ERROR: 1036 netdev_dbg(dev, "bit0 error\n"); 1037 cf->data[2] |= CAN_ERR_PROT_BIT0; 1038 break; 1039 case LEC_CRC_ERROR: 1040 netdev_dbg(dev, "CRC error\n"); 1041 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 1042 CAN_ERR_PROT_LOC_CRC_DEL); 1043 break; 1044 default: 1045 break; 1046 } 1047 1048 /* set a `lec` value so that we can check for updates later */ 1049 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1050 1051 netif_receive_skb(skb); 1052 stats->rx_packets++; 1053 stats->rx_bytes += cf->can_dlc; 1054 1055 return 1; 1056} 1057 1058static int c_can_poll(struct napi_struct *napi, int quota) 1059{ 1060 u16 irqstatus; 1061 int lec_type = 0; 1062 int work_done = 0; 1063 struct net_device *dev = napi->dev; 1064 struct c_can_priv *priv = netdev_priv(dev); 1065 1066 irqstatus = priv->irqstatus; 1067 if (!irqstatus) 1068 goto end; 1069 1070 /* status events have the highest priority */ 1071 if (irqstatus == STATUS_INTERRUPT) { 1072 priv->current_status = priv->read_reg(priv, 1073 C_CAN_STS_REG); 1074 1075 /* handle Tx/Rx events */ 1076 if (priv->current_status & STATUS_TXOK) 1077 priv->write_reg(priv, C_CAN_STS_REG, 1078 priv->current_status & ~STATUS_TXOK); 1079 1080 if (priv->current_status & STATUS_RXOK) 1081 priv->write_reg(priv, C_CAN_STS_REG, 1082 priv->current_status & ~STATUS_RXOK); 1083 1084 /* handle state changes */ 1085 if ((priv->current_status & STATUS_EWARN) && 1086 (!(priv->last_status & STATUS_EWARN))) { 1087 netdev_dbg(dev, "entered error warning state\n"); 1088 work_done += c_can_handle_state_change(dev, 1089 C_CAN_ERROR_WARNING); 1090 } 1091 if ((priv->current_status & STATUS_EPASS) && 1092 (!(priv->last_status & STATUS_EPASS))) { 1093 netdev_dbg(dev, "entered error passive state\n"); 1094 work_done += c_can_handle_state_change(dev, 1095 C_CAN_ERROR_PASSIVE); 1096 } 1097 if ((priv->current_status & STATUS_BOFF) && 1098 (!(priv->last_status & STATUS_BOFF))) { 1099 netdev_dbg(dev, "entered bus off state\n"); 1100 work_done += c_can_handle_state_change(dev, 1101 C_CAN_BUS_OFF); 1102 } 1103 1104 /* handle bus recovery events */ 1105 if ((!(priv->current_status & STATUS_BOFF)) && 1106 (priv->last_status & STATUS_BOFF)) { 1107 netdev_dbg(dev, "left bus off state\n"); 1108 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1109 } 1110 if ((!(priv->current_status & STATUS_EPASS)) && 1111 (priv->last_status & STATUS_EPASS)) { 1112 netdev_dbg(dev, "left error passive state\n"); 1113 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1114 } 1115 1116 priv->last_status = priv->current_status; 1117 1118 /* handle lec errors on the bus */ 1119 lec_type = c_can_has_and_handle_berr(priv); 1120 if (lec_type) 1121 work_done += c_can_handle_bus_err(dev, lec_type); 1122 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && 1123 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { 1124 /* handle events corresponding to receive message objects */ 1125 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1126 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && 1127 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { 1128 /* handle events corresponding to transmit message objects */ 1129 c_can_do_tx(dev); 1130 } 1131 1132end: 1133 if (work_done < quota) { 1134 napi_complete(napi); 1135 /* enable all IRQs */ 1136 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1137 } 1138 1139 return work_done; 1140} 1141 1142static irqreturn_t c_can_isr(int irq, void *dev_id) 1143{ 1144 struct net_device *dev = (struct net_device *)dev_id; 1145 struct c_can_priv *priv = netdev_priv(dev); 1146 1147 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); 1148 if (!priv->irqstatus) 1149 return IRQ_NONE; 1150 1151 /* disable all interrupts and schedule the NAPI */ 1152 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1153 napi_schedule(&priv->napi); 1154 1155 return IRQ_HANDLED; 1156} 1157 1158static int c_can_open(struct net_device *dev) 1159{ 1160 int err; 1161 struct c_can_priv *priv = netdev_priv(dev); 1162 1163 c_can_pm_runtime_get_sync(priv); 1164 c_can_reset_ram(priv, true); 1165 1166 /* open the can device */ 1167 err = open_candev(dev); 1168 if (err) { 1169 netdev_err(dev, "failed to open can device\n"); 1170 goto exit_open_fail; 1171 } 1172 1173 /* register interrupt handler */ 1174 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1175 dev); 1176 if (err < 0) { 1177 netdev_err(dev, "failed to request interrupt\n"); 1178 goto exit_irq_fail; 1179 } 1180 1181 /* start the c_can controller */ 1182 err = c_can_start(dev); 1183 if (err) 1184 goto exit_start_fail; 1185 1186 can_led_event(dev, CAN_LED_EVENT_OPEN); 1187 1188 napi_enable(&priv->napi); 1189 netif_start_queue(dev); 1190 1191 return 0; 1192 1193exit_start_fail: 1194 free_irq(dev->irq, dev); 1195exit_irq_fail: 1196 close_candev(dev); 1197exit_open_fail: 1198 c_can_reset_ram(priv, false); 1199 c_can_pm_runtime_put_sync(priv); 1200 return err; 1201} 1202 1203static int c_can_close(struct net_device *dev) 1204{ 1205 struct c_can_priv *priv = netdev_priv(dev); 1206 1207 netif_stop_queue(dev); 1208 napi_disable(&priv->napi); 1209 c_can_stop(dev); 1210 free_irq(dev->irq, dev); 1211 close_candev(dev); 1212 1213 c_can_reset_ram(priv, false); 1214 c_can_pm_runtime_put_sync(priv); 1215 1216 can_led_event(dev, CAN_LED_EVENT_STOP); 1217 1218 return 0; 1219} 1220 1221struct net_device *alloc_c_can_dev(void) 1222{ 1223 struct net_device *dev; 1224 struct c_can_priv *priv; 1225 1226 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1227 if (!dev) 1228 return NULL; 1229 1230 priv = netdev_priv(dev); 1231 spin_lock_init(&priv->xmit_lock); 1232 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1233 1234 priv->dev = dev; 1235 priv->can.bittiming_const = &c_can_bittiming_const; 1236 priv->can.do_set_mode = c_can_set_mode; 1237 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1238 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1239 CAN_CTRLMODE_LISTENONLY | 1240 CAN_CTRLMODE_BERR_REPORTING; 1241 1242 return dev; 1243} 1244EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1245 1246#ifdef CONFIG_PM 1247int c_can_power_down(struct net_device *dev) 1248{ 1249 u32 val; 1250 unsigned long time_out; 1251 struct c_can_priv *priv = netdev_priv(dev); 1252 1253 if (!(dev->flags & IFF_UP)) 1254 return 0; 1255 1256 WARN_ON(priv->type != BOSCH_D_CAN); 1257 1258 /* set PDR value so the device goes to power down mode */ 1259 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1260 val |= CONTROL_EX_PDR; 1261 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1262 1263 /* Wait for the PDA bit to get set */ 1264 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1265 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1266 time_after(time_out, jiffies)) 1267 cpu_relax(); 1268 1269 if (time_after(jiffies, time_out)) 1270 return -ETIMEDOUT; 1271 1272 c_can_stop(dev); 1273 1274 c_can_reset_ram(priv, false); 1275 c_can_pm_runtime_put_sync(priv); 1276 1277 return 0; 1278} 1279EXPORT_SYMBOL_GPL(c_can_power_down); 1280 1281int c_can_power_up(struct net_device *dev) 1282{ 1283 u32 val; 1284 unsigned long time_out; 1285 struct c_can_priv *priv = netdev_priv(dev); 1286 1287 if (!(dev->flags & IFF_UP)) 1288 return 0; 1289 1290 WARN_ON(priv->type != BOSCH_D_CAN); 1291 1292 c_can_pm_runtime_get_sync(priv); 1293 c_can_reset_ram(priv, true); 1294 1295 /* Clear PDR and INIT bits */ 1296 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1297 val &= ~CONTROL_EX_PDR; 1298 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1299 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1300 val &= ~CONTROL_INIT; 1301 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1302 1303 /* Wait for the PDA bit to get clear */ 1304 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1305 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1306 time_after(time_out, jiffies)) 1307 cpu_relax(); 1308 1309 if (time_after(jiffies, time_out)) 1310 return -ETIMEDOUT; 1311 1312 return c_can_start(dev); 1313} 1314EXPORT_SYMBOL_GPL(c_can_power_up); 1315#endif 1316 1317void free_c_can_dev(struct net_device *dev) 1318{ 1319 struct c_can_priv *priv = netdev_priv(dev); 1320 1321 netif_napi_del(&priv->napi); 1322 free_candev(dev); 1323} 1324EXPORT_SYMBOL_GPL(free_c_can_dev); 1325 1326static const struct net_device_ops c_can_netdev_ops = { 1327 .ndo_open = c_can_open, 1328 .ndo_stop = c_can_close, 1329 .ndo_start_xmit = c_can_start_xmit, 1330}; 1331 1332int register_c_can_dev(struct net_device *dev) 1333{ 1334 struct c_can_priv *priv = netdev_priv(dev); 1335 int err; 1336 1337 c_can_pm_runtime_enable(priv); 1338 1339 dev->flags |= IFF_ECHO; /* we support local echo */ 1340 dev->netdev_ops = &c_can_netdev_ops; 1341 1342 err = register_candev(dev); 1343 if (err) 1344 c_can_pm_runtime_disable(priv); 1345 else 1346 devm_can_led_init(dev); 1347 1348 return err; 1349} 1350EXPORT_SYMBOL_GPL(register_c_can_dev); 1351 1352void unregister_c_can_dev(struct net_device *dev) 1353{ 1354 struct c_can_priv *priv = netdev_priv(dev); 1355 1356 unregister_candev(dev); 1357 1358 c_can_pm_runtime_disable(priv); 1359} 1360EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1361 1362MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1363MODULE_LICENSE("GPL v2"); 1364MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1365