c_can.c revision bed11db3d4095e5f818f5e8bf7f43ef2beb36d4e
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42#include <linux/can/led.h> 43 44#include "c_can.h" 45 46/* Number of interface registers */ 47#define IF_ENUM_REG_LEN 11 48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 49 50/* control extension register D_CAN specific */ 51#define CONTROL_EX_PDR BIT(8) 52 53/* control register */ 54#define CONTROL_TEST BIT(7) 55#define CONTROL_CCE BIT(6) 56#define CONTROL_DISABLE_AR BIT(5) 57#define CONTROL_ENABLE_AR (0 << 5) 58#define CONTROL_EIE BIT(3) 59#define CONTROL_SIE BIT(2) 60#define CONTROL_IE BIT(1) 61#define CONTROL_INIT BIT(0) 62 63/* test register */ 64#define TEST_RX BIT(7) 65#define TEST_TX1 BIT(6) 66#define TEST_TX2 BIT(5) 67#define TEST_LBACK BIT(4) 68#define TEST_SILENT BIT(3) 69#define TEST_BASIC BIT(2) 70 71/* status register */ 72#define STATUS_PDA BIT(10) 73#define STATUS_BOFF BIT(7) 74#define STATUS_EWARN BIT(6) 75#define STATUS_EPASS BIT(5) 76#define STATUS_RXOK BIT(4) 77#define STATUS_TXOK BIT(3) 78 79/* error counter register */ 80#define ERR_CNT_TEC_MASK 0xff 81#define ERR_CNT_TEC_SHIFT 0 82#define ERR_CNT_REC_SHIFT 8 83#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 84#define ERR_CNT_RP_SHIFT 15 85#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 86 87/* bit-timing register */ 88#define BTR_BRP_MASK 0x3f 89#define BTR_BRP_SHIFT 0 90#define BTR_SJW_SHIFT 6 91#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 92#define BTR_TSEG1_SHIFT 8 93#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 94#define BTR_TSEG2_SHIFT 12 95#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 96 97/* brp extension register */ 98#define BRP_EXT_BRPE_MASK 0x0f 99#define BRP_EXT_BRPE_SHIFT 0 100 101/* IFx command request */ 102#define IF_COMR_BUSY BIT(15) 103 104/* IFx command mask */ 105#define IF_COMM_WR BIT(7) 106#define IF_COMM_MASK BIT(6) 107#define IF_COMM_ARB BIT(5) 108#define IF_COMM_CONTROL BIT(4) 109#define IF_COMM_CLR_INT_PND BIT(3) 110#define IF_COMM_TXRQST BIT(2) 111#define IF_COMM_DATAA BIT(1) 112#define IF_COMM_DATAB BIT(0) 113#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ 114 IF_COMM_CONTROL | IF_COMM_TXRQST | \ 115 IF_COMM_DATAA | IF_COMM_DATAB) 116 117/* For the low buffers we clear the interrupt bit, but keep newdat */ 118#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 119 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 120 IF_COMM_DATAA | IF_COMM_DATAB) 121 122/* For the high buffers we clear the interrupt bit and newdat */ 123#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_TXRQST) 124 125/* IFx arbitration */ 126#define IF_ARB_MSGVAL BIT(15) 127#define IF_ARB_MSGXTD BIT(14) 128#define IF_ARB_TRANSMIT BIT(13) 129 130/* IFx message control */ 131#define IF_MCONT_NEWDAT BIT(15) 132#define IF_MCONT_MSGLST BIT(14) 133#define IF_MCONT_INTPND BIT(13) 134#define IF_MCONT_UMASK BIT(12) 135#define IF_MCONT_TXIE BIT(11) 136#define IF_MCONT_RXIE BIT(10) 137#define IF_MCONT_RMTEN BIT(9) 138#define IF_MCONT_TXRQST BIT(8) 139#define IF_MCONT_EOB BIT(7) 140#define IF_MCONT_DLC_MASK 0xf 141 142/* 143 * Use IF1 for RX and IF2 for TX 144 */ 145#define IF_RX 0 146#define IF_TX 1 147 148/* status interrupt */ 149#define STATUS_INTERRUPT 0x8000 150 151/* global interrupt masks */ 152#define ENABLE_ALL_INTERRUPTS 1 153#define DISABLE_ALL_INTERRUPTS 0 154 155/* minimum timeout for checking BUSY status */ 156#define MIN_TIMEOUT_VALUE 6 157 158/* Wait for ~1 sec for INIT bit */ 159#define INIT_WAIT_MS 1000 160 161/* napi related */ 162#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 163 164/* c_can lec values */ 165enum c_can_lec_type { 166 LEC_NO_ERROR = 0, 167 LEC_STUFF_ERROR, 168 LEC_FORM_ERROR, 169 LEC_ACK_ERROR, 170 LEC_BIT1_ERROR, 171 LEC_BIT0_ERROR, 172 LEC_CRC_ERROR, 173 LEC_UNUSED, 174}; 175 176/* 177 * c_can error types: 178 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 179 */ 180enum c_can_bus_error_types { 181 C_CAN_NO_ERROR = 0, 182 C_CAN_BUS_OFF, 183 C_CAN_ERROR_WARNING, 184 C_CAN_ERROR_PASSIVE, 185}; 186 187static const struct can_bittiming_const c_can_bittiming_const = { 188 .name = KBUILD_MODNAME, 189 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 190 .tseg1_max = 16, 191 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 192 .tseg2_max = 8, 193 .sjw_max = 4, 194 .brp_min = 1, 195 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 196 .brp_inc = 1, 197}; 198 199static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 200{ 201 if (priv->device) 202 pm_runtime_enable(priv->device); 203} 204 205static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 206{ 207 if (priv->device) 208 pm_runtime_disable(priv->device); 209} 210 211static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 212{ 213 if (priv->device) 214 pm_runtime_get_sync(priv->device); 215} 216 217static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 218{ 219 if (priv->device) 220 pm_runtime_put_sync(priv->device); 221} 222 223static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 224{ 225 if (priv->raminit) 226 priv->raminit(priv, enable); 227} 228 229static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 230{ 231 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + 232 C_CAN_MSG_OBJ_TX_FIRST; 233} 234 235static inline int get_tx_echo_msg_obj(int txecho) 236{ 237 return (txecho & C_CAN_NEXT_MSG_OBJ_MASK) + C_CAN_MSG_OBJ_TX_FIRST; 238} 239 240static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) 241{ 242 u32 val = priv->read_reg(priv, index); 243 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 244 return val; 245} 246 247static void c_can_enable_all_interrupts(struct c_can_priv *priv, 248 int enable) 249{ 250 unsigned int cntrl_save = priv->read_reg(priv, 251 C_CAN_CTRL_REG); 252 253 if (enable) 254 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 255 else 256 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); 257 258 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); 259} 260 261static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 262{ 263 int count = MIN_TIMEOUT_VALUE; 264 265 while (count && priv->read_reg(priv, 266 C_CAN_IFACE(COMREQ_REG, iface)) & 267 IF_COMR_BUSY) { 268 count--; 269 udelay(1); 270 } 271 272 if (!count) 273 return 1; 274 275 return 0; 276} 277 278static inline void c_can_object_get(struct net_device *dev, 279 int iface, int objno, int mask) 280{ 281 struct c_can_priv *priv = netdev_priv(dev); 282 283 /* 284 * As per specs, after writting the message object number in the 285 * IF command request register the transfer b/w interface 286 * register and message RAM must be complete in 6 CAN-CLK 287 * period. 288 */ 289 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 290 IFX_WRITE_LOW_16BIT(mask)); 291 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 292 IFX_WRITE_LOW_16BIT(objno)); 293 294 if (c_can_msg_obj_is_busy(priv, iface)) 295 netdev_err(dev, "timed out in object get\n"); 296} 297 298static inline void c_can_object_put(struct net_device *dev, 299 int iface, int objno, int mask) 300{ 301 struct c_can_priv *priv = netdev_priv(dev); 302 303 /* 304 * As per specs, after writting the message object number in the 305 * IF command request register the transfer b/w interface 306 * register and message RAM must be complete in 6 CAN-CLK 307 * period. 308 */ 309 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 310 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); 311 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 312 IFX_WRITE_LOW_16BIT(objno)); 313 314 if (c_can_msg_obj_is_busy(priv, iface)) 315 netdev_err(dev, "timed out in object put\n"); 316} 317 318static void c_can_write_msg_object(struct net_device *dev, 319 int iface, struct can_frame *frame, int objno) 320{ 321 int i; 322 u16 flags = 0; 323 unsigned int id; 324 struct c_can_priv *priv = netdev_priv(dev); 325 326 if (!(frame->can_id & CAN_RTR_FLAG)) 327 flags |= IF_ARB_TRANSMIT; 328 329 if (frame->can_id & CAN_EFF_FLAG) { 330 id = frame->can_id & CAN_EFF_MASK; 331 flags |= IF_ARB_MSGXTD; 332 } else 333 id = ((frame->can_id & CAN_SFF_MASK) << 18); 334 335 flags |= IF_ARB_MSGVAL; 336 337 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 338 IFX_WRITE_LOW_16BIT(id)); 339 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | 340 IFX_WRITE_HIGH_16BIT(id)); 341 342 for (i = 0; i < frame->can_dlc; i += 2) { 343 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 344 frame->data[i] | (frame->data[i + 1] << 8)); 345 } 346 347 /* enable interrupt for this message object */ 348 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 349 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | 350 frame->can_dlc); 351 c_can_object_put(dev, iface, objno, IF_COMM_ALL); 352} 353 354static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 355 int iface, 356 int ctrl_mask) 357{ 358 int i; 359 struct c_can_priv *priv = netdev_priv(dev); 360 361 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { 362 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 363 ctrl_mask & ~IF_MCONT_NEWDAT); 364 c_can_object_put(dev, iface, i, IF_COMM_CONTROL); 365 } 366} 367 368static int c_can_handle_lost_msg_obj(struct net_device *dev, 369 int iface, int objno, u32 ctrl) 370{ 371 struct net_device_stats *stats = &dev->stats; 372 struct c_can_priv *priv = netdev_priv(dev); 373 struct can_frame *frame; 374 struct sk_buff *skb; 375 376 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 377 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 378 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 379 380 /* create an error msg */ 381 skb = alloc_can_err_skb(dev, &frame); 382 if (unlikely(!skb)) 383 return 0; 384 385 frame->can_id |= CAN_ERR_CRTL; 386 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 387 stats->rx_errors++; 388 stats->rx_over_errors++; 389 390 netif_receive_skb(skb); 391 return 1; 392} 393 394static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) 395{ 396 u16 flags, data; 397 int i; 398 unsigned int val; 399 struct c_can_priv *priv = netdev_priv(dev); 400 struct net_device_stats *stats = &dev->stats; 401 struct sk_buff *skb; 402 struct can_frame *frame; 403 404 skb = alloc_can_skb(dev, &frame); 405 if (!skb) { 406 stats->rx_dropped++; 407 return -ENOMEM; 408 } 409 410 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 411 412 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); 413 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | 414 (flags << 16); 415 416 if (flags & IF_ARB_MSGXTD) 417 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; 418 else 419 frame->can_id = (val >> 18) & CAN_SFF_MASK; 420 421 if (flags & IF_ARB_TRANSMIT) 422 frame->can_id |= CAN_RTR_FLAG; 423 else { 424 for (i = 0; i < frame->can_dlc; i += 2) { 425 data = priv->read_reg(priv, 426 C_CAN_IFACE(DATA1_REG, iface) + i / 2); 427 frame->data[i] = data; 428 frame->data[i + 1] = data >> 8; 429 } 430 } 431 432 netif_receive_skb(skb); 433 434 stats->rx_packets++; 435 stats->rx_bytes += frame->can_dlc; 436 return 0; 437} 438 439static void c_can_setup_receive_object(struct net_device *dev, int iface, 440 int objno, unsigned int mask, 441 unsigned int id, unsigned int mcont) 442{ 443 struct c_can_priv *priv = netdev_priv(dev); 444 445 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), 446 IFX_WRITE_LOW_16BIT(mask)); 447 448 /* According to C_CAN documentation, the reserved bit 449 * in IFx_MASK2 register is fixed 1 450 */ 451 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), 452 IFX_WRITE_HIGH_16BIT(mask) | BIT(13)); 453 454 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 455 IFX_WRITE_LOW_16BIT(id)); 456 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 457 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); 458 459 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 460 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 461 462 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 463 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 464} 465 466static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) 467{ 468 struct c_can_priv *priv = netdev_priv(dev); 469 470 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 471 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 472 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 473 474 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); 475 476 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 477 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 478} 479 480static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 481{ 482 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 483 484 /* 485 * as transmission request register's bit n-1 corresponds to 486 * message object n, we need to handle the same properly. 487 */ 488 if (val & (1 << (objno - 1))) 489 return 1; 490 491 return 0; 492} 493 494static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 495 struct net_device *dev) 496{ 497 u32 msg_obj_no; 498 struct c_can_priv *priv = netdev_priv(dev); 499 struct can_frame *frame = (struct can_frame *)skb->data; 500 501 if (can_dropped_invalid_skb(dev, skb)) 502 return NETDEV_TX_OK; 503 504 spin_lock_bh(&priv->xmit_lock); 505 msg_obj_no = get_tx_next_msg_obj(priv); 506 507 /* prepare message object for transmission */ 508 c_can_write_msg_object(dev, IF_TX, frame, msg_obj_no); 509 priv->dlc[msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST] = frame->can_dlc; 510 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 511 512 /* 513 * we have to stop the queue in case of a wrap around or 514 * if the next TX message object is still in use 515 */ 516 priv->tx_next++; 517 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 518 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 519 netif_stop_queue(dev); 520 spin_unlock_bh(&priv->xmit_lock); 521 522 return NETDEV_TX_OK; 523} 524 525static int c_can_wait_for_ctrl_init(struct net_device *dev, 526 struct c_can_priv *priv, u32 init) 527{ 528 int retry = 0; 529 530 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 531 udelay(10); 532 if (retry++ > 1000) { 533 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 534 return -EIO; 535 } 536 } 537 return 0; 538} 539 540static int c_can_set_bittiming(struct net_device *dev) 541{ 542 unsigned int reg_btr, reg_brpe, ctrl_save; 543 u8 brp, brpe, sjw, tseg1, tseg2; 544 u32 ten_bit_brp; 545 struct c_can_priv *priv = netdev_priv(dev); 546 const struct can_bittiming *bt = &priv->can.bittiming; 547 int res; 548 549 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 550 ten_bit_brp = bt->brp - 1; 551 brp = ten_bit_brp & BTR_BRP_MASK; 552 brpe = ten_bit_brp >> 6; 553 554 sjw = bt->sjw - 1; 555 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 556 tseg2 = bt->phase_seg2 - 1; 557 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 558 (tseg2 << BTR_TSEG2_SHIFT); 559 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 560 561 netdev_info(dev, 562 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 563 564 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 565 ctrl_save &= ~CONTROL_INIT; 566 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 567 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 568 if (res) 569 return res; 570 571 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 572 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 573 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 574 575 return c_can_wait_for_ctrl_init(dev, priv, 0); 576} 577 578/* 579 * Configure C_CAN message objects for Tx and Rx purposes: 580 * C_CAN provides a total of 32 message objects that can be configured 581 * either for Tx or Rx purposes. Here the first 16 message objects are used as 582 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 583 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 584 * See user guide document for further details on configuring message 585 * objects. 586 */ 587static void c_can_configure_msg_objects(struct net_device *dev) 588{ 589 int i; 590 591 /* first invalidate all message objects */ 592 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 593 c_can_inval_msg_object(dev, IF_RX, i); 594 595 /* setup receive message objects */ 596 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 597 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, 598 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); 599 600 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 601 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); 602} 603 604/* 605 * Configure C_CAN chip: 606 * - enable/disable auto-retransmission 607 * - set operating mode 608 * - configure message objects 609 */ 610static int c_can_chip_config(struct net_device *dev) 611{ 612 struct c_can_priv *priv = netdev_priv(dev); 613 614 /* enable automatic retransmission */ 615 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); 616 617 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 618 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 619 /* loopback + silent mode : useful for hot self-test */ 620 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 621 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); 622 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 623 /* loopback mode : useful for self-test function */ 624 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 625 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 626 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 627 /* silent mode : bus-monitoring mode */ 628 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 629 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 630 } 631 632 /* configure message objects */ 633 c_can_configure_msg_objects(dev); 634 635 /* set a `lec` value so that we can check for updates later */ 636 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 637 638 /* set bittiming params */ 639 return c_can_set_bittiming(dev); 640} 641 642static int c_can_start(struct net_device *dev) 643{ 644 struct c_can_priv *priv = netdev_priv(dev); 645 int err; 646 647 /* basic c_can configuration */ 648 err = c_can_chip_config(dev); 649 if (err) 650 return err; 651 652 priv->can.state = CAN_STATE_ERROR_ACTIVE; 653 654 /* reset tx helper pointers */ 655 priv->tx_next = priv->tx_echo = 0; 656 657 return 0; 658} 659 660static void c_can_stop(struct net_device *dev) 661{ 662 struct c_can_priv *priv = netdev_priv(dev); 663 664 /* disable all interrupts */ 665 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 666 667 /* set the state as STOPPED */ 668 priv->can.state = CAN_STATE_STOPPED; 669} 670 671static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 672{ 673 struct c_can_priv *priv = netdev_priv(dev); 674 int err; 675 676 switch (mode) { 677 case CAN_MODE_START: 678 err = c_can_start(dev); 679 if (err) 680 return err; 681 netif_wake_queue(dev); 682 /* enable status change, error and module interrupts */ 683 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 684 break; 685 default: 686 return -EOPNOTSUPP; 687 } 688 689 return 0; 690} 691 692static int __c_can_get_berr_counter(const struct net_device *dev, 693 struct can_berr_counter *bec) 694{ 695 unsigned int reg_err_counter; 696 struct c_can_priv *priv = netdev_priv(dev); 697 698 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 699 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 700 ERR_CNT_REC_SHIFT; 701 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 702 703 return 0; 704} 705 706static int c_can_get_berr_counter(const struct net_device *dev, 707 struct can_berr_counter *bec) 708{ 709 struct c_can_priv *priv = netdev_priv(dev); 710 int err; 711 712 c_can_pm_runtime_get_sync(priv); 713 err = __c_can_get_berr_counter(dev, bec); 714 c_can_pm_runtime_put_sync(priv); 715 716 return err; 717} 718 719/* 720 * priv->tx_echo holds the number of the oldest can_frame put for 721 * transmission into the hardware, but not yet ACKed by the CAN tx 722 * complete IRQ. 723 * 724 * We iterate from priv->tx_echo to priv->tx_next and check if the 725 * packet has been transmitted, echo it back to the CAN framework. 726 * If we discover a not yet transmitted packet, stop looking for more. 727 */ 728static void c_can_do_tx(struct net_device *dev) 729{ 730 struct c_can_priv *priv = netdev_priv(dev); 731 struct net_device_stats *stats = &dev->stats; 732 u32 val, obj, pkts = 0, bytes = 0; 733 734 spin_lock_bh(&priv->xmit_lock); 735 736 for (; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 737 obj = get_tx_echo_msg_obj(priv->tx_echo); 738 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 739 740 if (val & (1 << (obj - 1))) 741 break; 742 743 can_get_echo_skb(dev, obj - C_CAN_MSG_OBJ_TX_FIRST); 744 bytes += priv->dlc[obj - C_CAN_MSG_OBJ_TX_FIRST]; 745 pkts++; 746 c_can_inval_msg_object(dev, IF_TX, obj); 747 } 748 749 /* restart queue if wrap-up or if queue stalled on last pkt */ 750 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 751 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) 752 netif_wake_queue(dev); 753 754 spin_unlock_bh(&priv->xmit_lock); 755 756 if (pkts) { 757 stats->tx_bytes += bytes; 758 stats->tx_packets += pkts; 759 can_led_event(dev, CAN_LED_EVENT_TX); 760 } 761} 762 763/* 764 * If we have a gap in the pending bits, that means we either 765 * raced with the hardware or failed to readout all upper 766 * objects in the last run due to quota limit. 767 */ 768static u32 c_can_adjust_pending(u32 pend) 769{ 770 u32 weight, lasts; 771 772 if (pend == RECEIVE_OBJECT_BITS) 773 return pend; 774 775 /* 776 * If the last set bit is larger than the number of pending 777 * bits we have a gap. 778 */ 779 weight = hweight32(pend); 780 lasts = fls(pend); 781 782 /* If the bits are linear, nothing to do */ 783 if (lasts == weight) 784 return pend; 785 786 /* 787 * Find the first set bit after the gap. We walk backwards 788 * from the last set bit. 789 */ 790 for (lasts--; pend & (1 << (lasts - 1)); lasts--); 791 792 return pend & ~((1 << lasts) - 1); 793} 794 795static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 796 u32 pend, int quota) 797{ 798 u32 pkts = 0, ctrl, obj, mcmd; 799 800 while ((obj = ffs(pend)) && quota > 0) { 801 pend &= ~BIT(obj - 1); 802 803 mcmd = obj < C_CAN_MSG_RX_LOW_LAST ? 804 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 805 806 c_can_object_get(dev, IF_RX, obj, mcmd); 807 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 808 809 if (ctrl & IF_MCONT_MSGLST) { 810 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); 811 812 pkts += n; 813 quota -= n; 814 continue; 815 } 816 817 /* 818 * This really should not happen, but this covers some 819 * odd HW behaviour. Do not remove that unless you 820 * want to brick your machine. 821 */ 822 if (!(ctrl & IF_MCONT_NEWDAT)) 823 continue; 824 825 /* read the data from the message object */ 826 c_can_read_msg_object(dev, IF_RX, ctrl); 827 828 if (obj == C_CAN_MSG_RX_LOW_LAST) 829 /* activate all lower message objects */ 830 c_can_activate_all_lower_rx_msg_obj(dev, IF_RX, ctrl); 831 832 pkts++; 833 quota--; 834 } 835 836 return pkts; 837} 838 839/* 840 * theory of operation: 841 * 842 * c_can core saves a received CAN message into the first free message 843 * object it finds free (starting with the lowest). Bits NEWDAT and 844 * INTPND are set for this message object indicating that a new message 845 * has arrived. To work-around this issue, we keep two groups of message 846 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 847 * 848 * To ensure in-order frame reception we use the following 849 * approach while re-activating a message object to receive further 850 * frames: 851 * - if the current message object number is lower than 852 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 853 * the INTPND bit. 854 * - if the current message object number is equal to 855 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 856 * receive message objects. 857 * - if the current message object number is greater than 858 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 859 * only this message object. 860 */ 861static int c_can_do_rx_poll(struct net_device *dev, int quota) 862{ 863 struct c_can_priv *priv = netdev_priv(dev); 864 u32 pkts = 0, pend = 0, toread, n; 865 866 /* 867 * It is faster to read only one 16bit register. This is only possible 868 * for a maximum number of 16 objects. 869 */ 870 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, 871 "Implementation does not support more message objects than 16"); 872 873 while (quota > 0) { 874 if (!pend) { 875 pend = priv->read_reg(priv, C_CAN_INTPND1_REG); 876 if (!pend) 877 break; 878 /* 879 * If the pending field has a gap, handle the 880 * bits above the gap first. 881 */ 882 toread = c_can_adjust_pending(pend); 883 } else { 884 toread = pend; 885 } 886 /* Remove the bits from pend */ 887 pend &= ~toread; 888 /* Read the objects */ 889 n = c_can_read_objects(dev, priv, toread, quota); 890 pkts += n; 891 quota -= n; 892 } 893 894 if (pkts) 895 can_led_event(dev, CAN_LED_EVENT_RX); 896 897 return pkts; 898} 899 900static inline int c_can_has_and_handle_berr(struct c_can_priv *priv) 901{ 902 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 903 (priv->current_status & LEC_UNUSED); 904} 905 906static int c_can_handle_state_change(struct net_device *dev, 907 enum c_can_bus_error_types error_type) 908{ 909 unsigned int reg_err_counter; 910 unsigned int rx_err_passive; 911 struct c_can_priv *priv = netdev_priv(dev); 912 struct net_device_stats *stats = &dev->stats; 913 struct can_frame *cf; 914 struct sk_buff *skb; 915 struct can_berr_counter bec; 916 917 /* propagate the error condition to the CAN stack */ 918 skb = alloc_can_err_skb(dev, &cf); 919 if (unlikely(!skb)) 920 return 0; 921 922 __c_can_get_berr_counter(dev, &bec); 923 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 924 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 925 ERR_CNT_RP_SHIFT; 926 927 switch (error_type) { 928 case C_CAN_ERROR_WARNING: 929 /* error warning state */ 930 priv->can.can_stats.error_warning++; 931 priv->can.state = CAN_STATE_ERROR_WARNING; 932 cf->can_id |= CAN_ERR_CRTL; 933 cf->data[1] = (bec.txerr > bec.rxerr) ? 934 CAN_ERR_CRTL_TX_WARNING : 935 CAN_ERR_CRTL_RX_WARNING; 936 cf->data[6] = bec.txerr; 937 cf->data[7] = bec.rxerr; 938 939 break; 940 case C_CAN_ERROR_PASSIVE: 941 /* error passive state */ 942 priv->can.can_stats.error_passive++; 943 priv->can.state = CAN_STATE_ERROR_PASSIVE; 944 cf->can_id |= CAN_ERR_CRTL; 945 if (rx_err_passive) 946 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 947 if (bec.txerr > 127) 948 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 949 950 cf->data[6] = bec.txerr; 951 cf->data[7] = bec.rxerr; 952 break; 953 case C_CAN_BUS_OFF: 954 /* bus-off state */ 955 priv->can.state = CAN_STATE_BUS_OFF; 956 cf->can_id |= CAN_ERR_BUSOFF; 957 /* 958 * disable all interrupts in bus-off mode to ensure that 959 * the CPU is not hogged down 960 */ 961 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 962 can_bus_off(dev); 963 break; 964 default: 965 break; 966 } 967 968 netif_receive_skb(skb); 969 stats->rx_packets++; 970 stats->rx_bytes += cf->can_dlc; 971 972 return 1; 973} 974 975static int c_can_handle_bus_err(struct net_device *dev, 976 enum c_can_lec_type lec_type) 977{ 978 struct c_can_priv *priv = netdev_priv(dev); 979 struct net_device_stats *stats = &dev->stats; 980 struct can_frame *cf; 981 struct sk_buff *skb; 982 983 /* 984 * early exit if no lec update or no error. 985 * no lec update means that no CAN bus event has been detected 986 * since CPU wrote 0x7 value to status reg. 987 */ 988 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 989 return 0; 990 991 /* propagate the error condition to the CAN stack */ 992 skb = alloc_can_err_skb(dev, &cf); 993 if (unlikely(!skb)) 994 return 0; 995 996 /* 997 * check for 'last error code' which tells us the 998 * type of the last error to occur on the CAN bus 999 */ 1000 1001 /* common for all type of bus errors */ 1002 priv->can.can_stats.bus_error++; 1003 stats->rx_errors++; 1004 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1005 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 1006 1007 switch (lec_type) { 1008 case LEC_STUFF_ERROR: 1009 netdev_dbg(dev, "stuff error\n"); 1010 cf->data[2] |= CAN_ERR_PROT_STUFF; 1011 break; 1012 case LEC_FORM_ERROR: 1013 netdev_dbg(dev, "form error\n"); 1014 cf->data[2] |= CAN_ERR_PROT_FORM; 1015 break; 1016 case LEC_ACK_ERROR: 1017 netdev_dbg(dev, "ack error\n"); 1018 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 1019 CAN_ERR_PROT_LOC_ACK_DEL); 1020 break; 1021 case LEC_BIT1_ERROR: 1022 netdev_dbg(dev, "bit1 error\n"); 1023 cf->data[2] |= CAN_ERR_PROT_BIT1; 1024 break; 1025 case LEC_BIT0_ERROR: 1026 netdev_dbg(dev, "bit0 error\n"); 1027 cf->data[2] |= CAN_ERR_PROT_BIT0; 1028 break; 1029 case LEC_CRC_ERROR: 1030 netdev_dbg(dev, "CRC error\n"); 1031 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 1032 CAN_ERR_PROT_LOC_CRC_DEL); 1033 break; 1034 default: 1035 break; 1036 } 1037 1038 /* set a `lec` value so that we can check for updates later */ 1039 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1040 1041 netif_receive_skb(skb); 1042 stats->rx_packets++; 1043 stats->rx_bytes += cf->can_dlc; 1044 1045 return 1; 1046} 1047 1048static int c_can_poll(struct napi_struct *napi, int quota) 1049{ 1050 u16 irqstatus; 1051 int lec_type = 0; 1052 int work_done = 0; 1053 struct net_device *dev = napi->dev; 1054 struct c_can_priv *priv = netdev_priv(dev); 1055 1056 irqstatus = priv->irqstatus; 1057 if (!irqstatus) 1058 goto end; 1059 1060 /* status events have the highest priority */ 1061 if (irqstatus == STATUS_INTERRUPT) { 1062 priv->current_status = priv->read_reg(priv, 1063 C_CAN_STS_REG); 1064 1065 /* handle Tx/Rx events */ 1066 if (priv->current_status & STATUS_TXOK) 1067 priv->write_reg(priv, C_CAN_STS_REG, 1068 priv->current_status & ~STATUS_TXOK); 1069 1070 if (priv->current_status & STATUS_RXOK) 1071 priv->write_reg(priv, C_CAN_STS_REG, 1072 priv->current_status & ~STATUS_RXOK); 1073 1074 /* handle state changes */ 1075 if ((priv->current_status & STATUS_EWARN) && 1076 (!(priv->last_status & STATUS_EWARN))) { 1077 netdev_dbg(dev, "entered error warning state\n"); 1078 work_done += c_can_handle_state_change(dev, 1079 C_CAN_ERROR_WARNING); 1080 } 1081 if ((priv->current_status & STATUS_EPASS) && 1082 (!(priv->last_status & STATUS_EPASS))) { 1083 netdev_dbg(dev, "entered error passive state\n"); 1084 work_done += c_can_handle_state_change(dev, 1085 C_CAN_ERROR_PASSIVE); 1086 } 1087 if ((priv->current_status & STATUS_BOFF) && 1088 (!(priv->last_status & STATUS_BOFF))) { 1089 netdev_dbg(dev, "entered bus off state\n"); 1090 work_done += c_can_handle_state_change(dev, 1091 C_CAN_BUS_OFF); 1092 } 1093 1094 /* handle bus recovery events */ 1095 if ((!(priv->current_status & STATUS_BOFF)) && 1096 (priv->last_status & STATUS_BOFF)) { 1097 netdev_dbg(dev, "left bus off state\n"); 1098 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1099 } 1100 if ((!(priv->current_status & STATUS_EPASS)) && 1101 (priv->last_status & STATUS_EPASS)) { 1102 netdev_dbg(dev, "left error passive state\n"); 1103 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1104 } 1105 1106 priv->last_status = priv->current_status; 1107 1108 /* handle lec errors on the bus */ 1109 lec_type = c_can_has_and_handle_berr(priv); 1110 if (lec_type) 1111 work_done += c_can_handle_bus_err(dev, lec_type); 1112 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && 1113 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { 1114 /* handle events corresponding to receive message objects */ 1115 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1116 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && 1117 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { 1118 /* handle events corresponding to transmit message objects */ 1119 c_can_do_tx(dev); 1120 } 1121 1122end: 1123 if (work_done < quota) { 1124 napi_complete(napi); 1125 /* enable all IRQs */ 1126 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1127 } 1128 1129 return work_done; 1130} 1131 1132static irqreturn_t c_can_isr(int irq, void *dev_id) 1133{ 1134 struct net_device *dev = (struct net_device *)dev_id; 1135 struct c_can_priv *priv = netdev_priv(dev); 1136 1137 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); 1138 if (!priv->irqstatus) 1139 return IRQ_NONE; 1140 1141 /* disable all interrupts and schedule the NAPI */ 1142 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1143 napi_schedule(&priv->napi); 1144 1145 return IRQ_HANDLED; 1146} 1147 1148static int c_can_open(struct net_device *dev) 1149{ 1150 int err; 1151 struct c_can_priv *priv = netdev_priv(dev); 1152 1153 c_can_pm_runtime_get_sync(priv); 1154 c_can_reset_ram(priv, true); 1155 1156 /* open the can device */ 1157 err = open_candev(dev); 1158 if (err) { 1159 netdev_err(dev, "failed to open can device\n"); 1160 goto exit_open_fail; 1161 } 1162 1163 /* register interrupt handler */ 1164 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1165 dev); 1166 if (err < 0) { 1167 netdev_err(dev, "failed to request interrupt\n"); 1168 goto exit_irq_fail; 1169 } 1170 1171 /* start the c_can controller */ 1172 err = c_can_start(dev); 1173 if (err) 1174 goto exit_start_fail; 1175 1176 can_led_event(dev, CAN_LED_EVENT_OPEN); 1177 1178 napi_enable(&priv->napi); 1179 /* enable status change, error and module interrupts */ 1180 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1181 netif_start_queue(dev); 1182 1183 return 0; 1184 1185exit_start_fail: 1186 free_irq(dev->irq, dev); 1187exit_irq_fail: 1188 close_candev(dev); 1189exit_open_fail: 1190 c_can_reset_ram(priv, false); 1191 c_can_pm_runtime_put_sync(priv); 1192 return err; 1193} 1194 1195static int c_can_close(struct net_device *dev) 1196{ 1197 struct c_can_priv *priv = netdev_priv(dev); 1198 1199 netif_stop_queue(dev); 1200 napi_disable(&priv->napi); 1201 c_can_stop(dev); 1202 free_irq(dev->irq, dev); 1203 close_candev(dev); 1204 1205 c_can_reset_ram(priv, false); 1206 c_can_pm_runtime_put_sync(priv); 1207 1208 can_led_event(dev, CAN_LED_EVENT_STOP); 1209 1210 return 0; 1211} 1212 1213struct net_device *alloc_c_can_dev(void) 1214{ 1215 struct net_device *dev; 1216 struct c_can_priv *priv; 1217 1218 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1219 if (!dev) 1220 return NULL; 1221 1222 priv = netdev_priv(dev); 1223 spin_lock_init(&priv->xmit_lock); 1224 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1225 1226 priv->dev = dev; 1227 priv->can.bittiming_const = &c_can_bittiming_const; 1228 priv->can.do_set_mode = c_can_set_mode; 1229 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1230 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1231 CAN_CTRLMODE_LISTENONLY | 1232 CAN_CTRLMODE_BERR_REPORTING; 1233 1234 return dev; 1235} 1236EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1237 1238#ifdef CONFIG_PM 1239int c_can_power_down(struct net_device *dev) 1240{ 1241 u32 val; 1242 unsigned long time_out; 1243 struct c_can_priv *priv = netdev_priv(dev); 1244 1245 if (!(dev->flags & IFF_UP)) 1246 return 0; 1247 1248 WARN_ON(priv->type != BOSCH_D_CAN); 1249 1250 /* set PDR value so the device goes to power down mode */ 1251 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1252 val |= CONTROL_EX_PDR; 1253 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1254 1255 /* Wait for the PDA bit to get set */ 1256 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1257 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1258 time_after(time_out, jiffies)) 1259 cpu_relax(); 1260 1261 if (time_after(jiffies, time_out)) 1262 return -ETIMEDOUT; 1263 1264 c_can_stop(dev); 1265 1266 c_can_reset_ram(priv, false); 1267 c_can_pm_runtime_put_sync(priv); 1268 1269 return 0; 1270} 1271EXPORT_SYMBOL_GPL(c_can_power_down); 1272 1273int c_can_power_up(struct net_device *dev) 1274{ 1275 u32 val; 1276 unsigned long time_out; 1277 struct c_can_priv *priv = netdev_priv(dev); 1278 int ret; 1279 1280 if (!(dev->flags & IFF_UP)) 1281 return 0; 1282 1283 WARN_ON(priv->type != BOSCH_D_CAN); 1284 1285 c_can_pm_runtime_get_sync(priv); 1286 c_can_reset_ram(priv, true); 1287 1288 /* Clear PDR and INIT bits */ 1289 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1290 val &= ~CONTROL_EX_PDR; 1291 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1292 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1293 val &= ~CONTROL_INIT; 1294 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1295 1296 /* Wait for the PDA bit to get clear */ 1297 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1298 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1299 time_after(time_out, jiffies)) 1300 cpu_relax(); 1301 1302 if (time_after(jiffies, time_out)) 1303 return -ETIMEDOUT; 1304 1305 ret = c_can_start(dev); 1306 if (!ret) 1307 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1308 1309 return ret; 1310} 1311EXPORT_SYMBOL_GPL(c_can_power_up); 1312#endif 1313 1314void free_c_can_dev(struct net_device *dev) 1315{ 1316 struct c_can_priv *priv = netdev_priv(dev); 1317 1318 netif_napi_del(&priv->napi); 1319 free_candev(dev); 1320} 1321EXPORT_SYMBOL_GPL(free_c_can_dev); 1322 1323static const struct net_device_ops c_can_netdev_ops = { 1324 .ndo_open = c_can_open, 1325 .ndo_stop = c_can_close, 1326 .ndo_start_xmit = c_can_start_xmit, 1327 .ndo_change_mtu = can_change_mtu, 1328}; 1329 1330int register_c_can_dev(struct net_device *dev) 1331{ 1332 struct c_can_priv *priv = netdev_priv(dev); 1333 int err; 1334 1335 c_can_pm_runtime_enable(priv); 1336 1337 dev->flags |= IFF_ECHO; /* we support local echo */ 1338 dev->netdev_ops = &c_can_netdev_ops; 1339 1340 err = register_candev(dev); 1341 if (err) 1342 c_can_pm_runtime_disable(priv); 1343 else 1344 devm_can_led_init(dev); 1345 1346 return err; 1347} 1348EXPORT_SYMBOL_GPL(register_c_can_dev); 1349 1350void unregister_c_can_dev(struct net_device *dev) 1351{ 1352 struct c_can_priv *priv = netdev_priv(dev); 1353 1354 unregister_candev(dev); 1355 1356 c_can_pm_runtime_disable(priv); 1357} 1358EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1359 1360MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1361MODULE_LICENSE("GPL v2"); 1362MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1363