c_can.c revision c0a9f4d396c9d3cf34d21e318a422f9461d93042
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42#include <linux/can/led.h> 43 44#include "c_can.h" 45 46/* Number of interface registers */ 47#define IF_ENUM_REG_LEN 11 48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 49 50/* control extension register D_CAN specific */ 51#define CONTROL_EX_PDR BIT(8) 52 53/* control register */ 54#define CONTROL_TEST BIT(7) 55#define CONTROL_CCE BIT(6) 56#define CONTROL_DISABLE_AR BIT(5) 57#define CONTROL_ENABLE_AR (0 << 5) 58#define CONTROL_EIE BIT(3) 59#define CONTROL_SIE BIT(2) 60#define CONTROL_IE BIT(1) 61#define CONTROL_INIT BIT(0) 62 63/* test register */ 64#define TEST_RX BIT(7) 65#define TEST_TX1 BIT(6) 66#define TEST_TX2 BIT(5) 67#define TEST_LBACK BIT(4) 68#define TEST_SILENT BIT(3) 69#define TEST_BASIC BIT(2) 70 71/* status register */ 72#define STATUS_PDA BIT(10) 73#define STATUS_BOFF BIT(7) 74#define STATUS_EWARN BIT(6) 75#define STATUS_EPASS BIT(5) 76#define STATUS_RXOK BIT(4) 77#define STATUS_TXOK BIT(3) 78 79/* error counter register */ 80#define ERR_CNT_TEC_MASK 0xff 81#define ERR_CNT_TEC_SHIFT 0 82#define ERR_CNT_REC_SHIFT 8 83#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 84#define ERR_CNT_RP_SHIFT 15 85#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 86 87/* bit-timing register */ 88#define BTR_BRP_MASK 0x3f 89#define BTR_BRP_SHIFT 0 90#define BTR_SJW_SHIFT 6 91#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 92#define BTR_TSEG1_SHIFT 8 93#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 94#define BTR_TSEG2_SHIFT 12 95#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 96 97/* brp extension register */ 98#define BRP_EXT_BRPE_MASK 0x0f 99#define BRP_EXT_BRPE_SHIFT 0 100 101/* IFx command request */ 102#define IF_COMR_BUSY BIT(15) 103 104/* IFx command mask */ 105#define IF_COMM_WR BIT(7) 106#define IF_COMM_MASK BIT(6) 107#define IF_COMM_ARB BIT(5) 108#define IF_COMM_CONTROL BIT(4) 109#define IF_COMM_CLR_INT_PND BIT(3) 110#define IF_COMM_TXRQST BIT(2) 111#define IF_COMM_DATAA BIT(1) 112#define IF_COMM_DATAB BIT(0) 113#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ 114 IF_COMM_CONTROL | IF_COMM_TXRQST | \ 115 IF_COMM_DATAA | IF_COMM_DATAB) 116 117/* For the low buffers we clear the interrupt bit, but keep newdat */ 118#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 119 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 120 IF_COMM_DATAA | IF_COMM_DATAB) 121 122/* For the high buffers we clear the interrupt bit and newdat */ 123#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_TXRQST) 124 125/* IFx arbitration */ 126#define IF_ARB_MSGVAL BIT(15) 127#define IF_ARB_MSGXTD BIT(14) 128#define IF_ARB_TRANSMIT BIT(13) 129 130/* IFx message control */ 131#define IF_MCONT_NEWDAT BIT(15) 132#define IF_MCONT_MSGLST BIT(14) 133#define IF_MCONT_INTPND BIT(13) 134#define IF_MCONT_UMASK BIT(12) 135#define IF_MCONT_TXIE BIT(11) 136#define IF_MCONT_RXIE BIT(10) 137#define IF_MCONT_RMTEN BIT(9) 138#define IF_MCONT_TXRQST BIT(8) 139#define IF_MCONT_EOB BIT(7) 140#define IF_MCONT_DLC_MASK 0xf 141 142/* 143 * Use IF1 for RX and IF2 for TX 144 */ 145#define IF_RX 0 146#define IF_TX 1 147 148/* 149 * IFx register masks: 150 * allow easy operation on 16-bit registers when the 151 * argument is 32-bit instead 152 */ 153#define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF) 154#define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16) 155 156/* message object split */ 157#define C_CAN_NO_OF_OBJECTS 32 158#define C_CAN_MSG_OBJ_RX_NUM 16 159#define C_CAN_MSG_OBJ_TX_NUM 16 160 161#define C_CAN_MSG_OBJ_RX_FIRST 1 162#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \ 163 C_CAN_MSG_OBJ_RX_NUM - 1) 164 165#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1) 166#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \ 167 C_CAN_MSG_OBJ_TX_NUM - 1) 168 169#define C_CAN_MSG_OBJ_RX_SPLIT 9 170#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1) 171 172#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1) 173#define RECEIVE_OBJECT_BITS 0x0000ffff 174 175/* status interrupt */ 176#define STATUS_INTERRUPT 0x8000 177 178/* global interrupt masks */ 179#define ENABLE_ALL_INTERRUPTS 1 180#define DISABLE_ALL_INTERRUPTS 0 181 182/* minimum timeout for checking BUSY status */ 183#define MIN_TIMEOUT_VALUE 6 184 185/* Wait for ~1 sec for INIT bit */ 186#define INIT_WAIT_MS 1000 187 188/* napi related */ 189#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 190 191/* c_can lec values */ 192enum c_can_lec_type { 193 LEC_NO_ERROR = 0, 194 LEC_STUFF_ERROR, 195 LEC_FORM_ERROR, 196 LEC_ACK_ERROR, 197 LEC_BIT1_ERROR, 198 LEC_BIT0_ERROR, 199 LEC_CRC_ERROR, 200 LEC_UNUSED, 201}; 202 203/* 204 * c_can error types: 205 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 206 */ 207enum c_can_bus_error_types { 208 C_CAN_NO_ERROR = 0, 209 C_CAN_BUS_OFF, 210 C_CAN_ERROR_WARNING, 211 C_CAN_ERROR_PASSIVE, 212}; 213 214static const struct can_bittiming_const c_can_bittiming_const = { 215 .name = KBUILD_MODNAME, 216 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 217 .tseg1_max = 16, 218 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 219 .tseg2_max = 8, 220 .sjw_max = 4, 221 .brp_min = 1, 222 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 223 .brp_inc = 1, 224}; 225 226static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 227{ 228 if (priv->device) 229 pm_runtime_enable(priv->device); 230} 231 232static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 233{ 234 if (priv->device) 235 pm_runtime_disable(priv->device); 236} 237 238static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 239{ 240 if (priv->device) 241 pm_runtime_get_sync(priv->device); 242} 243 244static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 245{ 246 if (priv->device) 247 pm_runtime_put_sync(priv->device); 248} 249 250static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 251{ 252 if (priv->raminit) 253 priv->raminit(priv, enable); 254} 255 256static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 257{ 258 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + 259 C_CAN_MSG_OBJ_TX_FIRST; 260} 261 262static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv) 263{ 264 return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) + 265 C_CAN_MSG_OBJ_TX_FIRST; 266} 267 268static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) 269{ 270 u32 val = priv->read_reg(priv, index); 271 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 272 return val; 273} 274 275static void c_can_enable_all_interrupts(struct c_can_priv *priv, 276 int enable) 277{ 278 unsigned int cntrl_save = priv->read_reg(priv, 279 C_CAN_CTRL_REG); 280 281 if (enable) 282 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 283 else 284 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); 285 286 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); 287} 288 289static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 290{ 291 int count = MIN_TIMEOUT_VALUE; 292 293 while (count && priv->read_reg(priv, 294 C_CAN_IFACE(COMREQ_REG, iface)) & 295 IF_COMR_BUSY) { 296 count--; 297 udelay(1); 298 } 299 300 if (!count) 301 return 1; 302 303 return 0; 304} 305 306static inline void c_can_object_get(struct net_device *dev, 307 int iface, int objno, int mask) 308{ 309 struct c_can_priv *priv = netdev_priv(dev); 310 311 /* 312 * As per specs, after writting the message object number in the 313 * IF command request register the transfer b/w interface 314 * register and message RAM must be complete in 6 CAN-CLK 315 * period. 316 */ 317 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 318 IFX_WRITE_LOW_16BIT(mask)); 319 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 320 IFX_WRITE_LOW_16BIT(objno)); 321 322 if (c_can_msg_obj_is_busy(priv, iface)) 323 netdev_err(dev, "timed out in object get\n"); 324} 325 326static inline void c_can_object_put(struct net_device *dev, 327 int iface, int objno, int mask) 328{ 329 struct c_can_priv *priv = netdev_priv(dev); 330 331 /* 332 * As per specs, after writting the message object number in the 333 * IF command request register the transfer b/w interface 334 * register and message RAM must be complete in 6 CAN-CLK 335 * period. 336 */ 337 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 338 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); 339 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 340 IFX_WRITE_LOW_16BIT(objno)); 341 342 if (c_can_msg_obj_is_busy(priv, iface)) 343 netdev_err(dev, "timed out in object put\n"); 344} 345 346static void c_can_write_msg_object(struct net_device *dev, 347 int iface, struct can_frame *frame, int objno) 348{ 349 int i; 350 u16 flags = 0; 351 unsigned int id; 352 struct c_can_priv *priv = netdev_priv(dev); 353 354 if (!(frame->can_id & CAN_RTR_FLAG)) 355 flags |= IF_ARB_TRANSMIT; 356 357 if (frame->can_id & CAN_EFF_FLAG) { 358 id = frame->can_id & CAN_EFF_MASK; 359 flags |= IF_ARB_MSGXTD; 360 } else 361 id = ((frame->can_id & CAN_SFF_MASK) << 18); 362 363 flags |= IF_ARB_MSGVAL; 364 365 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 366 IFX_WRITE_LOW_16BIT(id)); 367 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | 368 IFX_WRITE_HIGH_16BIT(id)); 369 370 for (i = 0; i < frame->can_dlc; i += 2) { 371 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 372 frame->data[i] | (frame->data[i + 1] << 8)); 373 } 374 375 /* enable interrupt for this message object */ 376 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 377 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | 378 frame->can_dlc); 379 c_can_object_put(dev, iface, objno, IF_COMM_ALL); 380} 381 382static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 383 int iface, 384 int ctrl_mask) 385{ 386 int i; 387 struct c_can_priv *priv = netdev_priv(dev); 388 389 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { 390 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 391 ctrl_mask & ~IF_MCONT_NEWDAT); 392 c_can_object_put(dev, iface, i, IF_COMM_CONTROL); 393 } 394} 395 396static int c_can_handle_lost_msg_obj(struct net_device *dev, 397 int iface, int objno, u32 ctrl) 398{ 399 struct net_device_stats *stats = &dev->stats; 400 struct c_can_priv *priv = netdev_priv(dev); 401 struct can_frame *frame; 402 struct sk_buff *skb; 403 404 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 405 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 406 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 407 408 /* create an error msg */ 409 skb = alloc_can_err_skb(dev, &frame); 410 if (unlikely(!skb)) 411 return 0; 412 413 frame->can_id |= CAN_ERR_CRTL; 414 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 415 stats->rx_errors++; 416 stats->rx_over_errors++; 417 418 netif_receive_skb(skb); 419 return 1; 420} 421 422static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) 423{ 424 u16 flags, data; 425 int i; 426 unsigned int val; 427 struct c_can_priv *priv = netdev_priv(dev); 428 struct net_device_stats *stats = &dev->stats; 429 struct sk_buff *skb; 430 struct can_frame *frame; 431 432 skb = alloc_can_skb(dev, &frame); 433 if (!skb) { 434 stats->rx_dropped++; 435 return -ENOMEM; 436 } 437 438 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 439 440 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); 441 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | 442 (flags << 16); 443 444 if (flags & IF_ARB_MSGXTD) 445 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; 446 else 447 frame->can_id = (val >> 18) & CAN_SFF_MASK; 448 449 if (flags & IF_ARB_TRANSMIT) 450 frame->can_id |= CAN_RTR_FLAG; 451 else { 452 for (i = 0; i < frame->can_dlc; i += 2) { 453 data = priv->read_reg(priv, 454 C_CAN_IFACE(DATA1_REG, iface) + i / 2); 455 frame->data[i] = data; 456 frame->data[i + 1] = data >> 8; 457 } 458 } 459 460 netif_receive_skb(skb); 461 462 stats->rx_packets++; 463 stats->rx_bytes += frame->can_dlc; 464 465 can_led_event(dev, CAN_LED_EVENT_RX); 466 467 return 0; 468} 469 470static void c_can_setup_receive_object(struct net_device *dev, int iface, 471 int objno, unsigned int mask, 472 unsigned int id, unsigned int mcont) 473{ 474 struct c_can_priv *priv = netdev_priv(dev); 475 476 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), 477 IFX_WRITE_LOW_16BIT(mask)); 478 479 /* According to C_CAN documentation, the reserved bit 480 * in IFx_MASK2 register is fixed 1 481 */ 482 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), 483 IFX_WRITE_HIGH_16BIT(mask) | BIT(13)); 484 485 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 486 IFX_WRITE_LOW_16BIT(id)); 487 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 488 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); 489 490 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 491 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 492 493 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 494 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 495} 496 497static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) 498{ 499 struct c_can_priv *priv = netdev_priv(dev); 500 501 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 502 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 503 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 504 505 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); 506 507 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 508 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 509} 510 511static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 512{ 513 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 514 515 /* 516 * as transmission request register's bit n-1 corresponds to 517 * message object n, we need to handle the same properly. 518 */ 519 if (val & (1 << (objno - 1))) 520 return 1; 521 522 return 0; 523} 524 525static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 526 struct net_device *dev) 527{ 528 u32 msg_obj_no; 529 struct c_can_priv *priv = netdev_priv(dev); 530 struct can_frame *frame = (struct can_frame *)skb->data; 531 532 if (can_dropped_invalid_skb(dev, skb)) 533 return NETDEV_TX_OK; 534 535 spin_lock_bh(&priv->xmit_lock); 536 msg_obj_no = get_tx_next_msg_obj(priv); 537 538 /* prepare message object for transmission */ 539 c_can_write_msg_object(dev, IF_TX, frame, msg_obj_no); 540 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 541 542 /* 543 * we have to stop the queue in case of a wrap around or 544 * if the next TX message object is still in use 545 */ 546 priv->tx_next++; 547 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 548 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 549 netif_stop_queue(dev); 550 spin_unlock_bh(&priv->xmit_lock); 551 552 return NETDEV_TX_OK; 553} 554 555static int c_can_wait_for_ctrl_init(struct net_device *dev, 556 struct c_can_priv *priv, u32 init) 557{ 558 int retry = 0; 559 560 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 561 udelay(10); 562 if (retry++ > 1000) { 563 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 564 return -EIO; 565 } 566 } 567 return 0; 568} 569 570static int c_can_set_bittiming(struct net_device *dev) 571{ 572 unsigned int reg_btr, reg_brpe, ctrl_save; 573 u8 brp, brpe, sjw, tseg1, tseg2; 574 u32 ten_bit_brp; 575 struct c_can_priv *priv = netdev_priv(dev); 576 const struct can_bittiming *bt = &priv->can.bittiming; 577 int res; 578 579 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 580 ten_bit_brp = bt->brp - 1; 581 brp = ten_bit_brp & BTR_BRP_MASK; 582 brpe = ten_bit_brp >> 6; 583 584 sjw = bt->sjw - 1; 585 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 586 tseg2 = bt->phase_seg2 - 1; 587 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 588 (tseg2 << BTR_TSEG2_SHIFT); 589 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 590 591 netdev_info(dev, 592 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 593 594 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 595 ctrl_save &= ~CONTROL_INIT; 596 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 597 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 598 if (res) 599 return res; 600 601 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 602 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 603 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 604 605 return c_can_wait_for_ctrl_init(dev, priv, 0); 606} 607 608/* 609 * Configure C_CAN message objects for Tx and Rx purposes: 610 * C_CAN provides a total of 32 message objects that can be configured 611 * either for Tx or Rx purposes. Here the first 16 message objects are used as 612 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 613 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 614 * See user guide document for further details on configuring message 615 * objects. 616 */ 617static void c_can_configure_msg_objects(struct net_device *dev) 618{ 619 int i; 620 621 /* first invalidate all message objects */ 622 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 623 c_can_inval_msg_object(dev, IF_RX, i); 624 625 /* setup receive message objects */ 626 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 627 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, 628 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); 629 630 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 631 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); 632} 633 634/* 635 * Configure C_CAN chip: 636 * - enable/disable auto-retransmission 637 * - set operating mode 638 * - configure message objects 639 */ 640static int c_can_chip_config(struct net_device *dev) 641{ 642 struct c_can_priv *priv = netdev_priv(dev); 643 644 /* enable automatic retransmission */ 645 priv->write_reg(priv, C_CAN_CTRL_REG, 646 CONTROL_ENABLE_AR); 647 648 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 649 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 650 /* loopback + silent mode : useful for hot self-test */ 651 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 652 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 653 priv->write_reg(priv, C_CAN_TEST_REG, 654 TEST_LBACK | TEST_SILENT); 655 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 656 /* loopback mode : useful for self-test function */ 657 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 658 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 659 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 660 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 661 /* silent mode : bus-monitoring mode */ 662 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 663 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 664 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 665 } else 666 /* normal mode*/ 667 priv->write_reg(priv, C_CAN_CTRL_REG, 668 CONTROL_EIE | CONTROL_SIE | CONTROL_IE); 669 670 /* configure message objects */ 671 c_can_configure_msg_objects(dev); 672 673 /* set a `lec` value so that we can check for updates later */ 674 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 675 676 /* set bittiming params */ 677 return c_can_set_bittiming(dev); 678} 679 680static int c_can_start(struct net_device *dev) 681{ 682 struct c_can_priv *priv = netdev_priv(dev); 683 int err; 684 685 /* basic c_can configuration */ 686 err = c_can_chip_config(dev); 687 if (err) 688 return err; 689 690 priv->can.state = CAN_STATE_ERROR_ACTIVE; 691 692 /* reset tx helper pointers */ 693 priv->tx_next = priv->tx_echo = 0; 694 695 /* enable status change, error and module interrupts */ 696 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 697 698 return 0; 699} 700 701static void c_can_stop(struct net_device *dev) 702{ 703 struct c_can_priv *priv = netdev_priv(dev); 704 705 /* disable all interrupts */ 706 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 707 708 /* set the state as STOPPED */ 709 priv->can.state = CAN_STATE_STOPPED; 710} 711 712static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 713{ 714 int err; 715 716 switch (mode) { 717 case CAN_MODE_START: 718 err = c_can_start(dev); 719 if (err) 720 return err; 721 netif_wake_queue(dev); 722 break; 723 default: 724 return -EOPNOTSUPP; 725 } 726 727 return 0; 728} 729 730static int __c_can_get_berr_counter(const struct net_device *dev, 731 struct can_berr_counter *bec) 732{ 733 unsigned int reg_err_counter; 734 struct c_can_priv *priv = netdev_priv(dev); 735 736 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 737 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 738 ERR_CNT_REC_SHIFT; 739 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 740 741 return 0; 742} 743 744static int c_can_get_berr_counter(const struct net_device *dev, 745 struct can_berr_counter *bec) 746{ 747 struct c_can_priv *priv = netdev_priv(dev); 748 int err; 749 750 c_can_pm_runtime_get_sync(priv); 751 err = __c_can_get_berr_counter(dev, bec); 752 c_can_pm_runtime_put_sync(priv); 753 754 return err; 755} 756 757/* 758 * theory of operation: 759 * 760 * priv->tx_echo holds the number of the oldest can_frame put for 761 * transmission into the hardware, but not yet ACKed by the CAN tx 762 * complete IRQ. 763 * 764 * We iterate from priv->tx_echo to priv->tx_next and check if the 765 * packet has been transmitted, echo it back to the CAN framework. 766 * If we discover a not yet transmitted packet, stop looking for more. 767 */ 768static void c_can_do_tx(struct net_device *dev) 769{ 770 u32 val; 771 u32 msg_obj_no; 772 struct c_can_priv *priv = netdev_priv(dev); 773 struct net_device_stats *stats = &dev->stats; 774 775 spin_lock_bh(&priv->xmit_lock); 776 777 for (; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 778 msg_obj_no = get_tx_echo_msg_obj(priv); 779 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 780 if (!(val & (1 << (msg_obj_no - 1)))) { 781 can_get_echo_skb(dev, 782 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 783 c_can_object_get(dev, IF_TX, msg_obj_no, IF_COMM_ALL); 784 stats->tx_bytes += priv->read_reg(priv, 785 C_CAN_IFACE(MSGCTRL_REG, IF_TX)) 786 & IF_MCONT_DLC_MASK; 787 stats->tx_packets++; 788 can_led_event(dev, CAN_LED_EVENT_TX); 789 c_can_inval_msg_object(dev, IF_TX, msg_obj_no); 790 } else { 791 break; 792 } 793 } 794 795 /* restart queue if wrap-up or if queue stalled on last pkt */ 796 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 797 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) 798 netif_wake_queue(dev); 799 800 spin_unlock_bh(&priv->xmit_lock); 801} 802 803/* 804 * If we have a gap in the pending bits, that means we either 805 * raced with the hardware or failed to readout all upper 806 * objects in the last run due to quota limit. 807 */ 808static u32 c_can_adjust_pending(u32 pend) 809{ 810 u32 weight, lasts; 811 812 if (pend == RECEIVE_OBJECT_BITS) 813 return pend; 814 815 /* 816 * If the last set bit is larger than the number of pending 817 * bits we have a gap. 818 */ 819 weight = hweight32(pend); 820 lasts = fls(pend); 821 822 /* If the bits are linear, nothing to do */ 823 if (lasts == weight) 824 return pend; 825 826 /* 827 * Find the first set bit after the gap. We walk backwards 828 * from the last set bit. 829 */ 830 for (lasts--; pend & (1 << (lasts - 1)); lasts--); 831 832 return pend & ~((1 << lasts) - 1); 833} 834 835static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 836 u32 pend, int quota) 837{ 838 u32 pkts = 0, ctrl, obj, mcmd; 839 840 while ((obj = ffs(pend)) && quota > 0) { 841 pend &= ~BIT(obj - 1); 842 843 mcmd = obj < C_CAN_MSG_RX_LOW_LAST ? 844 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 845 846 c_can_object_get(dev, IF_RX, obj, mcmd); 847 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 848 849 if (ctrl & IF_MCONT_MSGLST) { 850 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); 851 852 pkts += n; 853 quota -= n; 854 continue; 855 } 856 857 /* 858 * This really should not happen, but this covers some 859 * odd HW behaviour. Do not remove that unless you 860 * want to brick your machine. 861 */ 862 if (!(ctrl & IF_MCONT_NEWDAT)) 863 continue; 864 865 /* read the data from the message object */ 866 c_can_read_msg_object(dev, IF_RX, ctrl); 867 868 if (obj == C_CAN_MSG_RX_LOW_LAST) 869 /* activate all lower message objects */ 870 c_can_activate_all_lower_rx_msg_obj(dev, IF_RX, ctrl); 871 872 pkts++; 873 quota--; 874 } 875 876 return pkts; 877} 878 879/* 880 * theory of operation: 881 * 882 * c_can core saves a received CAN message into the first free message 883 * object it finds free (starting with the lowest). Bits NEWDAT and 884 * INTPND are set for this message object indicating that a new message 885 * has arrived. To work-around this issue, we keep two groups of message 886 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 887 * 888 * To ensure in-order frame reception we use the following 889 * approach while re-activating a message object to receive further 890 * frames: 891 * - if the current message object number is lower than 892 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 893 * the INTPND bit. 894 * - if the current message object number is equal to 895 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 896 * receive message objects. 897 * - if the current message object number is greater than 898 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 899 * only this message object. 900 */ 901static int c_can_do_rx_poll(struct net_device *dev, int quota) 902{ 903 struct c_can_priv *priv = netdev_priv(dev); 904 u32 pkts = 0, pend = 0, toread, n; 905 906 /* 907 * It is faster to read only one 16bit register. This is only possible 908 * for a maximum number of 16 objects. 909 */ 910 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, 911 "Implementation does not support more message objects than 16"); 912 913 while (quota > 0) { 914 if (!pend) { 915 pend = priv->read_reg(priv, C_CAN_INTPND1_REG); 916 if (!pend) 917 break; 918 /* 919 * If the pending field has a gap, handle the 920 * bits above the gap first. 921 */ 922 toread = c_can_adjust_pending(pend); 923 } else { 924 toread = pend; 925 } 926 /* Remove the bits from pend */ 927 pend &= ~toread; 928 /* Read the objects */ 929 n = c_can_read_objects(dev, priv, toread, quota); 930 pkts += n; 931 quota -= n; 932 } 933 return pkts; 934} 935 936static inline int c_can_has_and_handle_berr(struct c_can_priv *priv) 937{ 938 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 939 (priv->current_status & LEC_UNUSED); 940} 941 942static int c_can_handle_state_change(struct net_device *dev, 943 enum c_can_bus_error_types error_type) 944{ 945 unsigned int reg_err_counter; 946 unsigned int rx_err_passive; 947 struct c_can_priv *priv = netdev_priv(dev); 948 struct net_device_stats *stats = &dev->stats; 949 struct can_frame *cf; 950 struct sk_buff *skb; 951 struct can_berr_counter bec; 952 953 /* propagate the error condition to the CAN stack */ 954 skb = alloc_can_err_skb(dev, &cf); 955 if (unlikely(!skb)) 956 return 0; 957 958 __c_can_get_berr_counter(dev, &bec); 959 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 960 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 961 ERR_CNT_RP_SHIFT; 962 963 switch (error_type) { 964 case C_CAN_ERROR_WARNING: 965 /* error warning state */ 966 priv->can.can_stats.error_warning++; 967 priv->can.state = CAN_STATE_ERROR_WARNING; 968 cf->can_id |= CAN_ERR_CRTL; 969 cf->data[1] = (bec.txerr > bec.rxerr) ? 970 CAN_ERR_CRTL_TX_WARNING : 971 CAN_ERR_CRTL_RX_WARNING; 972 cf->data[6] = bec.txerr; 973 cf->data[7] = bec.rxerr; 974 975 break; 976 case C_CAN_ERROR_PASSIVE: 977 /* error passive state */ 978 priv->can.can_stats.error_passive++; 979 priv->can.state = CAN_STATE_ERROR_PASSIVE; 980 cf->can_id |= CAN_ERR_CRTL; 981 if (rx_err_passive) 982 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 983 if (bec.txerr > 127) 984 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 985 986 cf->data[6] = bec.txerr; 987 cf->data[7] = bec.rxerr; 988 break; 989 case C_CAN_BUS_OFF: 990 /* bus-off state */ 991 priv->can.state = CAN_STATE_BUS_OFF; 992 cf->can_id |= CAN_ERR_BUSOFF; 993 /* 994 * disable all interrupts in bus-off mode to ensure that 995 * the CPU is not hogged down 996 */ 997 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 998 can_bus_off(dev); 999 break; 1000 default: 1001 break; 1002 } 1003 1004 netif_receive_skb(skb); 1005 stats->rx_packets++; 1006 stats->rx_bytes += cf->can_dlc; 1007 1008 return 1; 1009} 1010 1011static int c_can_handle_bus_err(struct net_device *dev, 1012 enum c_can_lec_type lec_type) 1013{ 1014 struct c_can_priv *priv = netdev_priv(dev); 1015 struct net_device_stats *stats = &dev->stats; 1016 struct can_frame *cf; 1017 struct sk_buff *skb; 1018 1019 /* 1020 * early exit if no lec update or no error. 1021 * no lec update means that no CAN bus event has been detected 1022 * since CPU wrote 0x7 value to status reg. 1023 */ 1024 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 1025 return 0; 1026 1027 /* propagate the error condition to the CAN stack */ 1028 skb = alloc_can_err_skb(dev, &cf); 1029 if (unlikely(!skb)) 1030 return 0; 1031 1032 /* 1033 * check for 'last error code' which tells us the 1034 * type of the last error to occur on the CAN bus 1035 */ 1036 1037 /* common for all type of bus errors */ 1038 priv->can.can_stats.bus_error++; 1039 stats->rx_errors++; 1040 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1041 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 1042 1043 switch (lec_type) { 1044 case LEC_STUFF_ERROR: 1045 netdev_dbg(dev, "stuff error\n"); 1046 cf->data[2] |= CAN_ERR_PROT_STUFF; 1047 break; 1048 case LEC_FORM_ERROR: 1049 netdev_dbg(dev, "form error\n"); 1050 cf->data[2] |= CAN_ERR_PROT_FORM; 1051 break; 1052 case LEC_ACK_ERROR: 1053 netdev_dbg(dev, "ack error\n"); 1054 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 1055 CAN_ERR_PROT_LOC_ACK_DEL); 1056 break; 1057 case LEC_BIT1_ERROR: 1058 netdev_dbg(dev, "bit1 error\n"); 1059 cf->data[2] |= CAN_ERR_PROT_BIT1; 1060 break; 1061 case LEC_BIT0_ERROR: 1062 netdev_dbg(dev, "bit0 error\n"); 1063 cf->data[2] |= CAN_ERR_PROT_BIT0; 1064 break; 1065 case LEC_CRC_ERROR: 1066 netdev_dbg(dev, "CRC error\n"); 1067 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 1068 CAN_ERR_PROT_LOC_CRC_DEL); 1069 break; 1070 default: 1071 break; 1072 } 1073 1074 /* set a `lec` value so that we can check for updates later */ 1075 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1076 1077 netif_receive_skb(skb); 1078 stats->rx_packets++; 1079 stats->rx_bytes += cf->can_dlc; 1080 1081 return 1; 1082} 1083 1084static int c_can_poll(struct napi_struct *napi, int quota) 1085{ 1086 u16 irqstatus; 1087 int lec_type = 0; 1088 int work_done = 0; 1089 struct net_device *dev = napi->dev; 1090 struct c_can_priv *priv = netdev_priv(dev); 1091 1092 irqstatus = priv->irqstatus; 1093 if (!irqstatus) 1094 goto end; 1095 1096 /* status events have the highest priority */ 1097 if (irqstatus == STATUS_INTERRUPT) { 1098 priv->current_status = priv->read_reg(priv, 1099 C_CAN_STS_REG); 1100 1101 /* handle Tx/Rx events */ 1102 if (priv->current_status & STATUS_TXOK) 1103 priv->write_reg(priv, C_CAN_STS_REG, 1104 priv->current_status & ~STATUS_TXOK); 1105 1106 if (priv->current_status & STATUS_RXOK) 1107 priv->write_reg(priv, C_CAN_STS_REG, 1108 priv->current_status & ~STATUS_RXOK); 1109 1110 /* handle state changes */ 1111 if ((priv->current_status & STATUS_EWARN) && 1112 (!(priv->last_status & STATUS_EWARN))) { 1113 netdev_dbg(dev, "entered error warning state\n"); 1114 work_done += c_can_handle_state_change(dev, 1115 C_CAN_ERROR_WARNING); 1116 } 1117 if ((priv->current_status & STATUS_EPASS) && 1118 (!(priv->last_status & STATUS_EPASS))) { 1119 netdev_dbg(dev, "entered error passive state\n"); 1120 work_done += c_can_handle_state_change(dev, 1121 C_CAN_ERROR_PASSIVE); 1122 } 1123 if ((priv->current_status & STATUS_BOFF) && 1124 (!(priv->last_status & STATUS_BOFF))) { 1125 netdev_dbg(dev, "entered bus off state\n"); 1126 work_done += c_can_handle_state_change(dev, 1127 C_CAN_BUS_OFF); 1128 } 1129 1130 /* handle bus recovery events */ 1131 if ((!(priv->current_status & STATUS_BOFF)) && 1132 (priv->last_status & STATUS_BOFF)) { 1133 netdev_dbg(dev, "left bus off state\n"); 1134 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1135 } 1136 if ((!(priv->current_status & STATUS_EPASS)) && 1137 (priv->last_status & STATUS_EPASS)) { 1138 netdev_dbg(dev, "left error passive state\n"); 1139 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1140 } 1141 1142 priv->last_status = priv->current_status; 1143 1144 /* handle lec errors on the bus */ 1145 lec_type = c_can_has_and_handle_berr(priv); 1146 if (lec_type) 1147 work_done += c_can_handle_bus_err(dev, lec_type); 1148 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && 1149 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { 1150 /* handle events corresponding to receive message objects */ 1151 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1152 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && 1153 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { 1154 /* handle events corresponding to transmit message objects */ 1155 c_can_do_tx(dev); 1156 } 1157 1158end: 1159 if (work_done < quota) { 1160 napi_complete(napi); 1161 /* enable all IRQs */ 1162 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1163 } 1164 1165 return work_done; 1166} 1167 1168static irqreturn_t c_can_isr(int irq, void *dev_id) 1169{ 1170 struct net_device *dev = (struct net_device *)dev_id; 1171 struct c_can_priv *priv = netdev_priv(dev); 1172 1173 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); 1174 if (!priv->irqstatus) 1175 return IRQ_NONE; 1176 1177 /* disable all interrupts and schedule the NAPI */ 1178 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1179 napi_schedule(&priv->napi); 1180 1181 return IRQ_HANDLED; 1182} 1183 1184static int c_can_open(struct net_device *dev) 1185{ 1186 int err; 1187 struct c_can_priv *priv = netdev_priv(dev); 1188 1189 c_can_pm_runtime_get_sync(priv); 1190 c_can_reset_ram(priv, true); 1191 1192 /* open the can device */ 1193 err = open_candev(dev); 1194 if (err) { 1195 netdev_err(dev, "failed to open can device\n"); 1196 goto exit_open_fail; 1197 } 1198 1199 /* register interrupt handler */ 1200 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1201 dev); 1202 if (err < 0) { 1203 netdev_err(dev, "failed to request interrupt\n"); 1204 goto exit_irq_fail; 1205 } 1206 1207 /* start the c_can controller */ 1208 err = c_can_start(dev); 1209 if (err) 1210 goto exit_start_fail; 1211 1212 can_led_event(dev, CAN_LED_EVENT_OPEN); 1213 1214 napi_enable(&priv->napi); 1215 netif_start_queue(dev); 1216 1217 return 0; 1218 1219exit_start_fail: 1220 free_irq(dev->irq, dev); 1221exit_irq_fail: 1222 close_candev(dev); 1223exit_open_fail: 1224 c_can_reset_ram(priv, false); 1225 c_can_pm_runtime_put_sync(priv); 1226 return err; 1227} 1228 1229static int c_can_close(struct net_device *dev) 1230{ 1231 struct c_can_priv *priv = netdev_priv(dev); 1232 1233 netif_stop_queue(dev); 1234 napi_disable(&priv->napi); 1235 c_can_stop(dev); 1236 free_irq(dev->irq, dev); 1237 close_candev(dev); 1238 1239 c_can_reset_ram(priv, false); 1240 c_can_pm_runtime_put_sync(priv); 1241 1242 can_led_event(dev, CAN_LED_EVENT_STOP); 1243 1244 return 0; 1245} 1246 1247struct net_device *alloc_c_can_dev(void) 1248{ 1249 struct net_device *dev; 1250 struct c_can_priv *priv; 1251 1252 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1253 if (!dev) 1254 return NULL; 1255 1256 priv = netdev_priv(dev); 1257 spin_lock_init(&priv->xmit_lock); 1258 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1259 1260 priv->dev = dev; 1261 priv->can.bittiming_const = &c_can_bittiming_const; 1262 priv->can.do_set_mode = c_can_set_mode; 1263 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1264 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1265 CAN_CTRLMODE_LISTENONLY | 1266 CAN_CTRLMODE_BERR_REPORTING; 1267 1268 return dev; 1269} 1270EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1271 1272#ifdef CONFIG_PM 1273int c_can_power_down(struct net_device *dev) 1274{ 1275 u32 val; 1276 unsigned long time_out; 1277 struct c_can_priv *priv = netdev_priv(dev); 1278 1279 if (!(dev->flags & IFF_UP)) 1280 return 0; 1281 1282 WARN_ON(priv->type != BOSCH_D_CAN); 1283 1284 /* set PDR value so the device goes to power down mode */ 1285 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1286 val |= CONTROL_EX_PDR; 1287 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1288 1289 /* Wait for the PDA bit to get set */ 1290 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1291 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1292 time_after(time_out, jiffies)) 1293 cpu_relax(); 1294 1295 if (time_after(jiffies, time_out)) 1296 return -ETIMEDOUT; 1297 1298 c_can_stop(dev); 1299 1300 c_can_reset_ram(priv, false); 1301 c_can_pm_runtime_put_sync(priv); 1302 1303 return 0; 1304} 1305EXPORT_SYMBOL_GPL(c_can_power_down); 1306 1307int c_can_power_up(struct net_device *dev) 1308{ 1309 u32 val; 1310 unsigned long time_out; 1311 struct c_can_priv *priv = netdev_priv(dev); 1312 1313 if (!(dev->flags & IFF_UP)) 1314 return 0; 1315 1316 WARN_ON(priv->type != BOSCH_D_CAN); 1317 1318 c_can_pm_runtime_get_sync(priv); 1319 c_can_reset_ram(priv, true); 1320 1321 /* Clear PDR and INIT bits */ 1322 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1323 val &= ~CONTROL_EX_PDR; 1324 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1325 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1326 val &= ~CONTROL_INIT; 1327 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1328 1329 /* Wait for the PDA bit to get clear */ 1330 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1331 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1332 time_after(time_out, jiffies)) 1333 cpu_relax(); 1334 1335 if (time_after(jiffies, time_out)) 1336 return -ETIMEDOUT; 1337 1338 return c_can_start(dev); 1339} 1340EXPORT_SYMBOL_GPL(c_can_power_up); 1341#endif 1342 1343void free_c_can_dev(struct net_device *dev) 1344{ 1345 struct c_can_priv *priv = netdev_priv(dev); 1346 1347 netif_napi_del(&priv->napi); 1348 free_candev(dev); 1349} 1350EXPORT_SYMBOL_GPL(free_c_can_dev); 1351 1352static const struct net_device_ops c_can_netdev_ops = { 1353 .ndo_open = c_can_open, 1354 .ndo_stop = c_can_close, 1355 .ndo_start_xmit = c_can_start_xmit, 1356}; 1357 1358int register_c_can_dev(struct net_device *dev) 1359{ 1360 struct c_can_priv *priv = netdev_priv(dev); 1361 int err; 1362 1363 c_can_pm_runtime_enable(priv); 1364 1365 dev->flags |= IFF_ECHO; /* we support local echo */ 1366 dev->netdev_ops = &c_can_netdev_ops; 1367 1368 err = register_candev(dev); 1369 if (err) 1370 c_can_pm_runtime_disable(priv); 1371 else 1372 devm_can_led_init(dev); 1373 1374 return err; 1375} 1376EXPORT_SYMBOL_GPL(register_c_can_dev); 1377 1378void unregister_c_can_dev(struct net_device *dev) 1379{ 1380 struct c_can_priv *priv = netdev_priv(dev); 1381 1382 unregister_candev(dev); 1383 1384 c_can_pm_runtime_disable(priv); 1385} 1386EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1387 1388MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1389MODULE_LICENSE("GPL v2"); 1390MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1391