c_can.c revision ccbc5357db3098c57176945f677b0af37f5e87e6
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42#include <linux/can/led.h> 43 44#include "c_can.h" 45 46/* Number of interface registers */ 47#define IF_ENUM_REG_LEN 11 48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 49 50/* control extension register D_CAN specific */ 51#define CONTROL_EX_PDR BIT(8) 52 53/* control register */ 54#define CONTROL_TEST BIT(7) 55#define CONTROL_CCE BIT(6) 56#define CONTROL_DISABLE_AR BIT(5) 57#define CONTROL_ENABLE_AR (0 << 5) 58#define CONTROL_EIE BIT(3) 59#define CONTROL_SIE BIT(2) 60#define CONTROL_IE BIT(1) 61#define CONTROL_INIT BIT(0) 62 63#define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE) 64 65/* test register */ 66#define TEST_RX BIT(7) 67#define TEST_TX1 BIT(6) 68#define TEST_TX2 BIT(5) 69#define TEST_LBACK BIT(4) 70#define TEST_SILENT BIT(3) 71#define TEST_BASIC BIT(2) 72 73/* status register */ 74#define STATUS_PDA BIT(10) 75#define STATUS_BOFF BIT(7) 76#define STATUS_EWARN BIT(6) 77#define STATUS_EPASS BIT(5) 78#define STATUS_RXOK BIT(4) 79#define STATUS_TXOK BIT(3) 80 81/* error counter register */ 82#define ERR_CNT_TEC_MASK 0xff 83#define ERR_CNT_TEC_SHIFT 0 84#define ERR_CNT_REC_SHIFT 8 85#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 86#define ERR_CNT_RP_SHIFT 15 87#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 88 89/* bit-timing register */ 90#define BTR_BRP_MASK 0x3f 91#define BTR_BRP_SHIFT 0 92#define BTR_SJW_SHIFT 6 93#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 94#define BTR_TSEG1_SHIFT 8 95#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 96#define BTR_TSEG2_SHIFT 12 97#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 98 99/* brp extension register */ 100#define BRP_EXT_BRPE_MASK 0x0f 101#define BRP_EXT_BRPE_SHIFT 0 102 103/* IFx command request */ 104#define IF_COMR_BUSY BIT(15) 105 106/* IFx command mask */ 107#define IF_COMM_WR BIT(7) 108#define IF_COMM_MASK BIT(6) 109#define IF_COMM_ARB BIT(5) 110#define IF_COMM_CONTROL BIT(4) 111#define IF_COMM_CLR_INT_PND BIT(3) 112#define IF_COMM_TXRQST BIT(2) 113#define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST 114#define IF_COMM_DATAA BIT(1) 115#define IF_COMM_DATAB BIT(0) 116 117/* TX buffer setup */ 118#define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \ 119 IF_COMM_TXRQST | \ 120 IF_COMM_DATAA | IF_COMM_DATAB) 121 122/* For the low buffers we clear the interrupt bit, but keep newdat */ 123#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 124 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 125 IF_COMM_DATAA | IF_COMM_DATAB) 126 127/* For the high buffers we clear the interrupt bit and newdat */ 128#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT) 129 130 131/* Receive setup of message objects */ 132#define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL) 133 134/* Invalidation of message objects */ 135#define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL) 136 137/* IFx arbitration */ 138#define IF_ARB_MSGVAL BIT(31) 139#define IF_ARB_MSGXTD BIT(30) 140#define IF_ARB_TRANSMIT BIT(29) 141 142/* IFx message control */ 143#define IF_MCONT_NEWDAT BIT(15) 144#define IF_MCONT_MSGLST BIT(14) 145#define IF_MCONT_INTPND BIT(13) 146#define IF_MCONT_UMASK BIT(12) 147#define IF_MCONT_TXIE BIT(11) 148#define IF_MCONT_RXIE BIT(10) 149#define IF_MCONT_RMTEN BIT(9) 150#define IF_MCONT_TXRQST BIT(8) 151#define IF_MCONT_EOB BIT(7) 152#define IF_MCONT_DLC_MASK 0xf 153 154#define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK) 155#define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB) 156 157#define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB) 158 159/* 160 * Use IF1 for RX and IF2 for TX 161 */ 162#define IF_RX 0 163#define IF_TX 1 164 165/* minimum timeout for checking BUSY status */ 166#define MIN_TIMEOUT_VALUE 6 167 168/* Wait for ~1 sec for INIT bit */ 169#define INIT_WAIT_MS 1000 170 171/* napi related */ 172#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 173 174/* c_can lec values */ 175enum c_can_lec_type { 176 LEC_NO_ERROR = 0, 177 LEC_STUFF_ERROR, 178 LEC_FORM_ERROR, 179 LEC_ACK_ERROR, 180 LEC_BIT1_ERROR, 181 LEC_BIT0_ERROR, 182 LEC_CRC_ERROR, 183 LEC_UNUSED, 184 LEC_MASK = LEC_UNUSED, 185}; 186 187/* 188 * c_can error types: 189 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 190 */ 191enum c_can_bus_error_types { 192 C_CAN_NO_ERROR = 0, 193 C_CAN_BUS_OFF, 194 C_CAN_ERROR_WARNING, 195 C_CAN_ERROR_PASSIVE, 196}; 197 198static const struct can_bittiming_const c_can_bittiming_const = { 199 .name = KBUILD_MODNAME, 200 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 201 .tseg1_max = 16, 202 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 203 .tseg2_max = 8, 204 .sjw_max = 4, 205 .brp_min = 1, 206 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 207 .brp_inc = 1, 208}; 209 210static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 211{ 212 if (priv->device) 213 pm_runtime_enable(priv->device); 214} 215 216static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 217{ 218 if (priv->device) 219 pm_runtime_disable(priv->device); 220} 221 222static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 223{ 224 if (priv->device) 225 pm_runtime_get_sync(priv->device); 226} 227 228static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 229{ 230 if (priv->device) 231 pm_runtime_put_sync(priv->device); 232} 233 234static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 235{ 236 if (priv->raminit) 237 priv->raminit(priv, enable); 238} 239 240static void c_can_irq_control(struct c_can_priv *priv, bool enable) 241{ 242 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK; 243 244 if (enable) 245 ctrl |= CONTROL_IRQMSK; 246 247 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl); 248} 249 250static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj) 251{ 252 struct c_can_priv *priv = netdev_priv(dev); 253 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface); 254 255 priv->write_reg32(priv, reg, (cmd << 16) | obj); 256 257 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) { 258 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY)) 259 return; 260 udelay(1); 261 } 262 netdev_err(dev, "Updating object timed out\n"); 263 264} 265 266static inline void c_can_object_get(struct net_device *dev, int iface, 267 u32 obj, u32 cmd) 268{ 269 c_can_obj_update(dev, iface, cmd, obj); 270} 271 272static inline void c_can_object_put(struct net_device *dev, int iface, 273 u32 obj, u32 cmd) 274{ 275 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj); 276} 277 278/* 279 * Note: According to documentation clearing TXIE while MSGVAL is set 280 * is not allowed, but works nicely on C/DCAN. And that lowers the I/O 281 * load significantly. 282 */ 283static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj) 284{ 285 struct c_can_priv *priv = netdev_priv(dev); 286 287 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 288 c_can_object_put(dev, iface, obj, IF_COMM_INVAL); 289} 290 291static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj) 292{ 293 struct c_can_priv *priv = netdev_priv(dev); 294 295 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 296 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 297 c_can_inval_tx_object(dev, iface, obj); 298} 299 300static void c_can_setup_tx_object(struct net_device *dev, int iface, 301 struct can_frame *frame, int idx) 302{ 303 struct c_can_priv *priv = netdev_priv(dev); 304 u16 ctrl = IF_MCONT_TX | frame->can_dlc; 305 bool rtr = frame->can_id & CAN_RTR_FLAG; 306 u32 arb = IF_ARB_MSGVAL; 307 int i; 308 309 if (frame->can_id & CAN_EFF_FLAG) { 310 arb |= frame->can_id & CAN_EFF_MASK; 311 arb |= IF_ARB_MSGXTD; 312 } else { 313 arb |= (frame->can_id & CAN_SFF_MASK) << 18; 314 } 315 316 if (!rtr) 317 arb |= IF_ARB_TRANSMIT; 318 319 /* 320 * If we change the DIR bit, we need to invalidate the buffer 321 * first, i.e. clear the MSGVAL flag in the arbiter. 322 */ 323 if (rtr != (bool)test_bit(idx, &priv->tx_dir)) { 324 u32 obj = idx + C_CAN_MSG_OBJ_TX_FIRST; 325 326 c_can_inval_msg_object(dev, iface, obj); 327 change_bit(idx, &priv->tx_dir); 328 } 329 330 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb); 331 332 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 333 334 for (i = 0; i < frame->can_dlc; i += 2) { 335 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 336 frame->data[i] | (frame->data[i + 1] << 8)); 337 } 338} 339 340static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 341 int iface) 342{ 343 int i; 344 345 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) 346 c_can_object_get(dev, iface, i, IF_COMM_CLR_NEWDAT); 347} 348 349static int c_can_handle_lost_msg_obj(struct net_device *dev, 350 int iface, int objno, u32 ctrl) 351{ 352 struct net_device_stats *stats = &dev->stats; 353 struct c_can_priv *priv = netdev_priv(dev); 354 struct can_frame *frame; 355 struct sk_buff *skb; 356 357 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 358 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 359 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 360 361 stats->rx_errors++; 362 stats->rx_over_errors++; 363 364 /* create an error msg */ 365 skb = alloc_can_err_skb(dev, &frame); 366 if (unlikely(!skb)) 367 return 0; 368 369 frame->can_id |= CAN_ERR_CRTL; 370 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 371 372 netif_receive_skb(skb); 373 return 1; 374} 375 376static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl) 377{ 378 struct net_device_stats *stats = &dev->stats; 379 struct c_can_priv *priv = netdev_priv(dev); 380 struct can_frame *frame; 381 struct sk_buff *skb; 382 u32 arb, data; 383 384 skb = alloc_can_skb(dev, &frame); 385 if (!skb) { 386 stats->rx_dropped++; 387 return -ENOMEM; 388 } 389 390 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 391 392 arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface)); 393 394 if (arb & IF_ARB_MSGXTD) 395 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG; 396 else 397 frame->can_id = (arb >> 18) & CAN_SFF_MASK; 398 399 if (arb & IF_ARB_TRANSMIT) { 400 frame->can_id |= CAN_RTR_FLAG; 401 } else { 402 int i, dreg = C_CAN_IFACE(DATA1_REG, iface); 403 404 for (i = 0; i < frame->can_dlc; i += 2, dreg ++) { 405 data = priv->read_reg(priv, dreg); 406 frame->data[i] = data; 407 frame->data[i + 1] = data >> 8; 408 } 409 } 410 411 stats->rx_packets++; 412 stats->rx_bytes += frame->can_dlc; 413 414 netif_receive_skb(skb); 415 return 0; 416} 417 418static void c_can_setup_receive_object(struct net_device *dev, int iface, 419 u32 obj, u32 mask, u32 id, u32 mcont) 420{ 421 struct c_can_priv *priv = netdev_priv(dev); 422 423 mask |= BIT(29); 424 priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask); 425 426 id |= IF_ARB_MSGVAL; 427 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id); 428 429 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 430 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP); 431} 432 433static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 434 struct net_device *dev) 435{ 436 struct can_frame *frame = (struct can_frame *)skb->data; 437 struct c_can_priv *priv = netdev_priv(dev); 438 u32 idx, obj; 439 440 if (can_dropped_invalid_skb(dev, skb)) 441 return NETDEV_TX_OK; 442 /* 443 * This is not a FIFO. C/D_CAN sends out the buffers 444 * prioritized. The lowest buffer number wins. 445 */ 446 idx = fls(atomic_read(&priv->tx_active)); 447 obj = idx + C_CAN_MSG_OBJ_TX_FIRST; 448 449 /* If this is the last buffer, stop the xmit queue */ 450 if (idx == C_CAN_MSG_OBJ_TX_NUM - 1) 451 netif_stop_queue(dev); 452 /* 453 * Store the message in the interface so we can call 454 * can_put_echo_skb(). We must do this before we enable 455 * transmit as we might race against do_tx(). 456 */ 457 c_can_setup_tx_object(dev, IF_TX, frame, idx); 458 priv->dlc[idx] = frame->can_dlc; 459 can_put_echo_skb(skb, dev, idx); 460 461 /* Update the active bits */ 462 atomic_add((1 << idx), &priv->tx_active); 463 /* Start transmission */ 464 c_can_object_put(dev, IF_TX, obj, IF_COMM_TX); 465 466 return NETDEV_TX_OK; 467} 468 469static int c_can_wait_for_ctrl_init(struct net_device *dev, 470 struct c_can_priv *priv, u32 init) 471{ 472 int retry = 0; 473 474 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 475 udelay(10); 476 if (retry++ > 1000) { 477 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 478 return -EIO; 479 } 480 } 481 return 0; 482} 483 484static int c_can_set_bittiming(struct net_device *dev) 485{ 486 unsigned int reg_btr, reg_brpe, ctrl_save; 487 u8 brp, brpe, sjw, tseg1, tseg2; 488 u32 ten_bit_brp; 489 struct c_can_priv *priv = netdev_priv(dev); 490 const struct can_bittiming *bt = &priv->can.bittiming; 491 int res; 492 493 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 494 ten_bit_brp = bt->brp - 1; 495 brp = ten_bit_brp & BTR_BRP_MASK; 496 brpe = ten_bit_brp >> 6; 497 498 sjw = bt->sjw - 1; 499 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 500 tseg2 = bt->phase_seg2 - 1; 501 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 502 (tseg2 << BTR_TSEG2_SHIFT); 503 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 504 505 netdev_info(dev, 506 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 507 508 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 509 ctrl_save &= ~CONTROL_INIT; 510 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 511 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 512 if (res) 513 return res; 514 515 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 516 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 517 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 518 519 return c_can_wait_for_ctrl_init(dev, priv, 0); 520} 521 522/* 523 * Configure C_CAN message objects for Tx and Rx purposes: 524 * C_CAN provides a total of 32 message objects that can be configured 525 * either for Tx or Rx purposes. Here the first 16 message objects are used as 526 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 527 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 528 * See user guide document for further details on configuring message 529 * objects. 530 */ 531static void c_can_configure_msg_objects(struct net_device *dev) 532{ 533 int i; 534 535 /* first invalidate all message objects */ 536 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 537 c_can_inval_msg_object(dev, IF_RX, i); 538 539 /* setup receive message objects */ 540 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 541 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV); 542 543 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 544 IF_MCONT_RCV_EOB); 545} 546 547/* 548 * Configure C_CAN chip: 549 * - enable/disable auto-retransmission 550 * - set operating mode 551 * - configure message objects 552 */ 553static int c_can_chip_config(struct net_device *dev) 554{ 555 struct c_can_priv *priv = netdev_priv(dev); 556 557 /* enable automatic retransmission */ 558 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); 559 560 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 561 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 562 /* loopback + silent mode : useful for hot self-test */ 563 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 564 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); 565 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 566 /* loopback mode : useful for self-test function */ 567 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 568 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 569 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 570 /* silent mode : bus-monitoring mode */ 571 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 572 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 573 } 574 575 /* configure message objects */ 576 c_can_configure_msg_objects(dev); 577 578 /* set a `lec` value so that we can check for updates later */ 579 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 580 581 /* Clear all internal status */ 582 atomic_set(&priv->tx_active, 0); 583 priv->rxmasked = 0; 584 priv->tx_dir = 0; 585 586 /* set bittiming params */ 587 return c_can_set_bittiming(dev); 588} 589 590static int c_can_start(struct net_device *dev) 591{ 592 struct c_can_priv *priv = netdev_priv(dev); 593 int err; 594 595 /* basic c_can configuration */ 596 err = c_can_chip_config(dev); 597 if (err) 598 return err; 599 600 /* Setup the command for new messages */ 601 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ? 602 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 603 604 priv->can.state = CAN_STATE_ERROR_ACTIVE; 605 606 return 0; 607} 608 609static void c_can_stop(struct net_device *dev) 610{ 611 struct c_can_priv *priv = netdev_priv(dev); 612 613 c_can_irq_control(priv, false); 614 priv->can.state = CAN_STATE_STOPPED; 615} 616 617static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 618{ 619 struct c_can_priv *priv = netdev_priv(dev); 620 int err; 621 622 switch (mode) { 623 case CAN_MODE_START: 624 err = c_can_start(dev); 625 if (err) 626 return err; 627 netif_wake_queue(dev); 628 c_can_irq_control(priv, true); 629 break; 630 default: 631 return -EOPNOTSUPP; 632 } 633 634 return 0; 635} 636 637static int __c_can_get_berr_counter(const struct net_device *dev, 638 struct can_berr_counter *bec) 639{ 640 unsigned int reg_err_counter; 641 struct c_can_priv *priv = netdev_priv(dev); 642 643 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 644 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 645 ERR_CNT_REC_SHIFT; 646 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 647 648 return 0; 649} 650 651static int c_can_get_berr_counter(const struct net_device *dev, 652 struct can_berr_counter *bec) 653{ 654 struct c_can_priv *priv = netdev_priv(dev); 655 int err; 656 657 c_can_pm_runtime_get_sync(priv); 658 err = __c_can_get_berr_counter(dev, bec); 659 c_can_pm_runtime_put_sync(priv); 660 661 return err; 662} 663 664static void c_can_do_tx(struct net_device *dev) 665{ 666 struct c_can_priv *priv = netdev_priv(dev); 667 struct net_device_stats *stats = &dev->stats; 668 u32 idx, obj, pkts = 0, bytes = 0, pend, clr; 669 670 clr = pend = priv->read_reg(priv, C_CAN_INTPND2_REG); 671 672 while ((idx = ffs(pend))) { 673 idx--; 674 pend &= ~(1 << idx); 675 obj = idx + C_CAN_MSG_OBJ_TX_FIRST; 676 c_can_inval_tx_object(dev, IF_RX, obj); 677 can_get_echo_skb(dev, idx); 678 bytes += priv->dlc[idx]; 679 pkts++; 680 } 681 682 /* Clear the bits in the tx_active mask */ 683 atomic_sub(clr, &priv->tx_active); 684 685 if (clr & (1 << (C_CAN_MSG_OBJ_TX_NUM - 1))) 686 netif_wake_queue(dev); 687 688 if (pkts) { 689 stats->tx_bytes += bytes; 690 stats->tx_packets += pkts; 691 can_led_event(dev, CAN_LED_EVENT_TX); 692 } 693} 694 695/* 696 * If we have a gap in the pending bits, that means we either 697 * raced with the hardware or failed to readout all upper 698 * objects in the last run due to quota limit. 699 */ 700static u32 c_can_adjust_pending(u32 pend) 701{ 702 u32 weight, lasts; 703 704 if (pend == RECEIVE_OBJECT_BITS) 705 return pend; 706 707 /* 708 * If the last set bit is larger than the number of pending 709 * bits we have a gap. 710 */ 711 weight = hweight32(pend); 712 lasts = fls(pend); 713 714 /* If the bits are linear, nothing to do */ 715 if (lasts == weight) 716 return pend; 717 718 /* 719 * Find the first set bit after the gap. We walk backwards 720 * from the last set bit. 721 */ 722 for (lasts--; pend & (1 << (lasts - 1)); lasts--); 723 724 return pend & ~((1 << lasts) - 1); 725} 726 727static inline void c_can_rx_object_get(struct net_device *dev, 728 struct c_can_priv *priv, u32 obj) 729{ 730#ifdef CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING 731 if (obj < C_CAN_MSG_RX_LOW_LAST) 732 c_can_object_get(dev, IF_RX, obj, IF_COMM_RCV_LOW); 733 else 734#endif 735 c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high); 736} 737 738static inline void c_can_rx_finalize(struct net_device *dev, 739 struct c_can_priv *priv, u32 obj) 740{ 741#ifdef CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING 742 if (obj < C_CAN_MSG_RX_LOW_LAST) 743 priv->rxmasked |= BIT(obj - 1); 744 else if (obj == C_CAN_MSG_RX_LOW_LAST) { 745 priv->rxmasked = 0; 746 /* activate all lower message objects */ 747 c_can_activate_all_lower_rx_msg_obj(dev, IF_RX); 748 } 749#endif 750 if (priv->type != BOSCH_D_CAN) 751 c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT); 752} 753 754static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 755 u32 pend, int quota) 756{ 757 u32 pkts = 0, ctrl, obj; 758 759 while ((obj = ffs(pend)) && quota > 0) { 760 pend &= ~BIT(obj - 1); 761 762 c_can_rx_object_get(dev, priv, obj); 763 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 764 765 if (ctrl & IF_MCONT_MSGLST) { 766 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); 767 768 pkts += n; 769 quota -= n; 770 continue; 771 } 772 773 /* 774 * This really should not happen, but this covers some 775 * odd HW behaviour. Do not remove that unless you 776 * want to brick your machine. 777 */ 778 if (!(ctrl & IF_MCONT_NEWDAT)) 779 continue; 780 781 /* read the data from the message object */ 782 c_can_read_msg_object(dev, IF_RX, ctrl); 783 784 c_can_rx_finalize(dev, priv, obj); 785 786 pkts++; 787 quota--; 788 } 789 790 return pkts; 791} 792 793static inline u32 c_can_get_pending(struct c_can_priv *priv) 794{ 795 u32 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG); 796 797#ifdef CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING 798 pend &= ~priv->rxmasked; 799#endif 800 return pend; 801} 802 803/* 804 * theory of operation: 805 * 806 * c_can core saves a received CAN message into the first free message 807 * object it finds free (starting with the lowest). Bits NEWDAT and 808 * INTPND are set for this message object indicating that a new message 809 * has arrived. To work-around this issue, we keep two groups of message 810 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 811 * 812 * If CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING = y 813 * 814 * To ensure in-order frame reception we use the following 815 * approach while re-activating a message object to receive further 816 * frames: 817 * - if the current message object number is lower than 818 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 819 * the INTPND bit. 820 * - if the current message object number is equal to 821 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 822 * receive message objects. 823 * - if the current message object number is greater than 824 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 825 * only this message object. 826 * 827 * This can cause packet loss! 828 * 829 * If CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING = n 830 * 831 * We clear the newdat bit right away. 832 * 833 * This can result in packet reordering when the readout is slow. 834 */ 835static int c_can_do_rx_poll(struct net_device *dev, int quota) 836{ 837 struct c_can_priv *priv = netdev_priv(dev); 838 u32 pkts = 0, pend = 0, toread, n; 839 840 /* 841 * It is faster to read only one 16bit register. This is only possible 842 * for a maximum number of 16 objects. 843 */ 844 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, 845 "Implementation does not support more message objects than 16"); 846 847 while (quota > 0) { 848 if (!pend) { 849 pend = c_can_get_pending(priv); 850 if (!pend) 851 break; 852 /* 853 * If the pending field has a gap, handle the 854 * bits above the gap first. 855 */ 856 toread = c_can_adjust_pending(pend); 857 } else { 858 toread = pend; 859 } 860 /* Remove the bits from pend */ 861 pend &= ~toread; 862 /* Read the objects */ 863 n = c_can_read_objects(dev, priv, toread, quota); 864 pkts += n; 865 quota -= n; 866 } 867 868 if (pkts) 869 can_led_event(dev, CAN_LED_EVENT_RX); 870 871 return pkts; 872} 873 874static int c_can_handle_state_change(struct net_device *dev, 875 enum c_can_bus_error_types error_type) 876{ 877 unsigned int reg_err_counter; 878 unsigned int rx_err_passive; 879 struct c_can_priv *priv = netdev_priv(dev); 880 struct net_device_stats *stats = &dev->stats; 881 struct can_frame *cf; 882 struct sk_buff *skb; 883 struct can_berr_counter bec; 884 885 switch (error_type) { 886 case C_CAN_ERROR_WARNING: 887 /* error warning state */ 888 priv->can.can_stats.error_warning++; 889 priv->can.state = CAN_STATE_ERROR_WARNING; 890 break; 891 case C_CAN_ERROR_PASSIVE: 892 /* error passive state */ 893 priv->can.can_stats.error_passive++; 894 priv->can.state = CAN_STATE_ERROR_PASSIVE; 895 break; 896 case C_CAN_BUS_OFF: 897 /* bus-off state */ 898 priv->can.state = CAN_STATE_BUS_OFF; 899 can_bus_off(dev); 900 break; 901 default: 902 break; 903 } 904 905 /* propagate the error condition to the CAN stack */ 906 skb = alloc_can_err_skb(dev, &cf); 907 if (unlikely(!skb)) 908 return 0; 909 910 __c_can_get_berr_counter(dev, &bec); 911 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 912 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 913 ERR_CNT_RP_SHIFT; 914 915 switch (error_type) { 916 case C_CAN_ERROR_WARNING: 917 /* error warning state */ 918 cf->can_id |= CAN_ERR_CRTL; 919 cf->data[1] = (bec.txerr > bec.rxerr) ? 920 CAN_ERR_CRTL_TX_WARNING : 921 CAN_ERR_CRTL_RX_WARNING; 922 cf->data[6] = bec.txerr; 923 cf->data[7] = bec.rxerr; 924 925 break; 926 case C_CAN_ERROR_PASSIVE: 927 /* error passive state */ 928 cf->can_id |= CAN_ERR_CRTL; 929 if (rx_err_passive) 930 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 931 if (bec.txerr > 127) 932 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 933 934 cf->data[6] = bec.txerr; 935 cf->data[7] = bec.rxerr; 936 break; 937 case C_CAN_BUS_OFF: 938 /* bus-off state */ 939 cf->can_id |= CAN_ERR_BUSOFF; 940 can_bus_off(dev); 941 break; 942 default: 943 break; 944 } 945 946 stats->rx_packets++; 947 stats->rx_bytes += cf->can_dlc; 948 netif_receive_skb(skb); 949 950 return 1; 951} 952 953static int c_can_handle_bus_err(struct net_device *dev, 954 enum c_can_lec_type lec_type) 955{ 956 struct c_can_priv *priv = netdev_priv(dev); 957 struct net_device_stats *stats = &dev->stats; 958 struct can_frame *cf; 959 struct sk_buff *skb; 960 961 /* 962 * early exit if no lec update or no error. 963 * no lec update means that no CAN bus event has been detected 964 * since CPU wrote 0x7 value to status reg. 965 */ 966 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 967 return 0; 968 969 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 970 return 0; 971 972 /* common for all type of bus errors */ 973 priv->can.can_stats.bus_error++; 974 stats->rx_errors++; 975 976 /* propagate the error condition to the CAN stack */ 977 skb = alloc_can_err_skb(dev, &cf); 978 if (unlikely(!skb)) 979 return 0; 980 981 /* 982 * check for 'last error code' which tells us the 983 * type of the last error to occur on the CAN bus 984 */ 985 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 986 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 987 988 switch (lec_type) { 989 case LEC_STUFF_ERROR: 990 netdev_dbg(dev, "stuff error\n"); 991 cf->data[2] |= CAN_ERR_PROT_STUFF; 992 break; 993 case LEC_FORM_ERROR: 994 netdev_dbg(dev, "form error\n"); 995 cf->data[2] |= CAN_ERR_PROT_FORM; 996 break; 997 case LEC_ACK_ERROR: 998 netdev_dbg(dev, "ack error\n"); 999 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 1000 CAN_ERR_PROT_LOC_ACK_DEL); 1001 break; 1002 case LEC_BIT1_ERROR: 1003 netdev_dbg(dev, "bit1 error\n"); 1004 cf->data[2] |= CAN_ERR_PROT_BIT1; 1005 break; 1006 case LEC_BIT0_ERROR: 1007 netdev_dbg(dev, "bit0 error\n"); 1008 cf->data[2] |= CAN_ERR_PROT_BIT0; 1009 break; 1010 case LEC_CRC_ERROR: 1011 netdev_dbg(dev, "CRC error\n"); 1012 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 1013 CAN_ERR_PROT_LOC_CRC_DEL); 1014 break; 1015 default: 1016 break; 1017 } 1018 1019 stats->rx_packets++; 1020 stats->rx_bytes += cf->can_dlc; 1021 netif_receive_skb(skb); 1022 return 1; 1023} 1024 1025static int c_can_poll(struct napi_struct *napi, int quota) 1026{ 1027 struct net_device *dev = napi->dev; 1028 struct c_can_priv *priv = netdev_priv(dev); 1029 u16 curr, last = priv->last_status; 1030 int work_done = 0; 1031 1032 priv->last_status = curr = priv->read_reg(priv, C_CAN_STS_REG); 1033 /* Ack status on C_CAN. D_CAN is self clearing */ 1034 if (priv->type != BOSCH_D_CAN) 1035 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1036 1037 /* handle state changes */ 1038 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) { 1039 netdev_dbg(dev, "entered error warning state\n"); 1040 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); 1041 } 1042 1043 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) { 1044 netdev_dbg(dev, "entered error passive state\n"); 1045 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); 1046 } 1047 1048 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) { 1049 netdev_dbg(dev, "entered bus off state\n"); 1050 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF); 1051 goto end; 1052 } 1053 1054 /* handle bus recovery events */ 1055 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) { 1056 netdev_dbg(dev, "left bus off state\n"); 1057 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1058 } 1059 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) { 1060 netdev_dbg(dev, "left error passive state\n"); 1061 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1062 } 1063 1064 /* handle lec errors on the bus */ 1065 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK); 1066 1067 /* Handle Tx/Rx events. We do this unconditionally */ 1068 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1069 c_can_do_tx(dev); 1070 1071end: 1072 if (work_done < quota) { 1073 napi_complete(napi); 1074 /* enable all IRQs if we are not in bus off state */ 1075 if (priv->can.state != CAN_STATE_BUS_OFF) 1076 c_can_irq_control(priv, true); 1077 } 1078 1079 return work_done; 1080} 1081 1082static irqreturn_t c_can_isr(int irq, void *dev_id) 1083{ 1084 struct net_device *dev = (struct net_device *)dev_id; 1085 struct c_can_priv *priv = netdev_priv(dev); 1086 1087 if (!priv->read_reg(priv, C_CAN_INT_REG)) 1088 return IRQ_NONE; 1089 1090 /* disable all interrupts and schedule the NAPI */ 1091 c_can_irq_control(priv, false); 1092 napi_schedule(&priv->napi); 1093 1094 return IRQ_HANDLED; 1095} 1096 1097static int c_can_open(struct net_device *dev) 1098{ 1099 int err; 1100 struct c_can_priv *priv = netdev_priv(dev); 1101 1102 c_can_pm_runtime_get_sync(priv); 1103 c_can_reset_ram(priv, true); 1104 1105 /* open the can device */ 1106 err = open_candev(dev); 1107 if (err) { 1108 netdev_err(dev, "failed to open can device\n"); 1109 goto exit_open_fail; 1110 } 1111 1112 /* register interrupt handler */ 1113 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1114 dev); 1115 if (err < 0) { 1116 netdev_err(dev, "failed to request interrupt\n"); 1117 goto exit_irq_fail; 1118 } 1119 1120 /* start the c_can controller */ 1121 err = c_can_start(dev); 1122 if (err) 1123 goto exit_start_fail; 1124 1125 can_led_event(dev, CAN_LED_EVENT_OPEN); 1126 1127 napi_enable(&priv->napi); 1128 /* enable status change, error and module interrupts */ 1129 c_can_irq_control(priv, true); 1130 netif_start_queue(dev); 1131 1132 return 0; 1133 1134exit_start_fail: 1135 free_irq(dev->irq, dev); 1136exit_irq_fail: 1137 close_candev(dev); 1138exit_open_fail: 1139 c_can_reset_ram(priv, false); 1140 c_can_pm_runtime_put_sync(priv); 1141 return err; 1142} 1143 1144static int c_can_close(struct net_device *dev) 1145{ 1146 struct c_can_priv *priv = netdev_priv(dev); 1147 1148 netif_stop_queue(dev); 1149 napi_disable(&priv->napi); 1150 c_can_stop(dev); 1151 free_irq(dev->irq, dev); 1152 close_candev(dev); 1153 1154 c_can_reset_ram(priv, false); 1155 c_can_pm_runtime_put_sync(priv); 1156 1157 can_led_event(dev, CAN_LED_EVENT_STOP); 1158 1159 return 0; 1160} 1161 1162struct net_device *alloc_c_can_dev(void) 1163{ 1164 struct net_device *dev; 1165 struct c_can_priv *priv; 1166 1167 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1168 if (!dev) 1169 return NULL; 1170 1171 priv = netdev_priv(dev); 1172 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1173 1174 priv->dev = dev; 1175 priv->can.bittiming_const = &c_can_bittiming_const; 1176 priv->can.do_set_mode = c_can_set_mode; 1177 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1178 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1179 CAN_CTRLMODE_LISTENONLY | 1180 CAN_CTRLMODE_BERR_REPORTING; 1181 1182 return dev; 1183} 1184EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1185 1186#ifdef CONFIG_PM 1187int c_can_power_down(struct net_device *dev) 1188{ 1189 u32 val; 1190 unsigned long time_out; 1191 struct c_can_priv *priv = netdev_priv(dev); 1192 1193 if (!(dev->flags & IFF_UP)) 1194 return 0; 1195 1196 WARN_ON(priv->type != BOSCH_D_CAN); 1197 1198 /* set PDR value so the device goes to power down mode */ 1199 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1200 val |= CONTROL_EX_PDR; 1201 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1202 1203 /* Wait for the PDA bit to get set */ 1204 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1205 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1206 time_after(time_out, jiffies)) 1207 cpu_relax(); 1208 1209 if (time_after(jiffies, time_out)) 1210 return -ETIMEDOUT; 1211 1212 c_can_stop(dev); 1213 1214 c_can_reset_ram(priv, false); 1215 c_can_pm_runtime_put_sync(priv); 1216 1217 return 0; 1218} 1219EXPORT_SYMBOL_GPL(c_can_power_down); 1220 1221int c_can_power_up(struct net_device *dev) 1222{ 1223 u32 val; 1224 unsigned long time_out; 1225 struct c_can_priv *priv = netdev_priv(dev); 1226 int ret; 1227 1228 if (!(dev->flags & IFF_UP)) 1229 return 0; 1230 1231 WARN_ON(priv->type != BOSCH_D_CAN); 1232 1233 c_can_pm_runtime_get_sync(priv); 1234 c_can_reset_ram(priv, true); 1235 1236 /* Clear PDR and INIT bits */ 1237 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1238 val &= ~CONTROL_EX_PDR; 1239 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1240 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1241 val &= ~CONTROL_INIT; 1242 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1243 1244 /* Wait for the PDA bit to get clear */ 1245 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1246 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1247 time_after(time_out, jiffies)) 1248 cpu_relax(); 1249 1250 if (time_after(jiffies, time_out)) 1251 return -ETIMEDOUT; 1252 1253 ret = c_can_start(dev); 1254 if (!ret) 1255 c_can_irq_control(priv, true); 1256 1257 return ret; 1258} 1259EXPORT_SYMBOL_GPL(c_can_power_up); 1260#endif 1261 1262void free_c_can_dev(struct net_device *dev) 1263{ 1264 struct c_can_priv *priv = netdev_priv(dev); 1265 1266 netif_napi_del(&priv->napi); 1267 free_candev(dev); 1268} 1269EXPORT_SYMBOL_GPL(free_c_can_dev); 1270 1271static const struct net_device_ops c_can_netdev_ops = { 1272 .ndo_open = c_can_open, 1273 .ndo_stop = c_can_close, 1274 .ndo_start_xmit = c_can_start_xmit, 1275 .ndo_change_mtu = can_change_mtu, 1276}; 1277 1278int register_c_can_dev(struct net_device *dev) 1279{ 1280 struct c_can_priv *priv = netdev_priv(dev); 1281 int err; 1282 1283 c_can_pm_runtime_enable(priv); 1284 1285 dev->flags |= IFF_ECHO; /* we support local echo */ 1286 dev->netdev_ops = &c_can_netdev_ops; 1287 1288 err = register_candev(dev); 1289 if (err) 1290 c_can_pm_runtime_disable(priv); 1291 else 1292 devm_can_led_init(dev); 1293 1294 return err; 1295} 1296EXPORT_SYMBOL_GPL(register_c_can_dev); 1297 1298void unregister_c_can_dev(struct net_device *dev) 1299{ 1300 struct c_can_priv *priv = netdev_priv(dev); 1301 1302 unregister_candev(dev); 1303 1304 c_can_pm_runtime_disable(priv); 1305} 1306EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1307 1308MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1309MODULE_LICENSE("GPL v2"); 1310MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1311