c_can.c revision d48071be6cb94912cf3c3ac0b4d520438fab4778
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42#include <linux/can/led.h> 43 44#include "c_can.h" 45 46/* Number of interface registers */ 47#define IF_ENUM_REG_LEN 11 48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 49 50/* control extension register D_CAN specific */ 51#define CONTROL_EX_PDR BIT(8) 52 53/* control register */ 54#define CONTROL_TEST BIT(7) 55#define CONTROL_CCE BIT(6) 56#define CONTROL_DISABLE_AR BIT(5) 57#define CONTROL_ENABLE_AR (0 << 5) 58#define CONTROL_EIE BIT(3) 59#define CONTROL_SIE BIT(2) 60#define CONTROL_IE BIT(1) 61#define CONTROL_INIT BIT(0) 62 63#define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE) 64 65/* test register */ 66#define TEST_RX BIT(7) 67#define TEST_TX1 BIT(6) 68#define TEST_TX2 BIT(5) 69#define TEST_LBACK BIT(4) 70#define TEST_SILENT BIT(3) 71#define TEST_BASIC BIT(2) 72 73/* status register */ 74#define STATUS_PDA BIT(10) 75#define STATUS_BOFF BIT(7) 76#define STATUS_EWARN BIT(6) 77#define STATUS_EPASS BIT(5) 78#define STATUS_RXOK BIT(4) 79#define STATUS_TXOK BIT(3) 80 81/* error counter register */ 82#define ERR_CNT_TEC_MASK 0xff 83#define ERR_CNT_TEC_SHIFT 0 84#define ERR_CNT_REC_SHIFT 8 85#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 86#define ERR_CNT_RP_SHIFT 15 87#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 88 89/* bit-timing register */ 90#define BTR_BRP_MASK 0x3f 91#define BTR_BRP_SHIFT 0 92#define BTR_SJW_SHIFT 6 93#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 94#define BTR_TSEG1_SHIFT 8 95#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 96#define BTR_TSEG2_SHIFT 12 97#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 98 99/* brp extension register */ 100#define BRP_EXT_BRPE_MASK 0x0f 101#define BRP_EXT_BRPE_SHIFT 0 102 103/* IFx command request */ 104#define IF_COMR_BUSY BIT(15) 105 106/* IFx command mask */ 107#define IF_COMM_WR BIT(7) 108#define IF_COMM_MASK BIT(6) 109#define IF_COMM_ARB BIT(5) 110#define IF_COMM_CONTROL BIT(4) 111#define IF_COMM_CLR_INT_PND BIT(3) 112#define IF_COMM_TXRQST BIT(2) 113#define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST 114#define IF_COMM_DATAA BIT(1) 115#define IF_COMM_DATAB BIT(0) 116 117/* TX buffer setup */ 118#define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \ 119 IF_COMM_TXRQST | \ 120 IF_COMM_DATAA | IF_COMM_DATAB) 121 122/* For the low buffers we clear the interrupt bit, but keep newdat */ 123#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 124 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 125 IF_COMM_DATAA | IF_COMM_DATAB) 126 127/* For the high buffers we clear the interrupt bit and newdat */ 128#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT) 129 130 131/* Receive setup of message objects */ 132#define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL) 133 134/* Invalidation of message objects */ 135#define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL) 136 137/* IFx arbitration */ 138#define IF_ARB_MSGVAL BIT(31) 139#define IF_ARB_MSGXTD BIT(30) 140#define IF_ARB_TRANSMIT BIT(29) 141 142/* IFx message control */ 143#define IF_MCONT_NEWDAT BIT(15) 144#define IF_MCONT_MSGLST BIT(14) 145#define IF_MCONT_INTPND BIT(13) 146#define IF_MCONT_UMASK BIT(12) 147#define IF_MCONT_TXIE BIT(11) 148#define IF_MCONT_RXIE BIT(10) 149#define IF_MCONT_RMTEN BIT(9) 150#define IF_MCONT_TXRQST BIT(8) 151#define IF_MCONT_EOB BIT(7) 152#define IF_MCONT_DLC_MASK 0xf 153 154#define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK) 155#define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB) 156 157#define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB) 158 159/* 160 * Use IF1 for RX and IF2 for TX 161 */ 162#define IF_RX 0 163#define IF_TX 1 164 165/* minimum timeout for checking BUSY status */ 166#define MIN_TIMEOUT_VALUE 6 167 168/* Wait for ~1 sec for INIT bit */ 169#define INIT_WAIT_MS 1000 170 171/* napi related */ 172#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 173 174/* c_can lec values */ 175enum c_can_lec_type { 176 LEC_NO_ERROR = 0, 177 LEC_STUFF_ERROR, 178 LEC_FORM_ERROR, 179 LEC_ACK_ERROR, 180 LEC_BIT1_ERROR, 181 LEC_BIT0_ERROR, 182 LEC_CRC_ERROR, 183 LEC_UNUSED, 184 LEC_MASK = LEC_UNUSED, 185}; 186 187/* 188 * c_can error types: 189 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 190 */ 191enum c_can_bus_error_types { 192 C_CAN_NO_ERROR = 0, 193 C_CAN_BUS_OFF, 194 C_CAN_ERROR_WARNING, 195 C_CAN_ERROR_PASSIVE, 196}; 197 198static const struct can_bittiming_const c_can_bittiming_const = { 199 .name = KBUILD_MODNAME, 200 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 201 .tseg1_max = 16, 202 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 203 .tseg2_max = 8, 204 .sjw_max = 4, 205 .brp_min = 1, 206 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 207 .brp_inc = 1, 208}; 209 210static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 211{ 212 if (priv->device) 213 pm_runtime_enable(priv->device); 214} 215 216static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 217{ 218 if (priv->device) 219 pm_runtime_disable(priv->device); 220} 221 222static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 223{ 224 if (priv->device) 225 pm_runtime_get_sync(priv->device); 226} 227 228static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 229{ 230 if (priv->device) 231 pm_runtime_put_sync(priv->device); 232} 233 234static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 235{ 236 if (priv->raminit) 237 priv->raminit(priv, enable); 238} 239 240static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 241{ 242 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + 243 C_CAN_MSG_OBJ_TX_FIRST; 244} 245 246static inline int get_tx_echo_msg_obj(int txecho) 247{ 248 return (txecho & C_CAN_NEXT_MSG_OBJ_MASK) + C_CAN_MSG_OBJ_TX_FIRST; 249} 250 251static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) 252{ 253 u32 val = priv->read_reg(priv, index); 254 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 255 return val; 256} 257 258static void c_can_irq_control(struct c_can_priv *priv, bool enable) 259{ 260 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK; 261 262 if (enable) 263 ctrl |= CONTROL_IRQMSK; 264 265 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl); 266} 267 268static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj) 269{ 270 struct c_can_priv *priv = netdev_priv(dev); 271 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface); 272 273 priv->write_reg(priv, reg + 1, cmd); 274 priv->write_reg(priv, reg, obj); 275 276 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) { 277 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY)) 278 return; 279 udelay(1); 280 } 281 netdev_err(dev, "Updating object timed out\n"); 282 283} 284 285static inline void c_can_object_get(struct net_device *dev, int iface, 286 u32 obj, u32 cmd) 287{ 288 c_can_obj_update(dev, iface, cmd, obj); 289} 290 291static inline void c_can_object_put(struct net_device *dev, int iface, 292 u32 obj, u32 cmd) 293{ 294 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj); 295} 296 297static void c_can_write_msg_object(struct net_device *dev, int iface, 298 struct can_frame *frame, int obj) 299{ 300 struct c_can_priv *priv = netdev_priv(dev); 301 u16 ctrl = IF_MCONT_TX | frame->can_dlc; 302 u32 arb = IF_ARB_MSGVAL; 303 int i; 304 305 if (frame->can_id & CAN_EFF_FLAG) { 306 arb |= frame->can_id & CAN_EFF_MASK; 307 arb |= IF_ARB_MSGXTD; 308 } else { 309 arb |= (frame->can_id & CAN_SFF_MASK) << 18; 310 } 311 312 if (!(frame->can_id & CAN_RTR_FLAG)) 313 arb |= IF_ARB_TRANSMIT; 314 315 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), arb); 316 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), arb >> 16); 317 318 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 319 320 for (i = 0; i < frame->can_dlc; i += 2) { 321 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 322 frame->data[i] | (frame->data[i + 1] << 8)); 323 } 324 325 c_can_object_put(dev, iface, obj, IF_COMM_TX); 326} 327 328static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 329 int iface) 330{ 331 int i; 332 333 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) 334 c_can_object_get(dev, iface, i, IF_COMM_CLR_NEWDAT); 335} 336 337static int c_can_handle_lost_msg_obj(struct net_device *dev, 338 int iface, int objno, u32 ctrl) 339{ 340 struct net_device_stats *stats = &dev->stats; 341 struct c_can_priv *priv = netdev_priv(dev); 342 struct can_frame *frame; 343 struct sk_buff *skb; 344 345 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 346 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 347 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 348 349 stats->rx_errors++; 350 stats->rx_over_errors++; 351 352 /* create an error msg */ 353 skb = alloc_can_err_skb(dev, &frame); 354 if (unlikely(!skb)) 355 return 0; 356 357 frame->can_id |= CAN_ERR_CRTL; 358 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 359 360 netif_receive_skb(skb); 361 return 1; 362} 363 364static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl) 365{ 366 struct net_device_stats *stats = &dev->stats; 367 struct c_can_priv *priv = netdev_priv(dev); 368 struct can_frame *frame; 369 struct sk_buff *skb; 370 u32 arb, data; 371 372 skb = alloc_can_skb(dev, &frame); 373 if (!skb) { 374 stats->rx_dropped++; 375 return -ENOMEM; 376 } 377 378 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 379 380 arb = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)); 381 arb |= priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)) << 16; 382 383 if (arb & IF_ARB_MSGXTD) 384 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG; 385 else 386 frame->can_id = (arb >> 18) & CAN_SFF_MASK; 387 388 if (arb & IF_ARB_TRANSMIT) { 389 frame->can_id |= CAN_RTR_FLAG; 390 } else { 391 int i, dreg = C_CAN_IFACE(DATA1_REG, iface); 392 393 for (i = 0; i < frame->can_dlc; i += 2, dreg ++) { 394 data = priv->read_reg(priv, dreg); 395 frame->data[i] = data; 396 frame->data[i + 1] = data >> 8; 397 } 398 } 399 400 stats->rx_packets++; 401 stats->rx_bytes += frame->can_dlc; 402 403 netif_receive_skb(skb); 404 return 0; 405} 406 407static void c_can_setup_receive_object(struct net_device *dev, int iface, 408 u32 obj, u32 mask, u32 id, u32 mcont) 409{ 410 struct c_can_priv *priv = netdev_priv(dev); 411 412 mask |= BIT(29); 413 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), mask); 414 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), mask >> 16); 415 416 id |= IF_ARB_MSGVAL; 417 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), id); 418 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), id >> 16); 419 420 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 421 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP); 422} 423 424static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj) 425{ 426 struct c_can_priv *priv = netdev_priv(dev); 427 428 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 429 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 430 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 431 432 c_can_object_put(dev, iface, obj, IF_COMM_INVAL); 433} 434 435static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 436{ 437 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 438 439 /* 440 * as transmission request register's bit n-1 corresponds to 441 * message object n, we need to handle the same properly. 442 */ 443 if (val & (1 << (objno - 1))) 444 return 1; 445 446 return 0; 447} 448 449static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 450 struct net_device *dev) 451{ 452 u32 msg_obj_no; 453 struct c_can_priv *priv = netdev_priv(dev); 454 struct can_frame *frame = (struct can_frame *)skb->data; 455 456 if (can_dropped_invalid_skb(dev, skb)) 457 return NETDEV_TX_OK; 458 459 spin_lock_bh(&priv->xmit_lock); 460 msg_obj_no = get_tx_next_msg_obj(priv); 461 462 /* prepare message object for transmission */ 463 c_can_write_msg_object(dev, IF_TX, frame, msg_obj_no); 464 priv->dlc[msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST] = frame->can_dlc; 465 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 466 467 /* 468 * we have to stop the queue in case of a wrap around or 469 * if the next TX message object is still in use 470 */ 471 priv->tx_next++; 472 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 473 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 474 netif_stop_queue(dev); 475 spin_unlock_bh(&priv->xmit_lock); 476 477 return NETDEV_TX_OK; 478} 479 480static int c_can_wait_for_ctrl_init(struct net_device *dev, 481 struct c_can_priv *priv, u32 init) 482{ 483 int retry = 0; 484 485 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 486 udelay(10); 487 if (retry++ > 1000) { 488 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 489 return -EIO; 490 } 491 } 492 return 0; 493} 494 495static int c_can_set_bittiming(struct net_device *dev) 496{ 497 unsigned int reg_btr, reg_brpe, ctrl_save; 498 u8 brp, brpe, sjw, tseg1, tseg2; 499 u32 ten_bit_brp; 500 struct c_can_priv *priv = netdev_priv(dev); 501 const struct can_bittiming *bt = &priv->can.bittiming; 502 int res; 503 504 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 505 ten_bit_brp = bt->brp - 1; 506 brp = ten_bit_brp & BTR_BRP_MASK; 507 brpe = ten_bit_brp >> 6; 508 509 sjw = bt->sjw - 1; 510 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 511 tseg2 = bt->phase_seg2 - 1; 512 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 513 (tseg2 << BTR_TSEG2_SHIFT); 514 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 515 516 netdev_info(dev, 517 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 518 519 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 520 ctrl_save &= ~CONTROL_INIT; 521 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 522 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 523 if (res) 524 return res; 525 526 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 527 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 528 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 529 530 return c_can_wait_for_ctrl_init(dev, priv, 0); 531} 532 533/* 534 * Configure C_CAN message objects for Tx and Rx purposes: 535 * C_CAN provides a total of 32 message objects that can be configured 536 * either for Tx or Rx purposes. Here the first 16 message objects are used as 537 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 538 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 539 * See user guide document for further details on configuring message 540 * objects. 541 */ 542static void c_can_configure_msg_objects(struct net_device *dev) 543{ 544 int i; 545 546 /* first invalidate all message objects */ 547 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 548 c_can_inval_msg_object(dev, IF_RX, i); 549 550 /* setup receive message objects */ 551 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 552 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV); 553 554 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 555 IF_MCONT_RCV_EOB); 556} 557 558/* 559 * Configure C_CAN chip: 560 * - enable/disable auto-retransmission 561 * - set operating mode 562 * - configure message objects 563 */ 564static int c_can_chip_config(struct net_device *dev) 565{ 566 struct c_can_priv *priv = netdev_priv(dev); 567 568 /* enable automatic retransmission */ 569 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); 570 571 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 572 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 573 /* loopback + silent mode : useful for hot self-test */ 574 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 575 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); 576 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 577 /* loopback mode : useful for self-test function */ 578 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 579 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 580 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 581 /* silent mode : bus-monitoring mode */ 582 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 583 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 584 } 585 586 /* configure message objects */ 587 c_can_configure_msg_objects(dev); 588 589 /* set a `lec` value so that we can check for updates later */ 590 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 591 592 /* set bittiming params */ 593 return c_can_set_bittiming(dev); 594} 595 596static int c_can_start(struct net_device *dev) 597{ 598 struct c_can_priv *priv = netdev_priv(dev); 599 int err; 600 601 /* basic c_can configuration */ 602 err = c_can_chip_config(dev); 603 if (err) 604 return err; 605 606 /* Setup the command for new messages */ 607 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ? 608 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 609 610 priv->can.state = CAN_STATE_ERROR_ACTIVE; 611 612 /* reset tx helper pointers and the rx mask */ 613 priv->tx_next = priv->tx_echo = 0; 614 priv->rxmasked = 0; 615 616 return 0; 617} 618 619static void c_can_stop(struct net_device *dev) 620{ 621 struct c_can_priv *priv = netdev_priv(dev); 622 623 c_can_irq_control(priv, false); 624 priv->can.state = CAN_STATE_STOPPED; 625} 626 627static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 628{ 629 struct c_can_priv *priv = netdev_priv(dev); 630 int err; 631 632 switch (mode) { 633 case CAN_MODE_START: 634 err = c_can_start(dev); 635 if (err) 636 return err; 637 netif_wake_queue(dev); 638 c_can_irq_control(priv, true); 639 break; 640 default: 641 return -EOPNOTSUPP; 642 } 643 644 return 0; 645} 646 647static int __c_can_get_berr_counter(const struct net_device *dev, 648 struct can_berr_counter *bec) 649{ 650 unsigned int reg_err_counter; 651 struct c_can_priv *priv = netdev_priv(dev); 652 653 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 654 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 655 ERR_CNT_REC_SHIFT; 656 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 657 658 return 0; 659} 660 661static int c_can_get_berr_counter(const struct net_device *dev, 662 struct can_berr_counter *bec) 663{ 664 struct c_can_priv *priv = netdev_priv(dev); 665 int err; 666 667 c_can_pm_runtime_get_sync(priv); 668 err = __c_can_get_berr_counter(dev, bec); 669 c_can_pm_runtime_put_sync(priv); 670 671 return err; 672} 673 674/* 675 * priv->tx_echo holds the number of the oldest can_frame put for 676 * transmission into the hardware, but not yet ACKed by the CAN tx 677 * complete IRQ. 678 * 679 * We iterate from priv->tx_echo to priv->tx_next and check if the 680 * packet has been transmitted, echo it back to the CAN framework. 681 * If we discover a not yet transmitted packet, stop looking for more. 682 */ 683static void c_can_do_tx(struct net_device *dev) 684{ 685 struct c_can_priv *priv = netdev_priv(dev); 686 struct net_device_stats *stats = &dev->stats; 687 u32 val, obj, pkts = 0, bytes = 0; 688 689 spin_lock_bh(&priv->xmit_lock); 690 691 for (; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 692 obj = get_tx_echo_msg_obj(priv->tx_echo); 693 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 694 695 if (val & (1 << (obj - 1))) 696 break; 697 698 can_get_echo_skb(dev, obj - C_CAN_MSG_OBJ_TX_FIRST); 699 bytes += priv->dlc[obj - C_CAN_MSG_OBJ_TX_FIRST]; 700 pkts++; 701 c_can_inval_msg_object(dev, IF_TX, obj); 702 } 703 704 /* restart queue if wrap-up or if queue stalled on last pkt */ 705 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 706 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) 707 netif_wake_queue(dev); 708 709 spin_unlock_bh(&priv->xmit_lock); 710 711 if (pkts) { 712 stats->tx_bytes += bytes; 713 stats->tx_packets += pkts; 714 can_led_event(dev, CAN_LED_EVENT_TX); 715 } 716} 717 718/* 719 * If we have a gap in the pending bits, that means we either 720 * raced with the hardware or failed to readout all upper 721 * objects in the last run due to quota limit. 722 */ 723static u32 c_can_adjust_pending(u32 pend) 724{ 725 u32 weight, lasts; 726 727 if (pend == RECEIVE_OBJECT_BITS) 728 return pend; 729 730 /* 731 * If the last set bit is larger than the number of pending 732 * bits we have a gap. 733 */ 734 weight = hweight32(pend); 735 lasts = fls(pend); 736 737 /* If the bits are linear, nothing to do */ 738 if (lasts == weight) 739 return pend; 740 741 /* 742 * Find the first set bit after the gap. We walk backwards 743 * from the last set bit. 744 */ 745 for (lasts--; pend & (1 << (lasts - 1)); lasts--); 746 747 return pend & ~((1 << lasts) - 1); 748} 749 750static inline void c_can_rx_object_get(struct net_device *dev, 751 struct c_can_priv *priv, u32 obj) 752{ 753#ifdef CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING 754 if (obj < C_CAN_MSG_RX_LOW_LAST) 755 c_can_object_get(dev, IF_RX, obj, IF_COMM_RCV_LOW); 756 else 757#endif 758 c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high); 759} 760 761static inline void c_can_rx_finalize(struct net_device *dev, 762 struct c_can_priv *priv, u32 obj) 763{ 764#ifdef CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING 765 if (obj < C_CAN_MSG_RX_LOW_LAST) 766 priv->rxmasked |= BIT(obj - 1); 767 else if (obj == C_CAN_MSG_RX_LOW_LAST) { 768 priv->rxmasked = 0; 769 /* activate all lower message objects */ 770 c_can_activate_all_lower_rx_msg_obj(dev, IF_RX); 771 } 772#endif 773 if (priv->type != BOSCH_D_CAN) 774 c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT); 775} 776 777static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 778 u32 pend, int quota) 779{ 780 u32 pkts = 0, ctrl, obj; 781 782 while ((obj = ffs(pend)) && quota > 0) { 783 pend &= ~BIT(obj - 1); 784 785 c_can_rx_object_get(dev, priv, obj); 786 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 787 788 if (ctrl & IF_MCONT_MSGLST) { 789 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); 790 791 pkts += n; 792 quota -= n; 793 continue; 794 } 795 796 /* 797 * This really should not happen, but this covers some 798 * odd HW behaviour. Do not remove that unless you 799 * want to brick your machine. 800 */ 801 if (!(ctrl & IF_MCONT_NEWDAT)) 802 continue; 803 804 /* read the data from the message object */ 805 c_can_read_msg_object(dev, IF_RX, ctrl); 806 807 c_can_rx_finalize(dev, priv, obj); 808 809 pkts++; 810 quota--; 811 } 812 813 return pkts; 814} 815 816static inline u32 c_can_get_pending(struct c_can_priv *priv) 817{ 818 u32 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG); 819 820#ifdef CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING 821 pend &= ~priv->rxmasked; 822#endif 823 return pend; 824} 825 826/* 827 * theory of operation: 828 * 829 * c_can core saves a received CAN message into the first free message 830 * object it finds free (starting with the lowest). Bits NEWDAT and 831 * INTPND are set for this message object indicating that a new message 832 * has arrived. To work-around this issue, we keep two groups of message 833 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 834 * 835 * If CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING = y 836 * 837 * To ensure in-order frame reception we use the following 838 * approach while re-activating a message object to receive further 839 * frames: 840 * - if the current message object number is lower than 841 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 842 * the INTPND bit. 843 * - if the current message object number is equal to 844 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 845 * receive message objects. 846 * - if the current message object number is greater than 847 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 848 * only this message object. 849 * 850 * This can cause packet loss! 851 * 852 * If CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING = n 853 * 854 * We clear the newdat bit right away. 855 * 856 * This can result in packet reordering when the readout is slow. 857 */ 858static int c_can_do_rx_poll(struct net_device *dev, int quota) 859{ 860 struct c_can_priv *priv = netdev_priv(dev); 861 u32 pkts = 0, pend = 0, toread, n; 862 863 /* 864 * It is faster to read only one 16bit register. This is only possible 865 * for a maximum number of 16 objects. 866 */ 867 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, 868 "Implementation does not support more message objects than 16"); 869 870 while (quota > 0) { 871 if (!pend) { 872 pend = c_can_get_pending(priv); 873 if (!pend) 874 break; 875 /* 876 * If the pending field has a gap, handle the 877 * bits above the gap first. 878 */ 879 toread = c_can_adjust_pending(pend); 880 } else { 881 toread = pend; 882 } 883 /* Remove the bits from pend */ 884 pend &= ~toread; 885 /* Read the objects */ 886 n = c_can_read_objects(dev, priv, toread, quota); 887 pkts += n; 888 quota -= n; 889 } 890 891 if (pkts) 892 can_led_event(dev, CAN_LED_EVENT_RX); 893 894 return pkts; 895} 896 897static int c_can_handle_state_change(struct net_device *dev, 898 enum c_can_bus_error_types error_type) 899{ 900 unsigned int reg_err_counter; 901 unsigned int rx_err_passive; 902 struct c_can_priv *priv = netdev_priv(dev); 903 struct net_device_stats *stats = &dev->stats; 904 struct can_frame *cf; 905 struct sk_buff *skb; 906 struct can_berr_counter bec; 907 908 switch (error_type) { 909 case C_CAN_ERROR_WARNING: 910 /* error warning state */ 911 priv->can.can_stats.error_warning++; 912 priv->can.state = CAN_STATE_ERROR_WARNING; 913 break; 914 case C_CAN_ERROR_PASSIVE: 915 /* error passive state */ 916 priv->can.can_stats.error_passive++; 917 priv->can.state = CAN_STATE_ERROR_PASSIVE; 918 break; 919 case C_CAN_BUS_OFF: 920 /* bus-off state */ 921 priv->can.state = CAN_STATE_BUS_OFF; 922 can_bus_off(dev); 923 break; 924 default: 925 break; 926 } 927 928 /* propagate the error condition to the CAN stack */ 929 skb = alloc_can_err_skb(dev, &cf); 930 if (unlikely(!skb)) 931 return 0; 932 933 __c_can_get_berr_counter(dev, &bec); 934 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 935 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 936 ERR_CNT_RP_SHIFT; 937 938 switch (error_type) { 939 case C_CAN_ERROR_WARNING: 940 /* error warning state */ 941 cf->can_id |= CAN_ERR_CRTL; 942 cf->data[1] = (bec.txerr > bec.rxerr) ? 943 CAN_ERR_CRTL_TX_WARNING : 944 CAN_ERR_CRTL_RX_WARNING; 945 cf->data[6] = bec.txerr; 946 cf->data[7] = bec.rxerr; 947 948 break; 949 case C_CAN_ERROR_PASSIVE: 950 /* error passive state */ 951 cf->can_id |= CAN_ERR_CRTL; 952 if (rx_err_passive) 953 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 954 if (bec.txerr > 127) 955 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 956 957 cf->data[6] = bec.txerr; 958 cf->data[7] = bec.rxerr; 959 break; 960 case C_CAN_BUS_OFF: 961 /* bus-off state */ 962 cf->can_id |= CAN_ERR_BUSOFF; 963 can_bus_off(dev); 964 break; 965 default: 966 break; 967 } 968 969 stats->rx_packets++; 970 stats->rx_bytes += cf->can_dlc; 971 netif_receive_skb(skb); 972 973 return 1; 974} 975 976static int c_can_handle_bus_err(struct net_device *dev, 977 enum c_can_lec_type lec_type) 978{ 979 struct c_can_priv *priv = netdev_priv(dev); 980 struct net_device_stats *stats = &dev->stats; 981 struct can_frame *cf; 982 struct sk_buff *skb; 983 984 /* 985 * early exit if no lec update or no error. 986 * no lec update means that no CAN bus event has been detected 987 * since CPU wrote 0x7 value to status reg. 988 */ 989 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 990 return 0; 991 992 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 993 return 0; 994 995 /* common for all type of bus errors */ 996 priv->can.can_stats.bus_error++; 997 stats->rx_errors++; 998 999 /* propagate the error condition to the CAN stack */ 1000 skb = alloc_can_err_skb(dev, &cf); 1001 if (unlikely(!skb)) 1002 return 0; 1003 1004 /* 1005 * check for 'last error code' which tells us the 1006 * type of the last error to occur on the CAN bus 1007 */ 1008 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1009 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 1010 1011 switch (lec_type) { 1012 case LEC_STUFF_ERROR: 1013 netdev_dbg(dev, "stuff error\n"); 1014 cf->data[2] |= CAN_ERR_PROT_STUFF; 1015 break; 1016 case LEC_FORM_ERROR: 1017 netdev_dbg(dev, "form error\n"); 1018 cf->data[2] |= CAN_ERR_PROT_FORM; 1019 break; 1020 case LEC_ACK_ERROR: 1021 netdev_dbg(dev, "ack error\n"); 1022 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 1023 CAN_ERR_PROT_LOC_ACK_DEL); 1024 break; 1025 case LEC_BIT1_ERROR: 1026 netdev_dbg(dev, "bit1 error\n"); 1027 cf->data[2] |= CAN_ERR_PROT_BIT1; 1028 break; 1029 case LEC_BIT0_ERROR: 1030 netdev_dbg(dev, "bit0 error\n"); 1031 cf->data[2] |= CAN_ERR_PROT_BIT0; 1032 break; 1033 case LEC_CRC_ERROR: 1034 netdev_dbg(dev, "CRC error\n"); 1035 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 1036 CAN_ERR_PROT_LOC_CRC_DEL); 1037 break; 1038 default: 1039 break; 1040 } 1041 1042 stats->rx_packets++; 1043 stats->rx_bytes += cf->can_dlc; 1044 netif_receive_skb(skb); 1045 return 1; 1046} 1047 1048static int c_can_poll(struct napi_struct *napi, int quota) 1049{ 1050 struct net_device *dev = napi->dev; 1051 struct c_can_priv *priv = netdev_priv(dev); 1052 u16 curr, last = priv->last_status; 1053 int work_done = 0; 1054 1055 priv->last_status = curr = priv->read_reg(priv, C_CAN_STS_REG); 1056 /* Ack status on C_CAN. D_CAN is self clearing */ 1057 if (priv->type != BOSCH_D_CAN) 1058 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1059 1060 /* handle state changes */ 1061 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) { 1062 netdev_dbg(dev, "entered error warning state\n"); 1063 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); 1064 } 1065 1066 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) { 1067 netdev_dbg(dev, "entered error passive state\n"); 1068 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); 1069 } 1070 1071 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) { 1072 netdev_dbg(dev, "entered bus off state\n"); 1073 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF); 1074 goto end; 1075 } 1076 1077 /* handle bus recovery events */ 1078 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) { 1079 netdev_dbg(dev, "left bus off state\n"); 1080 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1081 } 1082 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) { 1083 netdev_dbg(dev, "left error passive state\n"); 1084 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1085 } 1086 1087 /* handle lec errors on the bus */ 1088 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK); 1089 1090 /* Handle Tx/Rx events. We do this unconditionally */ 1091 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1092 c_can_do_tx(dev); 1093 1094end: 1095 if (work_done < quota) { 1096 napi_complete(napi); 1097 /* enable all IRQs if we are not in bus off state */ 1098 if (priv->can.state != CAN_STATE_BUS_OFF) 1099 c_can_irq_control(priv, true); 1100 } 1101 1102 return work_done; 1103} 1104 1105static irqreturn_t c_can_isr(int irq, void *dev_id) 1106{ 1107 struct net_device *dev = (struct net_device *)dev_id; 1108 struct c_can_priv *priv = netdev_priv(dev); 1109 1110 if (!priv->read_reg(priv, C_CAN_INT_REG)) 1111 return IRQ_NONE; 1112 1113 /* disable all interrupts and schedule the NAPI */ 1114 c_can_irq_control(priv, false); 1115 napi_schedule(&priv->napi); 1116 1117 return IRQ_HANDLED; 1118} 1119 1120static int c_can_open(struct net_device *dev) 1121{ 1122 int err; 1123 struct c_can_priv *priv = netdev_priv(dev); 1124 1125 c_can_pm_runtime_get_sync(priv); 1126 c_can_reset_ram(priv, true); 1127 1128 /* open the can device */ 1129 err = open_candev(dev); 1130 if (err) { 1131 netdev_err(dev, "failed to open can device\n"); 1132 goto exit_open_fail; 1133 } 1134 1135 /* register interrupt handler */ 1136 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1137 dev); 1138 if (err < 0) { 1139 netdev_err(dev, "failed to request interrupt\n"); 1140 goto exit_irq_fail; 1141 } 1142 1143 /* start the c_can controller */ 1144 err = c_can_start(dev); 1145 if (err) 1146 goto exit_start_fail; 1147 1148 can_led_event(dev, CAN_LED_EVENT_OPEN); 1149 1150 napi_enable(&priv->napi); 1151 /* enable status change, error and module interrupts */ 1152 c_can_irq_control(priv, true); 1153 netif_start_queue(dev); 1154 1155 return 0; 1156 1157exit_start_fail: 1158 free_irq(dev->irq, dev); 1159exit_irq_fail: 1160 close_candev(dev); 1161exit_open_fail: 1162 c_can_reset_ram(priv, false); 1163 c_can_pm_runtime_put_sync(priv); 1164 return err; 1165} 1166 1167static int c_can_close(struct net_device *dev) 1168{ 1169 struct c_can_priv *priv = netdev_priv(dev); 1170 1171 netif_stop_queue(dev); 1172 napi_disable(&priv->napi); 1173 c_can_stop(dev); 1174 free_irq(dev->irq, dev); 1175 close_candev(dev); 1176 1177 c_can_reset_ram(priv, false); 1178 c_can_pm_runtime_put_sync(priv); 1179 1180 can_led_event(dev, CAN_LED_EVENT_STOP); 1181 1182 return 0; 1183} 1184 1185struct net_device *alloc_c_can_dev(void) 1186{ 1187 struct net_device *dev; 1188 struct c_can_priv *priv; 1189 1190 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1191 if (!dev) 1192 return NULL; 1193 1194 priv = netdev_priv(dev); 1195 spin_lock_init(&priv->xmit_lock); 1196 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1197 1198 priv->dev = dev; 1199 priv->can.bittiming_const = &c_can_bittiming_const; 1200 priv->can.do_set_mode = c_can_set_mode; 1201 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1202 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1203 CAN_CTRLMODE_LISTENONLY | 1204 CAN_CTRLMODE_BERR_REPORTING; 1205 1206 return dev; 1207} 1208EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1209 1210#ifdef CONFIG_PM 1211int c_can_power_down(struct net_device *dev) 1212{ 1213 u32 val; 1214 unsigned long time_out; 1215 struct c_can_priv *priv = netdev_priv(dev); 1216 1217 if (!(dev->flags & IFF_UP)) 1218 return 0; 1219 1220 WARN_ON(priv->type != BOSCH_D_CAN); 1221 1222 /* set PDR value so the device goes to power down mode */ 1223 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1224 val |= CONTROL_EX_PDR; 1225 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1226 1227 /* Wait for the PDA bit to get set */ 1228 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1229 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1230 time_after(time_out, jiffies)) 1231 cpu_relax(); 1232 1233 if (time_after(jiffies, time_out)) 1234 return -ETIMEDOUT; 1235 1236 c_can_stop(dev); 1237 1238 c_can_reset_ram(priv, false); 1239 c_can_pm_runtime_put_sync(priv); 1240 1241 return 0; 1242} 1243EXPORT_SYMBOL_GPL(c_can_power_down); 1244 1245int c_can_power_up(struct net_device *dev) 1246{ 1247 u32 val; 1248 unsigned long time_out; 1249 struct c_can_priv *priv = netdev_priv(dev); 1250 int ret; 1251 1252 if (!(dev->flags & IFF_UP)) 1253 return 0; 1254 1255 WARN_ON(priv->type != BOSCH_D_CAN); 1256 1257 c_can_pm_runtime_get_sync(priv); 1258 c_can_reset_ram(priv, true); 1259 1260 /* Clear PDR and INIT bits */ 1261 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1262 val &= ~CONTROL_EX_PDR; 1263 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1264 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1265 val &= ~CONTROL_INIT; 1266 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1267 1268 /* Wait for the PDA bit to get clear */ 1269 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1270 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1271 time_after(time_out, jiffies)) 1272 cpu_relax(); 1273 1274 if (time_after(jiffies, time_out)) 1275 return -ETIMEDOUT; 1276 1277 ret = c_can_start(dev); 1278 if (!ret) 1279 c_can_irq_control(priv, true); 1280 1281 return ret; 1282} 1283EXPORT_SYMBOL_GPL(c_can_power_up); 1284#endif 1285 1286void free_c_can_dev(struct net_device *dev) 1287{ 1288 struct c_can_priv *priv = netdev_priv(dev); 1289 1290 netif_napi_del(&priv->napi); 1291 free_candev(dev); 1292} 1293EXPORT_SYMBOL_GPL(free_c_can_dev); 1294 1295static const struct net_device_ops c_can_netdev_ops = { 1296 .ndo_open = c_can_open, 1297 .ndo_stop = c_can_close, 1298 .ndo_start_xmit = c_can_start_xmit, 1299 .ndo_change_mtu = can_change_mtu, 1300}; 1301 1302int register_c_can_dev(struct net_device *dev) 1303{ 1304 struct c_can_priv *priv = netdev_priv(dev); 1305 int err; 1306 1307 c_can_pm_runtime_enable(priv); 1308 1309 dev->flags |= IFF_ECHO; /* we support local echo */ 1310 dev->netdev_ops = &c_can_netdev_ops; 1311 1312 err = register_candev(dev); 1313 if (err) 1314 c_can_pm_runtime_disable(priv); 1315 else 1316 devm_can_led_init(dev); 1317 1318 return err; 1319} 1320EXPORT_SYMBOL_GPL(register_c_can_dev); 1321 1322void unregister_c_can_dev(struct net_device *dev) 1323{ 1324 struct c_can_priv *priv = netdev_priv(dev); 1325 1326 unregister_candev(dev); 1327 1328 c_can_pm_runtime_disable(priv); 1329} 1330EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1331 1332MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1333MODULE_LICENSE("GPL v2"); 1334MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1335