c_can.c revision fa39b54ccf28a0a85256f04881297cd75b8ef204
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42#include <linux/can/led.h> 43 44#include "c_can.h" 45 46/* Number of interface registers */ 47#define IF_ENUM_REG_LEN 11 48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 49 50/* control extension register D_CAN specific */ 51#define CONTROL_EX_PDR BIT(8) 52 53/* control register */ 54#define CONTROL_TEST BIT(7) 55#define CONTROL_CCE BIT(6) 56#define CONTROL_DISABLE_AR BIT(5) 57#define CONTROL_ENABLE_AR (0 << 5) 58#define CONTROL_EIE BIT(3) 59#define CONTROL_SIE BIT(2) 60#define CONTROL_IE BIT(1) 61#define CONTROL_INIT BIT(0) 62 63/* test register */ 64#define TEST_RX BIT(7) 65#define TEST_TX1 BIT(6) 66#define TEST_TX2 BIT(5) 67#define TEST_LBACK BIT(4) 68#define TEST_SILENT BIT(3) 69#define TEST_BASIC BIT(2) 70 71/* status register */ 72#define STATUS_PDA BIT(10) 73#define STATUS_BOFF BIT(7) 74#define STATUS_EWARN BIT(6) 75#define STATUS_EPASS BIT(5) 76#define STATUS_RXOK BIT(4) 77#define STATUS_TXOK BIT(3) 78 79/* error counter register */ 80#define ERR_CNT_TEC_MASK 0xff 81#define ERR_CNT_TEC_SHIFT 0 82#define ERR_CNT_REC_SHIFT 8 83#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 84#define ERR_CNT_RP_SHIFT 15 85#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 86 87/* bit-timing register */ 88#define BTR_BRP_MASK 0x3f 89#define BTR_BRP_SHIFT 0 90#define BTR_SJW_SHIFT 6 91#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 92#define BTR_TSEG1_SHIFT 8 93#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 94#define BTR_TSEG2_SHIFT 12 95#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 96 97/* brp extension register */ 98#define BRP_EXT_BRPE_MASK 0x0f 99#define BRP_EXT_BRPE_SHIFT 0 100 101/* IFx command request */ 102#define IF_COMR_BUSY BIT(15) 103 104/* IFx command mask */ 105#define IF_COMM_WR BIT(7) 106#define IF_COMM_MASK BIT(6) 107#define IF_COMM_ARB BIT(5) 108#define IF_COMM_CONTROL BIT(4) 109#define IF_COMM_CLR_INT_PND BIT(3) 110#define IF_COMM_TXRQST BIT(2) 111#define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST 112#define IF_COMM_DATAA BIT(1) 113#define IF_COMM_DATAB BIT(0) 114#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ 115 IF_COMM_CONTROL | IF_COMM_TXRQST | \ 116 IF_COMM_DATAA | IF_COMM_DATAB) 117 118/* For the low buffers we clear the interrupt bit, but keep newdat */ 119#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 120 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 121 IF_COMM_DATAA | IF_COMM_DATAB) 122 123/* For the high buffers we clear the interrupt bit and newdat */ 124#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT) 125 126/* IFx arbitration */ 127#define IF_ARB_MSGVAL BIT(15) 128#define IF_ARB_MSGXTD BIT(14) 129#define IF_ARB_TRANSMIT BIT(13) 130 131/* IFx message control */ 132#define IF_MCONT_NEWDAT BIT(15) 133#define IF_MCONT_MSGLST BIT(14) 134#define IF_MCONT_INTPND BIT(13) 135#define IF_MCONT_UMASK BIT(12) 136#define IF_MCONT_TXIE BIT(11) 137#define IF_MCONT_RXIE BIT(10) 138#define IF_MCONT_RMTEN BIT(9) 139#define IF_MCONT_TXRQST BIT(8) 140#define IF_MCONT_EOB BIT(7) 141#define IF_MCONT_DLC_MASK 0xf 142 143/* 144 * Use IF1 for RX and IF2 for TX 145 */ 146#define IF_RX 0 147#define IF_TX 1 148 149/* status interrupt */ 150#define STATUS_INTERRUPT 0x8000 151 152/* global interrupt masks */ 153#define ENABLE_ALL_INTERRUPTS 1 154#define DISABLE_ALL_INTERRUPTS 0 155 156/* minimum timeout for checking BUSY status */ 157#define MIN_TIMEOUT_VALUE 6 158 159/* Wait for ~1 sec for INIT bit */ 160#define INIT_WAIT_MS 1000 161 162/* napi related */ 163#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 164 165/* c_can lec values */ 166enum c_can_lec_type { 167 LEC_NO_ERROR = 0, 168 LEC_STUFF_ERROR, 169 LEC_FORM_ERROR, 170 LEC_ACK_ERROR, 171 LEC_BIT1_ERROR, 172 LEC_BIT0_ERROR, 173 LEC_CRC_ERROR, 174 LEC_UNUSED, 175 LEC_MASK = LEC_UNUSED, 176}; 177 178/* 179 * c_can error types: 180 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 181 */ 182enum c_can_bus_error_types { 183 C_CAN_NO_ERROR = 0, 184 C_CAN_BUS_OFF, 185 C_CAN_ERROR_WARNING, 186 C_CAN_ERROR_PASSIVE, 187}; 188 189static const struct can_bittiming_const c_can_bittiming_const = { 190 .name = KBUILD_MODNAME, 191 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 192 .tseg1_max = 16, 193 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 194 .tseg2_max = 8, 195 .sjw_max = 4, 196 .brp_min = 1, 197 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 198 .brp_inc = 1, 199}; 200 201static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 202{ 203 if (priv->device) 204 pm_runtime_enable(priv->device); 205} 206 207static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 208{ 209 if (priv->device) 210 pm_runtime_disable(priv->device); 211} 212 213static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 214{ 215 if (priv->device) 216 pm_runtime_get_sync(priv->device); 217} 218 219static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 220{ 221 if (priv->device) 222 pm_runtime_put_sync(priv->device); 223} 224 225static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 226{ 227 if (priv->raminit) 228 priv->raminit(priv, enable); 229} 230 231static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 232{ 233 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + 234 C_CAN_MSG_OBJ_TX_FIRST; 235} 236 237static inline int get_tx_echo_msg_obj(int txecho) 238{ 239 return (txecho & C_CAN_NEXT_MSG_OBJ_MASK) + C_CAN_MSG_OBJ_TX_FIRST; 240} 241 242static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) 243{ 244 u32 val = priv->read_reg(priv, index); 245 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 246 return val; 247} 248 249static void c_can_enable_all_interrupts(struct c_can_priv *priv, 250 int enable) 251{ 252 unsigned int cntrl_save = priv->read_reg(priv, 253 C_CAN_CTRL_REG); 254 255 if (enable) 256 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 257 else 258 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); 259 260 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); 261} 262 263static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 264{ 265 int count = MIN_TIMEOUT_VALUE; 266 267 while (count && priv->read_reg(priv, 268 C_CAN_IFACE(COMREQ_REG, iface)) & 269 IF_COMR_BUSY) { 270 count--; 271 udelay(1); 272 } 273 274 if (!count) 275 return 1; 276 277 return 0; 278} 279 280static inline void c_can_object_get(struct net_device *dev, 281 int iface, int objno, int mask) 282{ 283 struct c_can_priv *priv = netdev_priv(dev); 284 285 /* 286 * As per specs, after writting the message object number in the 287 * IF command request register the transfer b/w interface 288 * register and message RAM must be complete in 6 CAN-CLK 289 * period. 290 */ 291 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 292 IFX_WRITE_LOW_16BIT(mask)); 293 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 294 IFX_WRITE_LOW_16BIT(objno)); 295 296 if (c_can_msg_obj_is_busy(priv, iface)) 297 netdev_err(dev, "timed out in object get\n"); 298} 299 300static inline void c_can_object_put(struct net_device *dev, 301 int iface, int objno, int mask) 302{ 303 struct c_can_priv *priv = netdev_priv(dev); 304 305 /* 306 * As per specs, after writting the message object number in the 307 * IF command request register the transfer b/w interface 308 * register and message RAM must be complete in 6 CAN-CLK 309 * period. 310 */ 311 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 312 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); 313 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 314 IFX_WRITE_LOW_16BIT(objno)); 315 316 if (c_can_msg_obj_is_busy(priv, iface)) 317 netdev_err(dev, "timed out in object put\n"); 318} 319 320static void c_can_write_msg_object(struct net_device *dev, 321 int iface, struct can_frame *frame, int objno) 322{ 323 int i; 324 u16 flags = 0; 325 unsigned int id; 326 struct c_can_priv *priv = netdev_priv(dev); 327 328 if (!(frame->can_id & CAN_RTR_FLAG)) 329 flags |= IF_ARB_TRANSMIT; 330 331 if (frame->can_id & CAN_EFF_FLAG) { 332 id = frame->can_id & CAN_EFF_MASK; 333 flags |= IF_ARB_MSGXTD; 334 } else 335 id = ((frame->can_id & CAN_SFF_MASK) << 18); 336 337 flags |= IF_ARB_MSGVAL; 338 339 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 340 IFX_WRITE_LOW_16BIT(id)); 341 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | 342 IFX_WRITE_HIGH_16BIT(id)); 343 344 for (i = 0; i < frame->can_dlc; i += 2) { 345 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 346 frame->data[i] | (frame->data[i + 1] << 8)); 347 } 348 349 /* enable interrupt for this message object */ 350 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 351 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | 352 frame->can_dlc); 353 c_can_object_put(dev, iface, objno, IF_COMM_ALL); 354} 355 356static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 357 int iface) 358{ 359 int i; 360 361 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) 362 c_can_object_get(dev, iface, i, IF_COMM_CLR_NEWDAT); 363} 364 365static int c_can_handle_lost_msg_obj(struct net_device *dev, 366 int iface, int objno, u32 ctrl) 367{ 368 struct net_device_stats *stats = &dev->stats; 369 struct c_can_priv *priv = netdev_priv(dev); 370 struct can_frame *frame; 371 struct sk_buff *skb; 372 373 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 374 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 375 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 376 377 stats->rx_errors++; 378 stats->rx_over_errors++; 379 380 /* create an error msg */ 381 skb = alloc_can_err_skb(dev, &frame); 382 if (unlikely(!skb)) 383 return 0; 384 385 frame->can_id |= CAN_ERR_CRTL; 386 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 387 388 netif_receive_skb(skb); 389 return 1; 390} 391 392static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) 393{ 394 u16 flags, data; 395 int i; 396 unsigned int val; 397 struct c_can_priv *priv = netdev_priv(dev); 398 struct net_device_stats *stats = &dev->stats; 399 struct sk_buff *skb; 400 struct can_frame *frame; 401 402 skb = alloc_can_skb(dev, &frame); 403 if (!skb) { 404 stats->rx_dropped++; 405 return -ENOMEM; 406 } 407 408 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 409 410 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); 411 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | 412 (flags << 16); 413 414 if (flags & IF_ARB_MSGXTD) 415 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; 416 else 417 frame->can_id = (val >> 18) & CAN_SFF_MASK; 418 419 if (flags & IF_ARB_TRANSMIT) 420 frame->can_id |= CAN_RTR_FLAG; 421 else { 422 for (i = 0; i < frame->can_dlc; i += 2) { 423 data = priv->read_reg(priv, 424 C_CAN_IFACE(DATA1_REG, iface) + i / 2); 425 frame->data[i] = data; 426 frame->data[i + 1] = data >> 8; 427 } 428 } 429 430 stats->rx_packets++; 431 stats->rx_bytes += frame->can_dlc; 432 433 netif_receive_skb(skb); 434 return 0; 435} 436 437static void c_can_setup_receive_object(struct net_device *dev, int iface, 438 int objno, unsigned int mask, 439 unsigned int id, unsigned int mcont) 440{ 441 struct c_can_priv *priv = netdev_priv(dev); 442 443 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), 444 IFX_WRITE_LOW_16BIT(mask)); 445 446 /* According to C_CAN documentation, the reserved bit 447 * in IFx_MASK2 register is fixed 1 448 */ 449 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), 450 IFX_WRITE_HIGH_16BIT(mask) | BIT(13)); 451 452 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 453 IFX_WRITE_LOW_16BIT(id)); 454 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 455 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); 456 457 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 458 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 459 460 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 461 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 462} 463 464static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) 465{ 466 struct c_can_priv *priv = netdev_priv(dev); 467 468 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 469 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 470 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 471 472 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); 473 474 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 475 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 476} 477 478static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 479{ 480 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 481 482 /* 483 * as transmission request register's bit n-1 corresponds to 484 * message object n, we need to handle the same properly. 485 */ 486 if (val & (1 << (objno - 1))) 487 return 1; 488 489 return 0; 490} 491 492static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 493 struct net_device *dev) 494{ 495 u32 msg_obj_no; 496 struct c_can_priv *priv = netdev_priv(dev); 497 struct can_frame *frame = (struct can_frame *)skb->data; 498 499 if (can_dropped_invalid_skb(dev, skb)) 500 return NETDEV_TX_OK; 501 502 spin_lock_bh(&priv->xmit_lock); 503 msg_obj_no = get_tx_next_msg_obj(priv); 504 505 /* prepare message object for transmission */ 506 c_can_write_msg_object(dev, IF_TX, frame, msg_obj_no); 507 priv->dlc[msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST] = frame->can_dlc; 508 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 509 510 /* 511 * we have to stop the queue in case of a wrap around or 512 * if the next TX message object is still in use 513 */ 514 priv->tx_next++; 515 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 516 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 517 netif_stop_queue(dev); 518 spin_unlock_bh(&priv->xmit_lock); 519 520 return NETDEV_TX_OK; 521} 522 523static int c_can_wait_for_ctrl_init(struct net_device *dev, 524 struct c_can_priv *priv, u32 init) 525{ 526 int retry = 0; 527 528 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 529 udelay(10); 530 if (retry++ > 1000) { 531 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 532 return -EIO; 533 } 534 } 535 return 0; 536} 537 538static int c_can_set_bittiming(struct net_device *dev) 539{ 540 unsigned int reg_btr, reg_brpe, ctrl_save; 541 u8 brp, brpe, sjw, tseg1, tseg2; 542 u32 ten_bit_brp; 543 struct c_can_priv *priv = netdev_priv(dev); 544 const struct can_bittiming *bt = &priv->can.bittiming; 545 int res; 546 547 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 548 ten_bit_brp = bt->brp - 1; 549 brp = ten_bit_brp & BTR_BRP_MASK; 550 brpe = ten_bit_brp >> 6; 551 552 sjw = bt->sjw - 1; 553 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 554 tseg2 = bt->phase_seg2 - 1; 555 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 556 (tseg2 << BTR_TSEG2_SHIFT); 557 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 558 559 netdev_info(dev, 560 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 561 562 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 563 ctrl_save &= ~CONTROL_INIT; 564 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 565 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 566 if (res) 567 return res; 568 569 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 570 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 571 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 572 573 return c_can_wait_for_ctrl_init(dev, priv, 0); 574} 575 576/* 577 * Configure C_CAN message objects for Tx and Rx purposes: 578 * C_CAN provides a total of 32 message objects that can be configured 579 * either for Tx or Rx purposes. Here the first 16 message objects are used as 580 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 581 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 582 * See user guide document for further details on configuring message 583 * objects. 584 */ 585static void c_can_configure_msg_objects(struct net_device *dev) 586{ 587 int i; 588 589 /* first invalidate all message objects */ 590 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 591 c_can_inval_msg_object(dev, IF_RX, i); 592 593 /* setup receive message objects */ 594 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 595 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, 596 IF_MCONT_RXIE | IF_MCONT_UMASK); 597 598 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 599 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); 600} 601 602/* 603 * Configure C_CAN chip: 604 * - enable/disable auto-retransmission 605 * - set operating mode 606 * - configure message objects 607 */ 608static int c_can_chip_config(struct net_device *dev) 609{ 610 struct c_can_priv *priv = netdev_priv(dev); 611 612 /* enable automatic retransmission */ 613 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); 614 615 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 616 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 617 /* loopback + silent mode : useful for hot self-test */ 618 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 619 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); 620 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 621 /* loopback mode : useful for self-test function */ 622 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 623 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 624 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 625 /* silent mode : bus-monitoring mode */ 626 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 627 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 628 } 629 630 /* configure message objects */ 631 c_can_configure_msg_objects(dev); 632 633 /* set a `lec` value so that we can check for updates later */ 634 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 635 636 /* set bittiming params */ 637 return c_can_set_bittiming(dev); 638} 639 640static int c_can_start(struct net_device *dev) 641{ 642 struct c_can_priv *priv = netdev_priv(dev); 643 int err; 644 645 /* basic c_can configuration */ 646 err = c_can_chip_config(dev); 647 if (err) 648 return err; 649 650 priv->can.state = CAN_STATE_ERROR_ACTIVE; 651 652 /* reset tx helper pointers and the rx mask */ 653 priv->tx_next = priv->tx_echo = 0; 654 priv->rxmasked = 0; 655 656 return 0; 657} 658 659static void c_can_stop(struct net_device *dev) 660{ 661 struct c_can_priv *priv = netdev_priv(dev); 662 663 /* disable all interrupts */ 664 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 665 666 /* set the state as STOPPED */ 667 priv->can.state = CAN_STATE_STOPPED; 668} 669 670static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 671{ 672 struct c_can_priv *priv = netdev_priv(dev); 673 int err; 674 675 switch (mode) { 676 case CAN_MODE_START: 677 err = c_can_start(dev); 678 if (err) 679 return err; 680 netif_wake_queue(dev); 681 /* enable status change, error and module interrupts */ 682 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 683 break; 684 default: 685 return -EOPNOTSUPP; 686 } 687 688 return 0; 689} 690 691static int __c_can_get_berr_counter(const struct net_device *dev, 692 struct can_berr_counter *bec) 693{ 694 unsigned int reg_err_counter; 695 struct c_can_priv *priv = netdev_priv(dev); 696 697 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 698 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 699 ERR_CNT_REC_SHIFT; 700 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 701 702 return 0; 703} 704 705static int c_can_get_berr_counter(const struct net_device *dev, 706 struct can_berr_counter *bec) 707{ 708 struct c_can_priv *priv = netdev_priv(dev); 709 int err; 710 711 c_can_pm_runtime_get_sync(priv); 712 err = __c_can_get_berr_counter(dev, bec); 713 c_can_pm_runtime_put_sync(priv); 714 715 return err; 716} 717 718/* 719 * priv->tx_echo holds the number of the oldest can_frame put for 720 * transmission into the hardware, but not yet ACKed by the CAN tx 721 * complete IRQ. 722 * 723 * We iterate from priv->tx_echo to priv->tx_next and check if the 724 * packet has been transmitted, echo it back to the CAN framework. 725 * If we discover a not yet transmitted packet, stop looking for more. 726 */ 727static void c_can_do_tx(struct net_device *dev) 728{ 729 struct c_can_priv *priv = netdev_priv(dev); 730 struct net_device_stats *stats = &dev->stats; 731 u32 val, obj, pkts = 0, bytes = 0; 732 733 spin_lock_bh(&priv->xmit_lock); 734 735 for (; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 736 obj = get_tx_echo_msg_obj(priv->tx_echo); 737 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 738 739 if (val & (1 << (obj - 1))) 740 break; 741 742 can_get_echo_skb(dev, obj - C_CAN_MSG_OBJ_TX_FIRST); 743 bytes += priv->dlc[obj - C_CAN_MSG_OBJ_TX_FIRST]; 744 pkts++; 745 c_can_inval_msg_object(dev, IF_TX, obj); 746 } 747 748 /* restart queue if wrap-up or if queue stalled on last pkt */ 749 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 750 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) 751 netif_wake_queue(dev); 752 753 spin_unlock_bh(&priv->xmit_lock); 754 755 if (pkts) { 756 stats->tx_bytes += bytes; 757 stats->tx_packets += pkts; 758 can_led_event(dev, CAN_LED_EVENT_TX); 759 } 760} 761 762/* 763 * If we have a gap in the pending bits, that means we either 764 * raced with the hardware or failed to readout all upper 765 * objects in the last run due to quota limit. 766 */ 767static u32 c_can_adjust_pending(u32 pend) 768{ 769 u32 weight, lasts; 770 771 if (pend == RECEIVE_OBJECT_BITS) 772 return pend; 773 774 /* 775 * If the last set bit is larger than the number of pending 776 * bits we have a gap. 777 */ 778 weight = hweight32(pend); 779 lasts = fls(pend); 780 781 /* If the bits are linear, nothing to do */ 782 if (lasts == weight) 783 return pend; 784 785 /* 786 * Find the first set bit after the gap. We walk backwards 787 * from the last set bit. 788 */ 789 for (lasts--; pend & (1 << (lasts - 1)); lasts--); 790 791 return pend & ~((1 << lasts) - 1); 792} 793 794static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 795 u32 pend, int quota) 796{ 797 u32 pkts = 0, ctrl, obj, mcmd; 798 799 while ((obj = ffs(pend)) && quota > 0) { 800 pend &= ~BIT(obj - 1); 801 802 mcmd = obj < C_CAN_MSG_RX_LOW_LAST ? 803 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 804 805 c_can_object_get(dev, IF_RX, obj, mcmd); 806 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 807 808 if (ctrl & IF_MCONT_MSGLST) { 809 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); 810 811 pkts += n; 812 quota -= n; 813 continue; 814 } 815 816 /* 817 * This really should not happen, but this covers some 818 * odd HW behaviour. Do not remove that unless you 819 * want to brick your machine. 820 */ 821 if (!(ctrl & IF_MCONT_NEWDAT)) 822 continue; 823 824 /* read the data from the message object */ 825 c_can_read_msg_object(dev, IF_RX, ctrl); 826 827 if (obj < C_CAN_MSG_RX_LOW_LAST) 828 priv->rxmasked |= BIT(obj - 1); 829 else if (obj == C_CAN_MSG_RX_LOW_LAST) { 830 priv->rxmasked = 0; 831 /* activate all lower message objects */ 832 c_can_activate_all_lower_rx_msg_obj(dev, IF_RX); 833 } 834 835 pkts++; 836 quota--; 837 } 838 839 return pkts; 840} 841 842/* 843 * theory of operation: 844 * 845 * c_can core saves a received CAN message into the first free message 846 * object it finds free (starting with the lowest). Bits NEWDAT and 847 * INTPND are set for this message object indicating that a new message 848 * has arrived. To work-around this issue, we keep two groups of message 849 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 850 * 851 * To ensure in-order frame reception we use the following 852 * approach while re-activating a message object to receive further 853 * frames: 854 * - if the current message object number is lower than 855 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 856 * the INTPND bit. 857 * - if the current message object number is equal to 858 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 859 * receive message objects. 860 * - if the current message object number is greater than 861 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 862 * only this message object. 863 */ 864static int c_can_do_rx_poll(struct net_device *dev, int quota) 865{ 866 struct c_can_priv *priv = netdev_priv(dev); 867 u32 pkts = 0, pend = 0, toread, n; 868 869 /* 870 * It is faster to read only one 16bit register. This is only possible 871 * for a maximum number of 16 objects. 872 */ 873 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, 874 "Implementation does not support more message objects than 16"); 875 876 while (quota > 0) { 877 if (!pend) { 878 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG); 879 pend &= ~priv->rxmasked; 880 if (!pend) 881 break; 882 /* 883 * If the pending field has a gap, handle the 884 * bits above the gap first. 885 */ 886 toread = c_can_adjust_pending(pend); 887 } else { 888 toread = pend; 889 } 890 /* Remove the bits from pend */ 891 pend &= ~toread; 892 /* Read the objects */ 893 n = c_can_read_objects(dev, priv, toread, quota); 894 pkts += n; 895 quota -= n; 896 } 897 898 if (pkts) 899 can_led_event(dev, CAN_LED_EVENT_RX); 900 901 return pkts; 902} 903 904static int c_can_handle_state_change(struct net_device *dev, 905 enum c_can_bus_error_types error_type) 906{ 907 unsigned int reg_err_counter; 908 unsigned int rx_err_passive; 909 struct c_can_priv *priv = netdev_priv(dev); 910 struct net_device_stats *stats = &dev->stats; 911 struct can_frame *cf; 912 struct sk_buff *skb; 913 struct can_berr_counter bec; 914 915 switch (error_type) { 916 case C_CAN_ERROR_WARNING: 917 /* error warning state */ 918 priv->can.can_stats.error_warning++; 919 priv->can.state = CAN_STATE_ERROR_WARNING; 920 break; 921 case C_CAN_ERROR_PASSIVE: 922 /* error passive state */ 923 priv->can.can_stats.error_passive++; 924 priv->can.state = CAN_STATE_ERROR_PASSIVE; 925 break; 926 case C_CAN_BUS_OFF: 927 /* bus-off state */ 928 priv->can.state = CAN_STATE_BUS_OFF; 929 can_bus_off(dev); 930 break; 931 default: 932 break; 933 } 934 935 /* propagate the error condition to the CAN stack */ 936 skb = alloc_can_err_skb(dev, &cf); 937 if (unlikely(!skb)) 938 return 0; 939 940 __c_can_get_berr_counter(dev, &bec); 941 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 942 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 943 ERR_CNT_RP_SHIFT; 944 945 switch (error_type) { 946 case C_CAN_ERROR_WARNING: 947 /* error warning state */ 948 cf->can_id |= CAN_ERR_CRTL; 949 cf->data[1] = (bec.txerr > bec.rxerr) ? 950 CAN_ERR_CRTL_TX_WARNING : 951 CAN_ERR_CRTL_RX_WARNING; 952 cf->data[6] = bec.txerr; 953 cf->data[7] = bec.rxerr; 954 955 break; 956 case C_CAN_ERROR_PASSIVE: 957 /* error passive state */ 958 cf->can_id |= CAN_ERR_CRTL; 959 if (rx_err_passive) 960 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 961 if (bec.txerr > 127) 962 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 963 964 cf->data[6] = bec.txerr; 965 cf->data[7] = bec.rxerr; 966 break; 967 case C_CAN_BUS_OFF: 968 /* bus-off state */ 969 cf->can_id |= CAN_ERR_BUSOFF; 970 can_bus_off(dev); 971 break; 972 default: 973 break; 974 } 975 976 stats->rx_packets++; 977 stats->rx_bytes += cf->can_dlc; 978 netif_receive_skb(skb); 979 980 return 1; 981} 982 983static int c_can_handle_bus_err(struct net_device *dev, 984 enum c_can_lec_type lec_type) 985{ 986 struct c_can_priv *priv = netdev_priv(dev); 987 struct net_device_stats *stats = &dev->stats; 988 struct can_frame *cf; 989 struct sk_buff *skb; 990 991 /* 992 * early exit if no lec update or no error. 993 * no lec update means that no CAN bus event has been detected 994 * since CPU wrote 0x7 value to status reg. 995 */ 996 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 997 return 0; 998 999 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 1000 return 0; 1001 1002 /* common for all type of bus errors */ 1003 priv->can.can_stats.bus_error++; 1004 stats->rx_errors++; 1005 1006 /* propagate the error condition to the CAN stack */ 1007 skb = alloc_can_err_skb(dev, &cf); 1008 if (unlikely(!skb)) 1009 return 0; 1010 1011 /* 1012 * check for 'last error code' which tells us the 1013 * type of the last error to occur on the CAN bus 1014 */ 1015 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1016 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 1017 1018 switch (lec_type) { 1019 case LEC_STUFF_ERROR: 1020 netdev_dbg(dev, "stuff error\n"); 1021 cf->data[2] |= CAN_ERR_PROT_STUFF; 1022 break; 1023 case LEC_FORM_ERROR: 1024 netdev_dbg(dev, "form error\n"); 1025 cf->data[2] |= CAN_ERR_PROT_FORM; 1026 break; 1027 case LEC_ACK_ERROR: 1028 netdev_dbg(dev, "ack error\n"); 1029 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 1030 CAN_ERR_PROT_LOC_ACK_DEL); 1031 break; 1032 case LEC_BIT1_ERROR: 1033 netdev_dbg(dev, "bit1 error\n"); 1034 cf->data[2] |= CAN_ERR_PROT_BIT1; 1035 break; 1036 case LEC_BIT0_ERROR: 1037 netdev_dbg(dev, "bit0 error\n"); 1038 cf->data[2] |= CAN_ERR_PROT_BIT0; 1039 break; 1040 case LEC_CRC_ERROR: 1041 netdev_dbg(dev, "CRC error\n"); 1042 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 1043 CAN_ERR_PROT_LOC_CRC_DEL); 1044 break; 1045 default: 1046 break; 1047 } 1048 1049 stats->rx_packets++; 1050 stats->rx_bytes += cf->can_dlc; 1051 netif_receive_skb(skb); 1052 return 1; 1053} 1054 1055static int c_can_poll(struct napi_struct *napi, int quota) 1056{ 1057 struct net_device *dev = napi->dev; 1058 struct c_can_priv *priv = netdev_priv(dev); 1059 u16 curr, last = priv->last_status; 1060 int work_done = 0; 1061 1062 priv->last_status = curr = priv->read_reg(priv, C_CAN_STS_REG); 1063 /* Ack status on C_CAN. D_CAN is self clearing */ 1064 if (priv->type != BOSCH_D_CAN) 1065 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1066 1067 /* handle state changes */ 1068 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) { 1069 netdev_dbg(dev, "entered error warning state\n"); 1070 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); 1071 } 1072 1073 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) { 1074 netdev_dbg(dev, "entered error passive state\n"); 1075 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); 1076 } 1077 1078 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) { 1079 netdev_dbg(dev, "entered bus off state\n"); 1080 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF); 1081 goto end; 1082 } 1083 1084 /* handle bus recovery events */ 1085 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) { 1086 netdev_dbg(dev, "left bus off state\n"); 1087 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1088 } 1089 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) { 1090 netdev_dbg(dev, "left error passive state\n"); 1091 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1092 } 1093 1094 /* handle lec errors on the bus */ 1095 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK); 1096 1097 /* Handle Tx/Rx events. We do this unconditionally */ 1098 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1099 c_can_do_tx(dev); 1100 1101end: 1102 if (work_done < quota) { 1103 napi_complete(napi); 1104 /* enable all IRQs if we are not in bus off state */ 1105 if (priv->can.state != CAN_STATE_BUS_OFF) 1106 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1107 } 1108 1109 return work_done; 1110} 1111 1112static irqreturn_t c_can_isr(int irq, void *dev_id) 1113{ 1114 struct net_device *dev = (struct net_device *)dev_id; 1115 struct c_can_priv *priv = netdev_priv(dev); 1116 1117 if (!priv->read_reg(priv, C_CAN_INT_REG)) 1118 return IRQ_NONE; 1119 1120 /* disable all interrupts and schedule the NAPI */ 1121 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1122 napi_schedule(&priv->napi); 1123 1124 return IRQ_HANDLED; 1125} 1126 1127static int c_can_open(struct net_device *dev) 1128{ 1129 int err; 1130 struct c_can_priv *priv = netdev_priv(dev); 1131 1132 c_can_pm_runtime_get_sync(priv); 1133 c_can_reset_ram(priv, true); 1134 1135 /* open the can device */ 1136 err = open_candev(dev); 1137 if (err) { 1138 netdev_err(dev, "failed to open can device\n"); 1139 goto exit_open_fail; 1140 } 1141 1142 /* register interrupt handler */ 1143 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1144 dev); 1145 if (err < 0) { 1146 netdev_err(dev, "failed to request interrupt\n"); 1147 goto exit_irq_fail; 1148 } 1149 1150 /* start the c_can controller */ 1151 err = c_can_start(dev); 1152 if (err) 1153 goto exit_start_fail; 1154 1155 can_led_event(dev, CAN_LED_EVENT_OPEN); 1156 1157 napi_enable(&priv->napi); 1158 /* enable status change, error and module interrupts */ 1159 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1160 netif_start_queue(dev); 1161 1162 return 0; 1163 1164exit_start_fail: 1165 free_irq(dev->irq, dev); 1166exit_irq_fail: 1167 close_candev(dev); 1168exit_open_fail: 1169 c_can_reset_ram(priv, false); 1170 c_can_pm_runtime_put_sync(priv); 1171 return err; 1172} 1173 1174static int c_can_close(struct net_device *dev) 1175{ 1176 struct c_can_priv *priv = netdev_priv(dev); 1177 1178 netif_stop_queue(dev); 1179 napi_disable(&priv->napi); 1180 c_can_stop(dev); 1181 free_irq(dev->irq, dev); 1182 close_candev(dev); 1183 1184 c_can_reset_ram(priv, false); 1185 c_can_pm_runtime_put_sync(priv); 1186 1187 can_led_event(dev, CAN_LED_EVENT_STOP); 1188 1189 return 0; 1190} 1191 1192struct net_device *alloc_c_can_dev(void) 1193{ 1194 struct net_device *dev; 1195 struct c_can_priv *priv; 1196 1197 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1198 if (!dev) 1199 return NULL; 1200 1201 priv = netdev_priv(dev); 1202 spin_lock_init(&priv->xmit_lock); 1203 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1204 1205 priv->dev = dev; 1206 priv->can.bittiming_const = &c_can_bittiming_const; 1207 priv->can.do_set_mode = c_can_set_mode; 1208 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1209 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1210 CAN_CTRLMODE_LISTENONLY | 1211 CAN_CTRLMODE_BERR_REPORTING; 1212 1213 return dev; 1214} 1215EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1216 1217#ifdef CONFIG_PM 1218int c_can_power_down(struct net_device *dev) 1219{ 1220 u32 val; 1221 unsigned long time_out; 1222 struct c_can_priv *priv = netdev_priv(dev); 1223 1224 if (!(dev->flags & IFF_UP)) 1225 return 0; 1226 1227 WARN_ON(priv->type != BOSCH_D_CAN); 1228 1229 /* set PDR value so the device goes to power down mode */ 1230 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1231 val |= CONTROL_EX_PDR; 1232 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1233 1234 /* Wait for the PDA bit to get set */ 1235 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1236 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1237 time_after(time_out, jiffies)) 1238 cpu_relax(); 1239 1240 if (time_after(jiffies, time_out)) 1241 return -ETIMEDOUT; 1242 1243 c_can_stop(dev); 1244 1245 c_can_reset_ram(priv, false); 1246 c_can_pm_runtime_put_sync(priv); 1247 1248 return 0; 1249} 1250EXPORT_SYMBOL_GPL(c_can_power_down); 1251 1252int c_can_power_up(struct net_device *dev) 1253{ 1254 u32 val; 1255 unsigned long time_out; 1256 struct c_can_priv *priv = netdev_priv(dev); 1257 int ret; 1258 1259 if (!(dev->flags & IFF_UP)) 1260 return 0; 1261 1262 WARN_ON(priv->type != BOSCH_D_CAN); 1263 1264 c_can_pm_runtime_get_sync(priv); 1265 c_can_reset_ram(priv, true); 1266 1267 /* Clear PDR and INIT bits */ 1268 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1269 val &= ~CONTROL_EX_PDR; 1270 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1271 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1272 val &= ~CONTROL_INIT; 1273 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1274 1275 /* Wait for the PDA bit to get clear */ 1276 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1277 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1278 time_after(time_out, jiffies)) 1279 cpu_relax(); 1280 1281 if (time_after(jiffies, time_out)) 1282 return -ETIMEDOUT; 1283 1284 ret = c_can_start(dev); 1285 if (!ret) 1286 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1287 1288 return ret; 1289} 1290EXPORT_SYMBOL_GPL(c_can_power_up); 1291#endif 1292 1293void free_c_can_dev(struct net_device *dev) 1294{ 1295 struct c_can_priv *priv = netdev_priv(dev); 1296 1297 netif_napi_del(&priv->napi); 1298 free_candev(dev); 1299} 1300EXPORT_SYMBOL_GPL(free_c_can_dev); 1301 1302static const struct net_device_ops c_can_netdev_ops = { 1303 .ndo_open = c_can_open, 1304 .ndo_stop = c_can_close, 1305 .ndo_start_xmit = c_can_start_xmit, 1306 .ndo_change_mtu = can_change_mtu, 1307}; 1308 1309int register_c_can_dev(struct net_device *dev) 1310{ 1311 struct c_can_priv *priv = netdev_priv(dev); 1312 int err; 1313 1314 c_can_pm_runtime_enable(priv); 1315 1316 dev->flags |= IFF_ECHO; /* we support local echo */ 1317 dev->netdev_ops = &c_can_netdev_ops; 1318 1319 err = register_candev(dev); 1320 if (err) 1321 c_can_pm_runtime_disable(priv); 1322 else 1323 devm_can_led_init(dev); 1324 1325 return err; 1326} 1327EXPORT_SYMBOL_GPL(register_c_can_dev); 1328 1329void unregister_c_can_dev(struct net_device *dev) 1330{ 1331 struct c_can_priv *priv = netdev_priv(dev); 1332 1333 unregister_candev(dev); 1334 1335 c_can_pm_runtime_disable(priv); 1336} 1337EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1338 1339MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1340MODULE_LICENSE("GPL v2"); 1341MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1342