c_can_platform.c revision a7380db5f0d6dd94981e73da08d8fa863ee72235 
1/*
2 * Platform CAN bus driver for Bosch C_CAN controller
3 *
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
6 *
7 * Borrowed heavily from the C_CAN driver originally written by:
8 * Copyright (C) 2007
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
11 *
12 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
13 * Bosch C_CAN user manual can be obtained from:
14 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
15 * users_manual_c_can.pdf
16 *
17 * This file is licensed under the terms of the GNU General Public
18 * License version 2. This program is licensed "as is" without any
19 * warranty of any kind, whether express or implied.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/netdevice.h>
27#include <linux/if_arp.h>
28#include <linux/if_ether.h>
29#include <linux/list.h>
30#include <linux/io.h>
31#include <linux/platform_device.h>
32#include <linux/clk.h>
33#include <linux/of.h>
34#include <linux/of_device.h>
35
36#include <linux/can/dev.h>
37
38#include "c_can.h"
39
40#define CAN_RAMINIT_START_MASK(i)	(0x001 << (i))
41#define CAN_RAMINIT_DONE_MASK(i)	(0x100 << (i))
42#define CAN_RAMINIT_ALL_MASK(i)		(0x101 << (i))
43#define DCAN_RAM_INIT_BIT		(1 << 3)
44static DEFINE_SPINLOCK(raminit_lock);
45/*
46 * 16-bit c_can registers can be arranged differently in the memory
47 * architecture of different implementations. For example: 16-bit
48 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
49 * Handle the same by providing a common read/write interface.
50 */
51static u16 c_can_plat_read_reg_aligned_to_16bit(const struct c_can_priv *priv,
52						enum reg index)
53{
54	return readw(priv->base + priv->regs[index]);
55}
56
57static void c_can_plat_write_reg_aligned_to_16bit(const struct c_can_priv *priv,
58						enum reg index, u16 val)
59{
60	writew(val, priv->base + priv->regs[index]);
61}
62
63static u16 c_can_plat_read_reg_aligned_to_32bit(const struct c_can_priv *priv,
64						enum reg index)
65{
66	return readw(priv->base + 2 * priv->regs[index]);
67}
68
69static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
70						enum reg index, u16 val)
71{
72	writew(val, priv->base + 2 * priv->regs[index]);
73}
74
75static void c_can_hw_raminit_wait_ti(const struct c_can_priv *priv, u32 mask,
76				  u32 val)
77{
78	/* We look only at the bits of our instance. */
79	val &= mask;
80	while ((readl(priv->raminit_ctrlreg) & mask) != val)
81		udelay(1);
82}
83
84static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)
85{
86	u32 mask = CAN_RAMINIT_ALL_MASK(priv->instance);
87	u32 ctrl;
88
89	spin_lock(&raminit_lock);
90
91	ctrl = readl(priv->raminit_ctrlreg);
92	/* We clear the done and start bit first. The start bit is
93	 * looking at the 0 -> transition, but is not self clearing;
94	 * And we clear the init done bit as well.
95	 */
96	ctrl &= ~CAN_RAMINIT_START_MASK(priv->instance);
97	ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
98	writel(ctrl, priv->raminit_ctrlreg);
99	ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance);
100	c_can_hw_raminit_wait_ti(priv, mask, ctrl);
101
102	if (enable) {
103		/* Set start bit and wait for the done bit. */
104		ctrl |= CAN_RAMINIT_START_MASK(priv->instance);
105		writel(ctrl, priv->raminit_ctrlreg);
106		ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
107		c_can_hw_raminit_wait_ti(priv, mask, ctrl);
108	}
109	spin_unlock(&raminit_lock);
110}
111
112static u32 c_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
113{
114	u32 val;
115
116	val = priv->read_reg(priv, index);
117	val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
118
119	return val;
120}
121
122static void c_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index,
123		u32 val)
124{
125	priv->write_reg(priv, index + 1, val >> 16);
126	priv->write_reg(priv, index, val);
127}
128
129static u32 d_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
130{
131	return readl(priv->base + priv->regs[index]);
132}
133
134static void d_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index,
135		u32 val)
136{
137	writel(val, priv->base + priv->regs[index]);
138}
139
140static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask)
141{
142	while (priv->read_reg32(priv, C_CAN_FUNCTION_REG) & mask)
143		udelay(1);
144}
145
146static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable)
147{
148	u32 ctrl;
149
150	ctrl = priv->read_reg32(priv, C_CAN_FUNCTION_REG);
151	ctrl &= ~DCAN_RAM_INIT_BIT;
152	priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
153	c_can_hw_raminit_wait(priv, ctrl);
154
155	if (enable) {
156		ctrl |= DCAN_RAM_INIT_BIT;
157		priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
158		c_can_hw_raminit_wait(priv, ctrl);
159	}
160}
161
162static struct platform_device_id c_can_id_table[] = {
163	[BOSCH_C_CAN_PLATFORM] = {
164		.name = KBUILD_MODNAME,
165		.driver_data = BOSCH_C_CAN,
166	},
167	[BOSCH_C_CAN] = {
168		.name = "c_can",
169		.driver_data = BOSCH_C_CAN,
170	},
171	[BOSCH_D_CAN] = {
172		.name = "d_can",
173		.driver_data = BOSCH_D_CAN,
174	}, {
175	}
176};
177MODULE_DEVICE_TABLE(platform, c_can_id_table);
178
179static const struct of_device_id c_can_of_table[] = {
180	{ .compatible = "bosch,c_can", .data = &c_can_id_table[BOSCH_C_CAN] },
181	{ .compatible = "bosch,d_can", .data = &c_can_id_table[BOSCH_D_CAN] },
182	{ /* sentinel */ },
183};
184MODULE_DEVICE_TABLE(of, c_can_of_table);
185
186static int c_can_plat_probe(struct platform_device *pdev)
187{
188	int ret;
189	void __iomem *addr;
190	struct net_device *dev;
191	struct c_can_priv *priv;
192	const struct of_device_id *match;
193	const struct platform_device_id *id;
194	struct resource *mem, *res;
195	int irq;
196	struct clk *clk;
197
198	if (pdev->dev.of_node) {
199		match = of_match_device(c_can_of_table, &pdev->dev);
200		if (!match) {
201			dev_err(&pdev->dev, "Failed to find matching dt id\n");
202			ret = -EINVAL;
203			goto exit;
204		}
205		id = match->data;
206	} else {
207		id = platform_get_device_id(pdev);
208	}
209
210	/* get the appropriate clk */
211	clk = devm_clk_get(&pdev->dev, NULL);
212	if (IS_ERR(clk)) {
213		ret = PTR_ERR(clk);
214		goto exit;
215	}
216
217	/* get the platform data */
218	irq = platform_get_irq(pdev, 0);
219	if (irq <= 0) {
220		ret = -ENODEV;
221		goto exit;
222	}
223
224	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
225	addr = devm_ioremap_resource(&pdev->dev, mem);
226	if (IS_ERR(addr)) {
227		ret =  PTR_ERR(addr);
228		goto exit;
229	}
230
231	/* allocate the c_can device */
232	dev = alloc_c_can_dev();
233	if (!dev) {
234		ret = -ENOMEM;
235		goto exit;
236	}
237
238	priv = netdev_priv(dev);
239	switch (id->driver_data) {
240	case BOSCH_C_CAN:
241		priv->regs = reg_map_c_can;
242		switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) {
243		case IORESOURCE_MEM_32BIT:
244			priv->read_reg = c_can_plat_read_reg_aligned_to_32bit;
245			priv->write_reg = c_can_plat_write_reg_aligned_to_32bit;
246			priv->read_reg32 = c_can_plat_read_reg32;
247			priv->write_reg32 = c_can_plat_write_reg32;
248			break;
249		case IORESOURCE_MEM_16BIT:
250		default:
251			priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
252			priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
253			priv->read_reg32 = c_can_plat_read_reg32;
254			priv->write_reg32 = c_can_plat_write_reg32;
255			break;
256		}
257		break;
258	case BOSCH_D_CAN:
259		priv->regs = reg_map_d_can;
260		priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
261		priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
262		priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
263		priv->read_reg32 = d_can_plat_read_reg32;
264		priv->write_reg32 = d_can_plat_write_reg32;
265
266		if (pdev->dev.of_node)
267			priv->instance = of_alias_get_id(pdev->dev.of_node, "d_can");
268		else
269			priv->instance = pdev->id;
270
271		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
272		/* Not all D_CAN modules have a separate register for the D_CAN
273		 * RAM initialization. Use default RAM init bit in D_CAN module
274		 * if not specified in DT.
275		 */
276		if (!res) {
277			priv->raminit = c_can_hw_raminit;
278			break;
279		}
280
281		priv->raminit_ctrlreg = devm_ioremap(&pdev->dev, res->start,
282						     resource_size(res));
283		if (!priv->raminit_ctrlreg || priv->instance < 0)
284			dev_info(&pdev->dev, "control memory is not used for raminit\n");
285		else
286			priv->raminit = c_can_hw_raminit_ti;
287		break;
288	default:
289		ret = -EINVAL;
290		goto exit_free_device;
291	}
292
293	dev->irq = irq;
294	priv->base = addr;
295	priv->device = &pdev->dev;
296	priv->can.clock.freq = clk_get_rate(clk);
297	priv->priv = clk;
298	priv->type = id->driver_data;
299
300	platform_set_drvdata(pdev, dev);
301	SET_NETDEV_DEV(dev, &pdev->dev);
302
303	ret = register_c_can_dev(dev);
304	if (ret) {
305		dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
306			KBUILD_MODNAME, ret);
307		goto exit_free_device;
308	}
309
310	dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
311		 KBUILD_MODNAME, priv->base, dev->irq);
312	return 0;
313
314exit_free_device:
315	free_c_can_dev(dev);
316exit:
317	dev_err(&pdev->dev, "probe failed\n");
318
319	return ret;
320}
321
322static int c_can_plat_remove(struct platform_device *pdev)
323{
324	struct net_device *dev = platform_get_drvdata(pdev);
325
326	unregister_c_can_dev(dev);
327
328	free_c_can_dev(dev);
329
330	return 0;
331}
332
333#ifdef CONFIG_PM
334static int c_can_suspend(struct platform_device *pdev, pm_message_t state)
335{
336	int ret;
337	struct net_device *ndev = platform_get_drvdata(pdev);
338	struct c_can_priv *priv = netdev_priv(ndev);
339
340	if (priv->type != BOSCH_D_CAN) {
341		dev_warn(&pdev->dev, "Not supported\n");
342		return 0;
343	}
344
345	if (netif_running(ndev)) {
346		netif_stop_queue(ndev);
347		netif_device_detach(ndev);
348	}
349
350	ret = c_can_power_down(ndev);
351	if (ret) {
352		netdev_err(ndev, "failed to enter power down mode\n");
353		return ret;
354	}
355
356	priv->can.state = CAN_STATE_SLEEPING;
357
358	return 0;
359}
360
361static int c_can_resume(struct platform_device *pdev)
362{
363	int ret;
364	struct net_device *ndev = platform_get_drvdata(pdev);
365	struct c_can_priv *priv = netdev_priv(ndev);
366
367	if (priv->type != BOSCH_D_CAN) {
368		dev_warn(&pdev->dev, "Not supported\n");
369		return 0;
370	}
371
372	ret = c_can_power_up(ndev);
373	if (ret) {
374		netdev_err(ndev, "Still in power down mode\n");
375		return ret;
376	}
377
378	priv->can.state = CAN_STATE_ERROR_ACTIVE;
379
380	if (netif_running(ndev)) {
381		netif_device_attach(ndev);
382		netif_start_queue(ndev);
383	}
384
385	return 0;
386}
387#else
388#define c_can_suspend NULL
389#define c_can_resume NULL
390#endif
391
392static struct platform_driver c_can_plat_driver = {
393	.driver = {
394		.name = KBUILD_MODNAME,
395		.owner = THIS_MODULE,
396		.of_match_table = c_can_of_table,
397	},
398	.probe = c_can_plat_probe,
399	.remove = c_can_plat_remove,
400	.suspend = c_can_suspend,
401	.resume = c_can_resume,
402	.id_table = c_can_id_table,
403};
404
405module_platform_driver(c_can_plat_driver);
406
407MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
408MODULE_LICENSE("GPL v2");
409MODULE_DESCRIPTION("Platform CAN bus driver for Bosch C_CAN controller");
410