flexcan.c revision 0e4b949e6620689b1d3142e20bca2c9d1f918fda
1/* 2 * flexcan.c - FLEXCAN CAN controller driver 3 * 4 * Copyright (c) 2005-2006 Varma Electronics Oy 5 * Copyright (c) 2009 Sascha Hauer, Pengutronix 6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix 7 * 8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com> 9 * 10 * LICENCE: 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22#include <linux/netdevice.h> 23#include <linux/can.h> 24#include <linux/can/dev.h> 25#include <linux/can/error.h> 26#include <linux/can/led.h> 27#include <linux/clk.h> 28#include <linux/delay.h> 29#include <linux/if_arp.h> 30#include <linux/if_ether.h> 31#include <linux/interrupt.h> 32#include <linux/io.h> 33#include <linux/kernel.h> 34#include <linux/list.h> 35#include <linux/module.h> 36#include <linux/of.h> 37#include <linux/of_device.h> 38#include <linux/platform_device.h> 39#include <linux/regulator/consumer.h> 40 41#define DRV_NAME "flexcan" 42 43/* 8 for RX fifo and 2 error handling */ 44#define FLEXCAN_NAPI_WEIGHT (8 + 2) 45 46/* FLEXCAN module configuration register (CANMCR) bits */ 47#define FLEXCAN_MCR_MDIS BIT(31) 48#define FLEXCAN_MCR_FRZ BIT(30) 49#define FLEXCAN_MCR_FEN BIT(29) 50#define FLEXCAN_MCR_HALT BIT(28) 51#define FLEXCAN_MCR_NOT_RDY BIT(27) 52#define FLEXCAN_MCR_WAK_MSK BIT(26) 53#define FLEXCAN_MCR_SOFTRST BIT(25) 54#define FLEXCAN_MCR_FRZ_ACK BIT(24) 55#define FLEXCAN_MCR_SUPV BIT(23) 56#define FLEXCAN_MCR_SLF_WAK BIT(22) 57#define FLEXCAN_MCR_WRN_EN BIT(21) 58#define FLEXCAN_MCR_LPM_ACK BIT(20) 59#define FLEXCAN_MCR_WAK_SRC BIT(19) 60#define FLEXCAN_MCR_DOZE BIT(18) 61#define FLEXCAN_MCR_SRX_DIS BIT(17) 62#define FLEXCAN_MCR_BCC BIT(16) 63#define FLEXCAN_MCR_LPRIO_EN BIT(13) 64#define FLEXCAN_MCR_AEN BIT(12) 65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f) 66#define FLEXCAN_MCR_IDAM_A (0 << 8) 67#define FLEXCAN_MCR_IDAM_B (1 << 8) 68#define FLEXCAN_MCR_IDAM_C (2 << 8) 69#define FLEXCAN_MCR_IDAM_D (3 << 8) 70 71/* FLEXCAN control register (CANCTRL) bits */ 72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 76#define FLEXCAN_CTRL_BOFF_MSK BIT(15) 77#define FLEXCAN_CTRL_ERR_MSK BIT(14) 78#define FLEXCAN_CTRL_CLK_SRC BIT(13) 79#define FLEXCAN_CTRL_LPB BIT(12) 80#define FLEXCAN_CTRL_TWRN_MSK BIT(11) 81#define FLEXCAN_CTRL_RWRN_MSK BIT(10) 82#define FLEXCAN_CTRL_SMP BIT(7) 83#define FLEXCAN_CTRL_BOFF_REC BIT(6) 84#define FLEXCAN_CTRL_TSYN BIT(5) 85#define FLEXCAN_CTRL_LBUF BIT(4) 86#define FLEXCAN_CTRL_LOM BIT(3) 87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 89#define FLEXCAN_CTRL_ERR_STATE \ 90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 91 FLEXCAN_CTRL_BOFF_MSK) 92#define FLEXCAN_CTRL_ERR_ALL \ 93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 94 95/* FLEXCAN error and status register (ESR) bits */ 96#define FLEXCAN_ESR_TWRN_INT BIT(17) 97#define FLEXCAN_ESR_RWRN_INT BIT(16) 98#define FLEXCAN_ESR_BIT1_ERR BIT(15) 99#define FLEXCAN_ESR_BIT0_ERR BIT(14) 100#define FLEXCAN_ESR_ACK_ERR BIT(13) 101#define FLEXCAN_ESR_CRC_ERR BIT(12) 102#define FLEXCAN_ESR_FRM_ERR BIT(11) 103#define FLEXCAN_ESR_STF_ERR BIT(10) 104#define FLEXCAN_ESR_TX_WRN BIT(9) 105#define FLEXCAN_ESR_RX_WRN BIT(8) 106#define FLEXCAN_ESR_IDLE BIT(7) 107#define FLEXCAN_ESR_TXRX BIT(6) 108#define FLEXCAN_EST_FLT_CONF_SHIFT (4) 109#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 110#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 111#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 112#define FLEXCAN_ESR_BOFF_INT BIT(2) 113#define FLEXCAN_ESR_ERR_INT BIT(1) 114#define FLEXCAN_ESR_WAK_INT BIT(0) 115#define FLEXCAN_ESR_ERR_BUS \ 116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 119#define FLEXCAN_ESR_ERR_STATE \ 120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 121#define FLEXCAN_ESR_ERR_ALL \ 122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 123#define FLEXCAN_ESR_ALL_INT \ 124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ 125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) 126 127/* FLEXCAN interrupt flag register (IFLAG) bits */ 128#define FLEXCAN_TX_BUF_ID 8 129#define FLEXCAN_IFLAG_BUF(x) BIT(x) 130#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 131#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 132#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 133#define FLEXCAN_IFLAG_DEFAULT \ 134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ 135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) 136 137/* FLEXCAN message buffers */ 138#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) 139#define FLEXCAN_MB_CNT_SRR BIT(22) 140#define FLEXCAN_MB_CNT_IDE BIT(21) 141#define FLEXCAN_MB_CNT_RTR BIT(20) 142#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 143#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 144 145#define FLEXCAN_MB_CODE_MASK (0xf0ffffff) 146 147/* 148 * FLEXCAN hardware feature flags 149 * 150 * Below is some version info we got: 151 * SOC Version IP-Version Glitch- [TR]WRN_INT 152 * Filter? connected? 153 * MX25 FlexCAN2 03.00.00.00 no no 154 * MX28 FlexCAN2 03.00.04.00 yes yes 155 * MX35 FlexCAN2 03.00.00.00 no no 156 * MX53 FlexCAN2 03.00.00.00 yes no 157 * MX6s FlexCAN3 10.00.12.00 yes yes 158 * 159 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected. 160 */ 161#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */ 162#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */ 163 164/* Structure of the message buffer */ 165struct flexcan_mb { 166 u32 can_ctrl; 167 u32 can_id; 168 u32 data[2]; 169}; 170 171/* Structure of the hardware registers */ 172struct flexcan_regs { 173 u32 mcr; /* 0x00 */ 174 u32 ctrl; /* 0x04 */ 175 u32 timer; /* 0x08 */ 176 u32 _reserved1; /* 0x0c */ 177 u32 rxgmask; /* 0x10 */ 178 u32 rx14mask; /* 0x14 */ 179 u32 rx15mask; /* 0x18 */ 180 u32 ecr; /* 0x1c */ 181 u32 esr; /* 0x20 */ 182 u32 imask2; /* 0x24 */ 183 u32 imask1; /* 0x28 */ 184 u32 iflag2; /* 0x2c */ 185 u32 iflag1; /* 0x30 */ 186 u32 crl2; /* 0x34 */ 187 u32 esr2; /* 0x38 */ 188 u32 imeur; /* 0x3c */ 189 u32 lrfr; /* 0x40 */ 190 u32 crcr; /* 0x44 */ 191 u32 rxfgmask; /* 0x48 */ 192 u32 rxfir; /* 0x4c */ 193 u32 _reserved3[12]; 194 struct flexcan_mb cantxfg[64]; 195}; 196 197struct flexcan_devtype_data { 198 u32 features; /* hardware controller features */ 199}; 200 201struct flexcan_priv { 202 struct can_priv can; 203 struct net_device *dev; 204 struct napi_struct napi; 205 206 void __iomem *base; 207 u32 reg_esr; 208 u32 reg_ctrl_default; 209 210 struct clk *clk_ipg; 211 struct clk *clk_per; 212 struct flexcan_platform_data *pdata; 213 const struct flexcan_devtype_data *devtype_data; 214 struct regulator *reg_xceiver; 215}; 216 217static struct flexcan_devtype_data fsl_p1010_devtype_data = { 218 .features = FLEXCAN_HAS_BROKEN_ERR_STATE, 219}; 220static struct flexcan_devtype_data fsl_imx28_devtype_data; 221static struct flexcan_devtype_data fsl_imx6q_devtype_data = { 222 .features = FLEXCAN_HAS_V10_FEATURES, 223}; 224 225static const struct can_bittiming_const flexcan_bittiming_const = { 226 .name = DRV_NAME, 227 .tseg1_min = 4, 228 .tseg1_max = 16, 229 .tseg2_min = 2, 230 .tseg2_max = 8, 231 .sjw_max = 4, 232 .brp_min = 1, 233 .brp_max = 256, 234 .brp_inc = 1, 235}; 236 237/* 238 * Abstract off the read/write for arm versus ppc. This 239 * assumes that PPC uses big-endian registers and everything 240 * else uses little-endian registers, independent of CPU 241 * endianess. 242 */ 243#if defined(CONFIG_PPC) 244static inline u32 flexcan_read(void __iomem *addr) 245{ 246 return in_be32(addr); 247} 248 249static inline void flexcan_write(u32 val, void __iomem *addr) 250{ 251 out_be32(addr, val); 252} 253#else 254static inline u32 flexcan_read(void __iomem *addr) 255{ 256 return readl(addr); 257} 258 259static inline void flexcan_write(u32 val, void __iomem *addr) 260{ 261 writel(val, addr); 262} 263#endif 264 265static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, 266 u32 reg_esr) 267{ 268 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 269 (reg_esr & FLEXCAN_ESR_ERR_BUS); 270} 271 272static inline void flexcan_chip_enable(struct flexcan_priv *priv) 273{ 274 struct flexcan_regs __iomem *regs = priv->base; 275 u32 reg; 276 277 reg = flexcan_read(®s->mcr); 278 reg &= ~FLEXCAN_MCR_MDIS; 279 flexcan_write(reg, ®s->mcr); 280 281 udelay(10); 282} 283 284static inline void flexcan_chip_disable(struct flexcan_priv *priv) 285{ 286 struct flexcan_regs __iomem *regs = priv->base; 287 u32 reg; 288 289 reg = flexcan_read(®s->mcr); 290 reg |= FLEXCAN_MCR_MDIS; 291 flexcan_write(reg, ®s->mcr); 292} 293 294static int flexcan_get_berr_counter(const struct net_device *dev, 295 struct can_berr_counter *bec) 296{ 297 const struct flexcan_priv *priv = netdev_priv(dev); 298 struct flexcan_regs __iomem *regs = priv->base; 299 u32 reg = flexcan_read(®s->ecr); 300 301 bec->txerr = (reg >> 0) & 0xff; 302 bec->rxerr = (reg >> 8) & 0xff; 303 304 return 0; 305} 306 307static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 308{ 309 const struct flexcan_priv *priv = netdev_priv(dev); 310 struct flexcan_regs __iomem *regs = priv->base; 311 struct can_frame *cf = (struct can_frame *)skb->data; 312 u32 can_id; 313 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); 314 315 if (can_dropped_invalid_skb(dev, skb)) 316 return NETDEV_TX_OK; 317 318 netif_stop_queue(dev); 319 320 if (cf->can_id & CAN_EFF_FLAG) { 321 can_id = cf->can_id & CAN_EFF_MASK; 322 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 323 } else { 324 can_id = (cf->can_id & CAN_SFF_MASK) << 18; 325 } 326 327 if (cf->can_id & CAN_RTR_FLAG) 328 ctrl |= FLEXCAN_MB_CNT_RTR; 329 330 if (cf->can_dlc > 0) { 331 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 332 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 333 } 334 if (cf->can_dlc > 3) { 335 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 336 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 337 } 338 339 can_put_echo_skb(skb, dev, 0); 340 341 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 342 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 343 344 return NETDEV_TX_OK; 345} 346 347static void do_bus_err(struct net_device *dev, 348 struct can_frame *cf, u32 reg_esr) 349{ 350 struct flexcan_priv *priv = netdev_priv(dev); 351 int rx_errors = 0, tx_errors = 0; 352 353 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 354 355 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 356 netdev_dbg(dev, "BIT1_ERR irq\n"); 357 cf->data[2] |= CAN_ERR_PROT_BIT1; 358 tx_errors = 1; 359 } 360 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 361 netdev_dbg(dev, "BIT0_ERR irq\n"); 362 cf->data[2] |= CAN_ERR_PROT_BIT0; 363 tx_errors = 1; 364 } 365 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 366 netdev_dbg(dev, "ACK_ERR irq\n"); 367 cf->can_id |= CAN_ERR_ACK; 368 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 369 tx_errors = 1; 370 } 371 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 372 netdev_dbg(dev, "CRC_ERR irq\n"); 373 cf->data[2] |= CAN_ERR_PROT_BIT; 374 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 375 rx_errors = 1; 376 } 377 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 378 netdev_dbg(dev, "FRM_ERR irq\n"); 379 cf->data[2] |= CAN_ERR_PROT_FORM; 380 rx_errors = 1; 381 } 382 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 383 netdev_dbg(dev, "STF_ERR irq\n"); 384 cf->data[2] |= CAN_ERR_PROT_STUFF; 385 rx_errors = 1; 386 } 387 388 priv->can.can_stats.bus_error++; 389 if (rx_errors) 390 dev->stats.rx_errors++; 391 if (tx_errors) 392 dev->stats.tx_errors++; 393} 394 395static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) 396{ 397 struct sk_buff *skb; 398 struct can_frame *cf; 399 400 skb = alloc_can_err_skb(dev, &cf); 401 if (unlikely(!skb)) 402 return 0; 403 404 do_bus_err(dev, cf, reg_esr); 405 netif_receive_skb(skb); 406 407 dev->stats.rx_packets++; 408 dev->stats.rx_bytes += cf->can_dlc; 409 410 return 1; 411} 412 413static void do_state(struct net_device *dev, 414 struct can_frame *cf, enum can_state new_state) 415{ 416 struct flexcan_priv *priv = netdev_priv(dev); 417 struct can_berr_counter bec; 418 419 flexcan_get_berr_counter(dev, &bec); 420 421 switch (priv->can.state) { 422 case CAN_STATE_ERROR_ACTIVE: 423 /* 424 * from: ERROR_ACTIVE 425 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 426 * => : there was a warning int 427 */ 428 if (new_state >= CAN_STATE_ERROR_WARNING && 429 new_state <= CAN_STATE_BUS_OFF) { 430 netdev_dbg(dev, "Error Warning IRQ\n"); 431 priv->can.can_stats.error_warning++; 432 433 cf->can_id |= CAN_ERR_CRTL; 434 cf->data[1] = (bec.txerr > bec.rxerr) ? 435 CAN_ERR_CRTL_TX_WARNING : 436 CAN_ERR_CRTL_RX_WARNING; 437 } 438 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 439 /* 440 * from: ERROR_ACTIVE, ERROR_WARNING 441 * to : ERROR_PASSIVE, BUS_OFF 442 * => : error passive int 443 */ 444 if (new_state >= CAN_STATE_ERROR_PASSIVE && 445 new_state <= CAN_STATE_BUS_OFF) { 446 netdev_dbg(dev, "Error Passive IRQ\n"); 447 priv->can.can_stats.error_passive++; 448 449 cf->can_id |= CAN_ERR_CRTL; 450 cf->data[1] = (bec.txerr > bec.rxerr) ? 451 CAN_ERR_CRTL_TX_PASSIVE : 452 CAN_ERR_CRTL_RX_PASSIVE; 453 } 454 break; 455 case CAN_STATE_BUS_OFF: 456 netdev_err(dev, "BUG! " 457 "hardware recovered automatically from BUS_OFF\n"); 458 break; 459 default: 460 break; 461 } 462 463 /* process state changes depending on the new state */ 464 switch (new_state) { 465 case CAN_STATE_ERROR_ACTIVE: 466 netdev_dbg(dev, "Error Active\n"); 467 cf->can_id |= CAN_ERR_PROT; 468 cf->data[2] = CAN_ERR_PROT_ACTIVE; 469 break; 470 case CAN_STATE_BUS_OFF: 471 cf->can_id |= CAN_ERR_BUSOFF; 472 can_bus_off(dev); 473 break; 474 default: 475 break; 476 } 477} 478 479static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) 480{ 481 struct flexcan_priv *priv = netdev_priv(dev); 482 struct sk_buff *skb; 483 struct can_frame *cf; 484 enum can_state new_state; 485 int flt; 486 487 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 488 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 489 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | 490 FLEXCAN_ESR_RX_WRN)))) 491 new_state = CAN_STATE_ERROR_ACTIVE; 492 else 493 new_state = CAN_STATE_ERROR_WARNING; 494 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) 495 new_state = CAN_STATE_ERROR_PASSIVE; 496 else 497 new_state = CAN_STATE_BUS_OFF; 498 499 /* state hasn't changed */ 500 if (likely(new_state == priv->can.state)) 501 return 0; 502 503 skb = alloc_can_err_skb(dev, &cf); 504 if (unlikely(!skb)) 505 return 0; 506 507 do_state(dev, cf, new_state); 508 priv->can.state = new_state; 509 netif_receive_skb(skb); 510 511 dev->stats.rx_packets++; 512 dev->stats.rx_bytes += cf->can_dlc; 513 514 return 1; 515} 516 517static void flexcan_read_fifo(const struct net_device *dev, 518 struct can_frame *cf) 519{ 520 const struct flexcan_priv *priv = netdev_priv(dev); 521 struct flexcan_regs __iomem *regs = priv->base; 522 struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; 523 u32 reg_ctrl, reg_id; 524 525 reg_ctrl = flexcan_read(&mb->can_ctrl); 526 reg_id = flexcan_read(&mb->can_id); 527 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 528 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 529 else 530 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; 531 532 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 533 cf->can_id |= CAN_RTR_FLAG; 534 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 535 536 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); 537 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); 538 539 /* mark as read */ 540 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 541 flexcan_read(®s->timer); 542} 543 544static int flexcan_read_frame(struct net_device *dev) 545{ 546 struct net_device_stats *stats = &dev->stats; 547 struct can_frame *cf; 548 struct sk_buff *skb; 549 550 skb = alloc_can_skb(dev, &cf); 551 if (unlikely(!skb)) { 552 stats->rx_dropped++; 553 return 0; 554 } 555 556 flexcan_read_fifo(dev, cf); 557 netif_receive_skb(skb); 558 559 stats->rx_packets++; 560 stats->rx_bytes += cf->can_dlc; 561 562 can_led_event(dev, CAN_LED_EVENT_RX); 563 564 return 1; 565} 566 567static int flexcan_poll(struct napi_struct *napi, int quota) 568{ 569 struct net_device *dev = napi->dev; 570 const struct flexcan_priv *priv = netdev_priv(dev); 571 struct flexcan_regs __iomem *regs = priv->base; 572 u32 reg_iflag1, reg_esr; 573 int work_done = 0; 574 575 /* 576 * The error bits are cleared on read, 577 * use saved value from irq handler. 578 */ 579 reg_esr = flexcan_read(®s->esr) | priv->reg_esr; 580 581 /* handle state changes */ 582 work_done += flexcan_poll_state(dev, reg_esr); 583 584 /* handle RX-FIFO */ 585 reg_iflag1 = flexcan_read(®s->iflag1); 586 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 587 work_done < quota) { 588 work_done += flexcan_read_frame(dev); 589 reg_iflag1 = flexcan_read(®s->iflag1); 590 } 591 592 /* report bus errors */ 593 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) 594 work_done += flexcan_poll_bus_err(dev, reg_esr); 595 596 if (work_done < quota) { 597 napi_complete(napi); 598 /* enable IRQs */ 599 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 600 flexcan_write(priv->reg_ctrl_default, ®s->ctrl); 601 } 602 603 return work_done; 604} 605 606static irqreturn_t flexcan_irq(int irq, void *dev_id) 607{ 608 struct net_device *dev = dev_id; 609 struct net_device_stats *stats = &dev->stats; 610 struct flexcan_priv *priv = netdev_priv(dev); 611 struct flexcan_regs __iomem *regs = priv->base; 612 u32 reg_iflag1, reg_esr; 613 614 reg_iflag1 = flexcan_read(®s->iflag1); 615 reg_esr = flexcan_read(®s->esr); 616 /* ACK all bus error and state change IRQ sources */ 617 if (reg_esr & FLEXCAN_ESR_ALL_INT) 618 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); 619 620 /* 621 * schedule NAPI in case of: 622 * - rx IRQ 623 * - state change IRQ 624 * - bus error IRQ and bus error reporting is activated 625 */ 626 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || 627 (reg_esr & FLEXCAN_ESR_ERR_STATE) || 628 flexcan_has_and_handle_berr(priv, reg_esr)) { 629 /* 630 * The error bits are cleared on read, 631 * save them for later use. 632 */ 633 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 634 flexcan_write(FLEXCAN_IFLAG_DEFAULT & 635 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); 636 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 637 ®s->ctrl); 638 napi_schedule(&priv->napi); 639 } 640 641 /* FIFO overflow */ 642 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 643 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); 644 dev->stats.rx_over_errors++; 645 dev->stats.rx_errors++; 646 } 647 648 /* transmission complete interrupt */ 649 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 650 stats->tx_bytes += can_get_echo_skb(dev, 0); 651 stats->tx_packets++; 652 can_led_event(dev, CAN_LED_EVENT_TX); 653 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); 654 netif_wake_queue(dev); 655 } 656 657 return IRQ_HANDLED; 658} 659 660static void flexcan_set_bittiming(struct net_device *dev) 661{ 662 const struct flexcan_priv *priv = netdev_priv(dev); 663 const struct can_bittiming *bt = &priv->can.bittiming; 664 struct flexcan_regs __iomem *regs = priv->base; 665 u32 reg; 666 667 reg = flexcan_read(®s->ctrl); 668 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 669 FLEXCAN_CTRL_RJW(0x3) | 670 FLEXCAN_CTRL_PSEG1(0x7) | 671 FLEXCAN_CTRL_PSEG2(0x7) | 672 FLEXCAN_CTRL_PROPSEG(0x7) | 673 FLEXCAN_CTRL_LPB | 674 FLEXCAN_CTRL_SMP | 675 FLEXCAN_CTRL_LOM); 676 677 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 678 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 679 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 680 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 681 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 682 683 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 684 reg |= FLEXCAN_CTRL_LPB; 685 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 686 reg |= FLEXCAN_CTRL_LOM; 687 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 688 reg |= FLEXCAN_CTRL_SMP; 689 690 netdev_info(dev, "writing ctrl=0x%08x\n", reg); 691 flexcan_write(reg, ®s->ctrl); 692 693 /* print chip status */ 694 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 695 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 696} 697 698/* 699 * flexcan_chip_start 700 * 701 * this functions is entered with clocks enabled 702 * 703 */ 704static int flexcan_chip_start(struct net_device *dev) 705{ 706 struct flexcan_priv *priv = netdev_priv(dev); 707 struct flexcan_regs __iomem *regs = priv->base; 708 int err; 709 u32 reg_mcr, reg_ctrl; 710 711 /* enable module */ 712 flexcan_chip_enable(priv); 713 714 /* soft reset */ 715 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 716 udelay(10); 717 718 reg_mcr = flexcan_read(®s->mcr); 719 if (reg_mcr & FLEXCAN_MCR_SOFTRST) { 720 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n", 721 reg_mcr); 722 err = -ENODEV; 723 goto out; 724 } 725 726 flexcan_set_bittiming(dev); 727 728 /* 729 * MCR 730 * 731 * enable freeze 732 * enable fifo 733 * halt now 734 * only supervisor access 735 * enable warning int 736 * choose format C 737 * disable local echo 738 * 739 */ 740 reg_mcr = flexcan_read(®s->mcr); 741 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff); 742 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 743 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 744 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS | 745 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID); 746 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); 747 flexcan_write(reg_mcr, ®s->mcr); 748 749 /* 750 * CTRL 751 * 752 * disable timer sync feature 753 * 754 * disable auto busoff recovery 755 * transmit lowest buffer first 756 * 757 * enable tx and rx warning interrupt 758 * enable bus off interrupt 759 * (== FLEXCAN_CTRL_ERR_STATE) 760 */ 761 reg_ctrl = flexcan_read(®s->ctrl); 762 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 763 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 764 FLEXCAN_CTRL_ERR_STATE; 765 /* 766 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), 767 * on most Flexcan cores, too. Otherwise we don't get 768 * any error warning or passive interrupts. 769 */ 770 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE || 771 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 772 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; 773 774 /* save for later use */ 775 priv->reg_ctrl_default = reg_ctrl; 776 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 777 flexcan_write(reg_ctrl, ®s->ctrl); 778 779 /* Abort any pending TX, mark Mailbox as INACTIVE */ 780 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4), 781 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 782 783 /* acceptance mask/acceptance code (accept everything) */ 784 flexcan_write(0x0, ®s->rxgmask); 785 flexcan_write(0x0, ®s->rx14mask); 786 flexcan_write(0x0, ®s->rx15mask); 787 788 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) 789 flexcan_write(0x0, ®s->rxfgmask); 790 791 if (priv->reg_xceiver) { 792 err = regulator_enable(priv->reg_xceiver); 793 if (err) 794 goto out; 795 } 796 797 /* synchronize with the can bus */ 798 reg_mcr = flexcan_read(®s->mcr); 799 reg_mcr &= ~FLEXCAN_MCR_HALT; 800 flexcan_write(reg_mcr, ®s->mcr); 801 802 priv->can.state = CAN_STATE_ERROR_ACTIVE; 803 804 /* enable FIFO interrupts */ 805 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 806 807 /* print chip status */ 808 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, 809 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 810 811 return 0; 812 813 out: 814 flexcan_chip_disable(priv); 815 return err; 816} 817 818/* 819 * flexcan_chip_stop 820 * 821 * this functions is entered with clocks enabled 822 * 823 */ 824static void flexcan_chip_stop(struct net_device *dev) 825{ 826 struct flexcan_priv *priv = netdev_priv(dev); 827 struct flexcan_regs __iomem *regs = priv->base; 828 u32 reg; 829 830 /* Disable all interrupts */ 831 flexcan_write(0, ®s->imask1); 832 833 /* Disable + halt module */ 834 reg = flexcan_read(®s->mcr); 835 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT; 836 flexcan_write(reg, ®s->mcr); 837 838 if (priv->reg_xceiver) 839 regulator_disable(priv->reg_xceiver); 840 priv->can.state = CAN_STATE_STOPPED; 841 842 return; 843} 844 845static int flexcan_open(struct net_device *dev) 846{ 847 struct flexcan_priv *priv = netdev_priv(dev); 848 int err; 849 850 err = clk_prepare_enable(priv->clk_ipg); 851 if (err) 852 return err; 853 854 err = clk_prepare_enable(priv->clk_per); 855 if (err) 856 goto out_disable_ipg; 857 858 err = open_candev(dev); 859 if (err) 860 goto out_disable_per; 861 862 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 863 if (err) 864 goto out_close; 865 866 /* start chip and queuing */ 867 err = flexcan_chip_start(dev); 868 if (err) 869 goto out_close; 870 871 can_led_event(dev, CAN_LED_EVENT_OPEN); 872 873 napi_enable(&priv->napi); 874 netif_start_queue(dev); 875 876 return 0; 877 878 out_close: 879 close_candev(dev); 880 out_disable_per: 881 clk_disable_unprepare(priv->clk_per); 882 out_disable_ipg: 883 clk_disable_unprepare(priv->clk_ipg); 884 885 return err; 886} 887 888static int flexcan_close(struct net_device *dev) 889{ 890 struct flexcan_priv *priv = netdev_priv(dev); 891 892 netif_stop_queue(dev); 893 napi_disable(&priv->napi); 894 flexcan_chip_stop(dev); 895 896 free_irq(dev->irq, dev); 897 clk_disable_unprepare(priv->clk_per); 898 clk_disable_unprepare(priv->clk_ipg); 899 900 close_candev(dev); 901 902 can_led_event(dev, CAN_LED_EVENT_STOP); 903 904 return 0; 905} 906 907static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 908{ 909 int err; 910 911 switch (mode) { 912 case CAN_MODE_START: 913 err = flexcan_chip_start(dev); 914 if (err) 915 return err; 916 917 netif_wake_queue(dev); 918 break; 919 920 default: 921 return -EOPNOTSUPP; 922 } 923 924 return 0; 925} 926 927static const struct net_device_ops flexcan_netdev_ops = { 928 .ndo_open = flexcan_open, 929 .ndo_stop = flexcan_close, 930 .ndo_start_xmit = flexcan_start_xmit, 931}; 932 933static int register_flexcandev(struct net_device *dev) 934{ 935 struct flexcan_priv *priv = netdev_priv(dev); 936 struct flexcan_regs __iomem *regs = priv->base; 937 u32 reg, err; 938 939 err = clk_prepare_enable(priv->clk_ipg); 940 if (err) 941 return err; 942 943 err = clk_prepare_enable(priv->clk_per); 944 if (err) 945 goto out_disable_ipg; 946 947 /* select "bus clock", chip must be disabled */ 948 flexcan_chip_disable(priv); 949 reg = flexcan_read(®s->ctrl); 950 reg |= FLEXCAN_CTRL_CLK_SRC; 951 flexcan_write(reg, ®s->ctrl); 952 953 flexcan_chip_enable(priv); 954 955 /* set freeze, halt and activate FIFO, restrict register access */ 956 reg = flexcan_read(®s->mcr); 957 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 958 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 959 flexcan_write(reg, ®s->mcr); 960 961 /* 962 * Currently we only support newer versions of this core 963 * featuring a RX FIFO. Older cores found on some Coldfire 964 * derivates are not yet supported. 965 */ 966 reg = flexcan_read(®s->mcr); 967 if (!(reg & FLEXCAN_MCR_FEN)) { 968 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); 969 err = -ENODEV; 970 goto out_disable_per; 971 } 972 973 err = register_candev(dev); 974 975 out_disable_per: 976 /* disable core and turn off clocks */ 977 flexcan_chip_disable(priv); 978 clk_disable_unprepare(priv->clk_per); 979 out_disable_ipg: 980 clk_disable_unprepare(priv->clk_ipg); 981 982 return err; 983} 984 985static void unregister_flexcandev(struct net_device *dev) 986{ 987 unregister_candev(dev); 988} 989 990static const struct of_device_id flexcan_of_match[] = { 991 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, 992 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, 993 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, 994 { /* sentinel */ }, 995}; 996MODULE_DEVICE_TABLE(of, flexcan_of_match); 997 998static const struct platform_device_id flexcan_id_table[] = { 999 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, }, 1000 { /* sentinel */ }, 1001}; 1002MODULE_DEVICE_TABLE(platform, flexcan_id_table); 1003 1004static int flexcan_probe(struct platform_device *pdev) 1005{ 1006 const struct of_device_id *of_id; 1007 const struct flexcan_devtype_data *devtype_data; 1008 struct net_device *dev; 1009 struct flexcan_priv *priv; 1010 struct resource *mem; 1011 struct clk *clk_ipg = NULL, *clk_per = NULL; 1012 void __iomem *base; 1013 int err, irq; 1014 u32 clock_freq = 0; 1015 1016 if (pdev->dev.of_node) 1017 of_property_read_u32(pdev->dev.of_node, 1018 "clock-frequency", &clock_freq); 1019 1020 if (!clock_freq) { 1021 clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1022 if (IS_ERR(clk_ipg)) { 1023 dev_err(&pdev->dev, "no ipg clock defined\n"); 1024 return PTR_ERR(clk_ipg); 1025 } 1026 1027 clk_per = devm_clk_get(&pdev->dev, "per"); 1028 if (IS_ERR(clk_per)) { 1029 dev_err(&pdev->dev, "no per clock defined\n"); 1030 return PTR_ERR(clk_per); 1031 } 1032 clock_freq = clk_get_rate(clk_per); 1033 } 1034 1035 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1036 irq = platform_get_irq(pdev, 0); 1037 if (irq <= 0) 1038 return -ENODEV; 1039 1040 base = devm_ioremap_resource(&pdev->dev, mem); 1041 if (IS_ERR(base)) 1042 return PTR_ERR(base); 1043 1044 of_id = of_match_device(flexcan_of_match, &pdev->dev); 1045 if (of_id) { 1046 devtype_data = of_id->data; 1047 } else if (pdev->id_entry->driver_data) { 1048 devtype_data = (struct flexcan_devtype_data *) 1049 pdev->id_entry->driver_data; 1050 } else { 1051 return -ENODEV; 1052 } 1053 1054 dev = alloc_candev(sizeof(struct flexcan_priv), 1); 1055 if (!dev) 1056 return -ENOMEM; 1057 1058 dev->netdev_ops = &flexcan_netdev_ops; 1059 dev->irq = irq; 1060 dev->flags |= IFF_ECHO; 1061 1062 priv = netdev_priv(dev); 1063 priv->can.clock.freq = clock_freq; 1064 priv->can.bittiming_const = &flexcan_bittiming_const; 1065 priv->can.do_set_mode = flexcan_set_mode; 1066 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 1067 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1068 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 1069 CAN_CTRLMODE_BERR_REPORTING; 1070 priv->base = base; 1071 priv->dev = dev; 1072 priv->clk_ipg = clk_ipg; 1073 priv->clk_per = clk_per; 1074 priv->pdata = dev_get_platdata(&pdev->dev); 1075 priv->devtype_data = devtype_data; 1076 1077 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); 1078 if (IS_ERR(priv->reg_xceiver)) 1079 priv->reg_xceiver = NULL; 1080 1081 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); 1082 1083 platform_set_drvdata(pdev, dev); 1084 SET_NETDEV_DEV(dev, &pdev->dev); 1085 1086 err = register_flexcandev(dev); 1087 if (err) { 1088 dev_err(&pdev->dev, "registering netdev failed\n"); 1089 goto failed_register; 1090 } 1091 1092 devm_can_led_init(dev); 1093 1094 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1095 priv->base, dev->irq); 1096 1097 return 0; 1098 1099 failed_register: 1100 free_candev(dev); 1101 return err; 1102} 1103 1104static int flexcan_remove(struct platform_device *pdev) 1105{ 1106 struct net_device *dev = platform_get_drvdata(pdev); 1107 1108 unregister_flexcandev(dev); 1109 1110 free_candev(dev); 1111 1112 return 0; 1113} 1114 1115#ifdef CONFIG_PM_SLEEP 1116static int flexcan_suspend(struct device *device) 1117{ 1118 struct net_device *dev = dev_get_drvdata(device); 1119 struct flexcan_priv *priv = netdev_priv(dev); 1120 1121 flexcan_chip_disable(priv); 1122 1123 if (netif_running(dev)) { 1124 netif_stop_queue(dev); 1125 netif_device_detach(dev); 1126 } 1127 priv->can.state = CAN_STATE_SLEEPING; 1128 1129 return 0; 1130} 1131 1132static int flexcan_resume(struct device *device) 1133{ 1134 struct net_device *dev = dev_get_drvdata(device); 1135 struct flexcan_priv *priv = netdev_priv(dev); 1136 1137 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1138 if (netif_running(dev)) { 1139 netif_device_attach(dev); 1140 netif_start_queue(dev); 1141 } 1142 flexcan_chip_enable(priv); 1143 1144 return 0; 1145} 1146#endif /* CONFIG_PM_SLEEP */ 1147 1148static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume); 1149 1150static struct platform_driver flexcan_driver = { 1151 .driver = { 1152 .name = DRV_NAME, 1153 .owner = THIS_MODULE, 1154 .pm = &flexcan_pm_ops, 1155 .of_match_table = flexcan_of_match, 1156 }, 1157 .probe = flexcan_probe, 1158 .remove = flexcan_remove, 1159 .id_table = flexcan_id_table, 1160}; 1161 1162module_platform_driver(flexcan_driver); 1163 1164MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 1165 "Marc Kleine-Budde <kernel@pengutronix.de>"); 1166MODULE_LICENSE("GPL v2"); 1167MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 1168