flexcan.c revision 12732c308340ad786d540b3a85f7b164189f2108
1/* 2 * flexcan.c - FLEXCAN CAN controller driver 3 * 4 * Copyright (c) 2005-2006 Varma Electronics Oy 5 * Copyright (c) 2009 Sascha Hauer, Pengutronix 6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix 7 * 8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com> 9 * 10 * LICENCE: 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22#include <linux/netdevice.h> 23#include <linux/can.h> 24#include <linux/can/dev.h> 25#include <linux/can/error.h> 26#include <linux/can/platform/flexcan.h> 27#include <linux/clk.h> 28#include <linux/delay.h> 29#include <linux/if_arp.h> 30#include <linux/if_ether.h> 31#include <linux/interrupt.h> 32#include <linux/io.h> 33#include <linux/kernel.h> 34#include <linux/list.h> 35#include <linux/module.h> 36#include <linux/platform_device.h> 37 38#define DRV_NAME "flexcan" 39 40/* 8 for RX fifo and 2 error handling */ 41#define FLEXCAN_NAPI_WEIGHT (8 + 2) 42 43/* FLEXCAN module configuration register (CANMCR) bits */ 44#define FLEXCAN_MCR_MDIS BIT(31) 45#define FLEXCAN_MCR_FRZ BIT(30) 46#define FLEXCAN_MCR_FEN BIT(29) 47#define FLEXCAN_MCR_HALT BIT(28) 48#define FLEXCAN_MCR_NOT_RDY BIT(27) 49#define FLEXCAN_MCR_WAK_MSK BIT(26) 50#define FLEXCAN_MCR_SOFTRST BIT(25) 51#define FLEXCAN_MCR_FRZ_ACK BIT(24) 52#define FLEXCAN_MCR_SUPV BIT(23) 53#define FLEXCAN_MCR_SLF_WAK BIT(22) 54#define FLEXCAN_MCR_WRN_EN BIT(21) 55#define FLEXCAN_MCR_LPM_ACK BIT(20) 56#define FLEXCAN_MCR_WAK_SRC BIT(19) 57#define FLEXCAN_MCR_DOZE BIT(18) 58#define FLEXCAN_MCR_SRX_DIS BIT(17) 59#define FLEXCAN_MCR_BCC BIT(16) 60#define FLEXCAN_MCR_LPRIO_EN BIT(13) 61#define FLEXCAN_MCR_AEN BIT(12) 62#define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf) 63#define FLEXCAN_MCR_IDAM_A (0 << 8) 64#define FLEXCAN_MCR_IDAM_B (1 << 8) 65#define FLEXCAN_MCR_IDAM_C (2 << 8) 66#define FLEXCAN_MCR_IDAM_D (3 << 8) 67 68/* FLEXCAN control register (CANCTRL) bits */ 69#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 70#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 71#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 72#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 73#define FLEXCAN_CTRL_BOFF_MSK BIT(15) 74#define FLEXCAN_CTRL_ERR_MSK BIT(14) 75#define FLEXCAN_CTRL_CLK_SRC BIT(13) 76#define FLEXCAN_CTRL_LPB BIT(12) 77#define FLEXCAN_CTRL_TWRN_MSK BIT(11) 78#define FLEXCAN_CTRL_RWRN_MSK BIT(10) 79#define FLEXCAN_CTRL_SMP BIT(7) 80#define FLEXCAN_CTRL_BOFF_REC BIT(6) 81#define FLEXCAN_CTRL_TSYN BIT(5) 82#define FLEXCAN_CTRL_LBUF BIT(4) 83#define FLEXCAN_CTRL_LOM BIT(3) 84#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 85#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 86#define FLEXCAN_CTRL_ERR_STATE \ 87 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 88 FLEXCAN_CTRL_BOFF_MSK) 89#define FLEXCAN_CTRL_ERR_ALL \ 90 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 91 92/* FLEXCAN error and status register (ESR) bits */ 93#define FLEXCAN_ESR_TWRN_INT BIT(17) 94#define FLEXCAN_ESR_RWRN_INT BIT(16) 95#define FLEXCAN_ESR_BIT1_ERR BIT(15) 96#define FLEXCAN_ESR_BIT0_ERR BIT(14) 97#define FLEXCAN_ESR_ACK_ERR BIT(13) 98#define FLEXCAN_ESR_CRC_ERR BIT(12) 99#define FLEXCAN_ESR_FRM_ERR BIT(11) 100#define FLEXCAN_ESR_STF_ERR BIT(10) 101#define FLEXCAN_ESR_TX_WRN BIT(9) 102#define FLEXCAN_ESR_RX_WRN BIT(8) 103#define FLEXCAN_ESR_IDLE BIT(7) 104#define FLEXCAN_ESR_TXRX BIT(6) 105#define FLEXCAN_EST_FLT_CONF_SHIFT (4) 106#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 107#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 108#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 109#define FLEXCAN_ESR_BOFF_INT BIT(2) 110#define FLEXCAN_ESR_ERR_INT BIT(1) 111#define FLEXCAN_ESR_WAK_INT BIT(0) 112#define FLEXCAN_ESR_ERR_BUS \ 113 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 114 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 115 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 116#define FLEXCAN_ESR_ERR_STATE \ 117 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 118#define FLEXCAN_ESR_ERR_ALL \ 119 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 120 121/* FLEXCAN interrupt flag register (IFLAG) bits */ 122#define FLEXCAN_TX_BUF_ID 8 123#define FLEXCAN_IFLAG_BUF(x) BIT(x) 124#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 125#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 126#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 127#define FLEXCAN_IFLAG_DEFAULT \ 128 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ 129 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) 130 131/* FLEXCAN message buffers */ 132#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) 133#define FLEXCAN_MB_CNT_SRR BIT(22) 134#define FLEXCAN_MB_CNT_IDE BIT(21) 135#define FLEXCAN_MB_CNT_RTR BIT(20) 136#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 137#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 138 139#define FLEXCAN_MB_CODE_MASK (0xf0ffffff) 140 141/* Structure of the message buffer */ 142struct flexcan_mb { 143 u32 can_ctrl; 144 u32 can_id; 145 u32 data[2]; 146}; 147 148/* Structure of the hardware registers */ 149struct flexcan_regs { 150 u32 mcr; /* 0x00 */ 151 u32 ctrl; /* 0x04 */ 152 u32 timer; /* 0x08 */ 153 u32 _reserved1; /* 0x0c */ 154 u32 rxgmask; /* 0x10 */ 155 u32 rx14mask; /* 0x14 */ 156 u32 rx15mask; /* 0x18 */ 157 u32 ecr; /* 0x1c */ 158 u32 esr; /* 0x20 */ 159 u32 imask2; /* 0x24 */ 160 u32 imask1; /* 0x28 */ 161 u32 iflag2; /* 0x2c */ 162 u32 iflag1; /* 0x30 */ 163 u32 _reserved2[19]; 164 struct flexcan_mb cantxfg[64]; 165}; 166 167struct flexcan_priv { 168 struct can_priv can; 169 struct net_device *dev; 170 struct napi_struct napi; 171 172 void __iomem *base; 173 u32 reg_esr; 174 u32 reg_ctrl_default; 175 176 struct clk *clk; 177 struct flexcan_platform_data *pdata; 178}; 179 180static struct can_bittiming_const flexcan_bittiming_const = { 181 .name = DRV_NAME, 182 .tseg1_min = 4, 183 .tseg1_max = 16, 184 .tseg2_min = 2, 185 .tseg2_max = 8, 186 .sjw_max = 4, 187 .brp_min = 1, 188 .brp_max = 256, 189 .brp_inc = 1, 190}; 191 192/* 193 * Swtich transceiver on or off 194 */ 195static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on) 196{ 197 if (priv->pdata && priv->pdata->transceiver_switch) 198 priv->pdata->transceiver_switch(on); 199} 200 201static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, 202 u32 reg_esr) 203{ 204 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 205 (reg_esr & FLEXCAN_ESR_ERR_BUS); 206} 207 208static inline void flexcan_chip_enable(struct flexcan_priv *priv) 209{ 210 struct flexcan_regs __iomem *regs = priv->base; 211 u32 reg; 212 213 reg = readl(®s->mcr); 214 reg &= ~FLEXCAN_MCR_MDIS; 215 writel(reg, ®s->mcr); 216 217 udelay(10); 218} 219 220static inline void flexcan_chip_disable(struct flexcan_priv *priv) 221{ 222 struct flexcan_regs __iomem *regs = priv->base; 223 u32 reg; 224 225 reg = readl(®s->mcr); 226 reg |= FLEXCAN_MCR_MDIS; 227 writel(reg, ®s->mcr); 228} 229 230static int flexcan_get_berr_counter(const struct net_device *dev, 231 struct can_berr_counter *bec) 232{ 233 const struct flexcan_priv *priv = netdev_priv(dev); 234 struct flexcan_regs __iomem *regs = priv->base; 235 u32 reg = readl(®s->ecr); 236 237 bec->txerr = (reg >> 0) & 0xff; 238 bec->rxerr = (reg >> 8) & 0xff; 239 240 return 0; 241} 242 243static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 244{ 245 const struct flexcan_priv *priv = netdev_priv(dev); 246 struct net_device_stats *stats = &dev->stats; 247 struct flexcan_regs __iomem *regs = priv->base; 248 struct can_frame *cf = (struct can_frame *)skb->data; 249 u32 can_id; 250 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); 251 252 if (can_dropped_invalid_skb(dev, skb)) 253 return NETDEV_TX_OK; 254 255 netif_stop_queue(dev); 256 257 if (cf->can_id & CAN_EFF_FLAG) { 258 can_id = cf->can_id & CAN_EFF_MASK; 259 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 260 } else { 261 can_id = (cf->can_id & CAN_SFF_MASK) << 18; 262 } 263 264 if (cf->can_id & CAN_RTR_FLAG) 265 ctrl |= FLEXCAN_MB_CNT_RTR; 266 267 if (cf->can_dlc > 0) { 268 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 269 writel(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 270 } 271 if (cf->can_dlc > 3) { 272 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 273 writel(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 274 } 275 276 writel(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 277 writel(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 278 279 kfree_skb(skb); 280 281 /* tx_packets is incremented in flexcan_irq */ 282 stats->tx_bytes += cf->can_dlc; 283 284 return NETDEV_TX_OK; 285} 286 287static void do_bus_err(struct net_device *dev, 288 struct can_frame *cf, u32 reg_esr) 289{ 290 struct flexcan_priv *priv = netdev_priv(dev); 291 int rx_errors = 0, tx_errors = 0; 292 293 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 294 295 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 296 dev_dbg(dev->dev.parent, "BIT1_ERR irq\n"); 297 cf->data[2] |= CAN_ERR_PROT_BIT1; 298 tx_errors = 1; 299 } 300 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 301 dev_dbg(dev->dev.parent, "BIT0_ERR irq\n"); 302 cf->data[2] |= CAN_ERR_PROT_BIT0; 303 tx_errors = 1; 304 } 305 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 306 dev_dbg(dev->dev.parent, "ACK_ERR irq\n"); 307 cf->can_id |= CAN_ERR_ACK; 308 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 309 tx_errors = 1; 310 } 311 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 312 dev_dbg(dev->dev.parent, "CRC_ERR irq\n"); 313 cf->data[2] |= CAN_ERR_PROT_BIT; 314 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 315 rx_errors = 1; 316 } 317 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 318 dev_dbg(dev->dev.parent, "FRM_ERR irq\n"); 319 cf->data[2] |= CAN_ERR_PROT_FORM; 320 rx_errors = 1; 321 } 322 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 323 dev_dbg(dev->dev.parent, "STF_ERR irq\n"); 324 cf->data[2] |= CAN_ERR_PROT_STUFF; 325 rx_errors = 1; 326 } 327 328 priv->can.can_stats.bus_error++; 329 if (rx_errors) 330 dev->stats.rx_errors++; 331 if (tx_errors) 332 dev->stats.tx_errors++; 333} 334 335static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) 336{ 337 struct sk_buff *skb; 338 struct can_frame *cf; 339 340 skb = alloc_can_err_skb(dev, &cf); 341 if (unlikely(!skb)) 342 return 0; 343 344 do_bus_err(dev, cf, reg_esr); 345 netif_receive_skb(skb); 346 347 dev->stats.rx_packets++; 348 dev->stats.rx_bytes += cf->can_dlc; 349 350 return 1; 351} 352 353static void do_state(struct net_device *dev, 354 struct can_frame *cf, enum can_state new_state) 355{ 356 struct flexcan_priv *priv = netdev_priv(dev); 357 struct can_berr_counter bec; 358 359 flexcan_get_berr_counter(dev, &bec); 360 361 switch (priv->can.state) { 362 case CAN_STATE_ERROR_ACTIVE: 363 /* 364 * from: ERROR_ACTIVE 365 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 366 * => : there was a warning int 367 */ 368 if (new_state >= CAN_STATE_ERROR_WARNING && 369 new_state <= CAN_STATE_BUS_OFF) { 370 dev_dbg(dev->dev.parent, "Error Warning IRQ\n"); 371 priv->can.can_stats.error_warning++; 372 373 cf->can_id |= CAN_ERR_CRTL; 374 cf->data[1] = (bec.txerr > bec.rxerr) ? 375 CAN_ERR_CRTL_TX_WARNING : 376 CAN_ERR_CRTL_RX_WARNING; 377 } 378 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 379 /* 380 * from: ERROR_ACTIVE, ERROR_WARNING 381 * to : ERROR_PASSIVE, BUS_OFF 382 * => : error passive int 383 */ 384 if (new_state >= CAN_STATE_ERROR_PASSIVE && 385 new_state <= CAN_STATE_BUS_OFF) { 386 dev_dbg(dev->dev.parent, "Error Passive IRQ\n"); 387 priv->can.can_stats.error_passive++; 388 389 cf->can_id |= CAN_ERR_CRTL; 390 cf->data[1] = (bec.txerr > bec.rxerr) ? 391 CAN_ERR_CRTL_TX_PASSIVE : 392 CAN_ERR_CRTL_RX_PASSIVE; 393 } 394 break; 395 case CAN_STATE_BUS_OFF: 396 dev_err(dev->dev.parent, 397 "BUG! hardware recovered automatically from BUS_OFF\n"); 398 break; 399 default: 400 break; 401 } 402 403 /* process state changes depending on the new state */ 404 switch (new_state) { 405 case CAN_STATE_ERROR_ACTIVE: 406 dev_dbg(dev->dev.parent, "Error Active\n"); 407 cf->can_id |= CAN_ERR_PROT; 408 cf->data[2] = CAN_ERR_PROT_ACTIVE; 409 break; 410 case CAN_STATE_BUS_OFF: 411 cf->can_id |= CAN_ERR_BUSOFF; 412 can_bus_off(dev); 413 break; 414 default: 415 break; 416 } 417} 418 419static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) 420{ 421 struct flexcan_priv *priv = netdev_priv(dev); 422 struct sk_buff *skb; 423 struct can_frame *cf; 424 enum can_state new_state; 425 int flt; 426 427 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 428 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 429 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | 430 FLEXCAN_ESR_RX_WRN)))) 431 new_state = CAN_STATE_ERROR_ACTIVE; 432 else 433 new_state = CAN_STATE_ERROR_WARNING; 434 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) 435 new_state = CAN_STATE_ERROR_PASSIVE; 436 else 437 new_state = CAN_STATE_BUS_OFF; 438 439 /* state hasn't changed */ 440 if (likely(new_state == priv->can.state)) 441 return 0; 442 443 skb = alloc_can_err_skb(dev, &cf); 444 if (unlikely(!skb)) 445 return 0; 446 447 do_state(dev, cf, new_state); 448 priv->can.state = new_state; 449 netif_receive_skb(skb); 450 451 dev->stats.rx_packets++; 452 dev->stats.rx_bytes += cf->can_dlc; 453 454 return 1; 455} 456 457static void flexcan_read_fifo(const struct net_device *dev, 458 struct can_frame *cf) 459{ 460 const struct flexcan_priv *priv = netdev_priv(dev); 461 struct flexcan_regs __iomem *regs = priv->base; 462 struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; 463 u32 reg_ctrl, reg_id; 464 465 reg_ctrl = readl(&mb->can_ctrl); 466 reg_id = readl(&mb->can_id); 467 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 468 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 469 else 470 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; 471 472 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 473 cf->can_id |= CAN_RTR_FLAG; 474 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 475 476 *(__be32 *)(cf->data + 0) = cpu_to_be32(readl(&mb->data[0])); 477 *(__be32 *)(cf->data + 4) = cpu_to_be32(readl(&mb->data[1])); 478 479 /* mark as read */ 480 writel(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 481 readl(®s->timer); 482} 483 484static int flexcan_read_frame(struct net_device *dev) 485{ 486 struct net_device_stats *stats = &dev->stats; 487 struct can_frame *cf; 488 struct sk_buff *skb; 489 490 skb = alloc_can_skb(dev, &cf); 491 if (unlikely(!skb)) { 492 stats->rx_dropped++; 493 return 0; 494 } 495 496 flexcan_read_fifo(dev, cf); 497 netif_receive_skb(skb); 498 499 stats->rx_packets++; 500 stats->rx_bytes += cf->can_dlc; 501 502 return 1; 503} 504 505static int flexcan_poll(struct napi_struct *napi, int quota) 506{ 507 struct net_device *dev = napi->dev; 508 const struct flexcan_priv *priv = netdev_priv(dev); 509 struct flexcan_regs __iomem *regs = priv->base; 510 u32 reg_iflag1, reg_esr; 511 int work_done = 0; 512 513 /* 514 * The error bits are cleared on read, 515 * use saved value from irq handler. 516 */ 517 reg_esr = readl(®s->esr) | priv->reg_esr; 518 519 /* handle state changes */ 520 work_done += flexcan_poll_state(dev, reg_esr); 521 522 /* handle RX-FIFO */ 523 reg_iflag1 = readl(®s->iflag1); 524 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 525 work_done < quota) { 526 work_done += flexcan_read_frame(dev); 527 reg_iflag1 = readl(®s->iflag1); 528 } 529 530 /* report bus errors */ 531 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) 532 work_done += flexcan_poll_bus_err(dev, reg_esr); 533 534 if (work_done < quota) { 535 napi_complete(napi); 536 /* enable IRQs */ 537 writel(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 538 writel(priv->reg_ctrl_default, ®s->ctrl); 539 } 540 541 return work_done; 542} 543 544static irqreturn_t flexcan_irq(int irq, void *dev_id) 545{ 546 struct net_device *dev = dev_id; 547 struct net_device_stats *stats = &dev->stats; 548 struct flexcan_priv *priv = netdev_priv(dev); 549 struct flexcan_regs __iomem *regs = priv->base; 550 u32 reg_iflag1, reg_esr; 551 552 reg_iflag1 = readl(®s->iflag1); 553 reg_esr = readl(®s->esr); 554 writel(FLEXCAN_ESR_ERR_INT, ®s->esr); /* ACK err IRQ */ 555 556 /* 557 * schedule NAPI in case of: 558 * - rx IRQ 559 * - state change IRQ 560 * - bus error IRQ and bus error reporting is activated 561 */ 562 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || 563 (reg_esr & FLEXCAN_ESR_ERR_STATE) || 564 flexcan_has_and_handle_berr(priv, reg_esr)) { 565 /* 566 * The error bits are cleared on read, 567 * save them for later use. 568 */ 569 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 570 writel(FLEXCAN_IFLAG_DEFAULT & ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, 571 ®s->imask1); 572 writel(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 573 ®s->ctrl); 574 napi_schedule(&priv->napi); 575 } 576 577 /* FIFO overflow */ 578 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 579 writel(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); 580 dev->stats.rx_over_errors++; 581 dev->stats.rx_errors++; 582 } 583 584 /* transmission complete interrupt */ 585 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 586 /* tx_bytes is incremented in flexcan_start_xmit */ 587 stats->tx_packets++; 588 writel((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); 589 netif_wake_queue(dev); 590 } 591 592 return IRQ_HANDLED; 593} 594 595static void flexcan_set_bittiming(struct net_device *dev) 596{ 597 const struct flexcan_priv *priv = netdev_priv(dev); 598 const struct can_bittiming *bt = &priv->can.bittiming; 599 struct flexcan_regs __iomem *regs = priv->base; 600 u32 reg; 601 602 reg = readl(®s->ctrl); 603 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 604 FLEXCAN_CTRL_RJW(0x3) | 605 FLEXCAN_CTRL_PSEG1(0x7) | 606 FLEXCAN_CTRL_PSEG2(0x7) | 607 FLEXCAN_CTRL_PROPSEG(0x7) | 608 FLEXCAN_CTRL_LPB | 609 FLEXCAN_CTRL_SMP | 610 FLEXCAN_CTRL_LOM); 611 612 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 613 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 614 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 615 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 616 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 617 618 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 619 reg |= FLEXCAN_CTRL_LPB; 620 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 621 reg |= FLEXCAN_CTRL_LOM; 622 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 623 reg |= FLEXCAN_CTRL_SMP; 624 625 dev_info(dev->dev.parent, "writing ctrl=0x%08x\n", reg); 626 writel(reg, ®s->ctrl); 627 628 /* print chip status */ 629 dev_dbg(dev->dev.parent, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 630 readl(®s->mcr), readl(®s->ctrl)); 631} 632 633/* 634 * flexcan_chip_start 635 * 636 * this functions is entered with clocks enabled 637 * 638 */ 639static int flexcan_chip_start(struct net_device *dev) 640{ 641 struct flexcan_priv *priv = netdev_priv(dev); 642 struct flexcan_regs __iomem *regs = priv->base; 643 unsigned int i; 644 int err; 645 u32 reg_mcr, reg_ctrl; 646 647 /* enable module */ 648 flexcan_chip_enable(priv); 649 650 /* soft reset */ 651 writel(FLEXCAN_MCR_SOFTRST, ®s->mcr); 652 udelay(10); 653 654 reg_mcr = readl(®s->mcr); 655 if (reg_mcr & FLEXCAN_MCR_SOFTRST) { 656 dev_err(dev->dev.parent, 657 "Failed to softreset can module (mcr=0x%08x)\n", 658 reg_mcr); 659 err = -ENODEV; 660 goto out; 661 } 662 663 flexcan_set_bittiming(dev); 664 665 /* 666 * MCR 667 * 668 * enable freeze 669 * enable fifo 670 * halt now 671 * only supervisor access 672 * enable warning int 673 * choose format C 674 * 675 */ 676 reg_mcr = readl(®s->mcr); 677 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 678 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 679 FLEXCAN_MCR_IDAM_C; 680 dev_dbg(dev->dev.parent, "%s: writing mcr=0x%08x", __func__, reg_mcr); 681 writel(reg_mcr, ®s->mcr); 682 683 /* 684 * CTRL 685 * 686 * disable timer sync feature 687 * 688 * disable auto busoff recovery 689 * transmit lowest buffer first 690 * 691 * enable tx and rx warning interrupt 692 * enable bus off interrupt 693 * (== FLEXCAN_CTRL_ERR_STATE) 694 * 695 * _note_: we enable the "error interrupt" 696 * (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any 697 * warning or bus passive interrupts. 698 */ 699 reg_ctrl = readl(®s->ctrl); 700 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 701 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 702 FLEXCAN_CTRL_ERR_STATE | FLEXCAN_CTRL_ERR_MSK; 703 704 /* save for later use */ 705 priv->reg_ctrl_default = reg_ctrl; 706 dev_dbg(dev->dev.parent, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 707 writel(reg_ctrl, ®s->ctrl); 708 709 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) { 710 writel(0, ®s->cantxfg[i].can_ctrl); 711 writel(0, ®s->cantxfg[i].can_id); 712 writel(0, ®s->cantxfg[i].data[0]); 713 writel(0, ®s->cantxfg[i].data[1]); 714 715 /* put MB into rx queue */ 716 writel(FLEXCAN_MB_CNT_CODE(0x4), ®s->cantxfg[i].can_ctrl); 717 } 718 719 /* acceptance mask/acceptance code (accept everything) */ 720 writel(0x0, ®s->rxgmask); 721 writel(0x0, ®s->rx14mask); 722 writel(0x0, ®s->rx15mask); 723 724 flexcan_transceiver_switch(priv, 1); 725 726 /* synchronize with the can bus */ 727 reg_mcr = readl(®s->mcr); 728 reg_mcr &= ~FLEXCAN_MCR_HALT; 729 writel(reg_mcr, ®s->mcr); 730 731 priv->can.state = CAN_STATE_ERROR_ACTIVE; 732 733 /* enable FIFO interrupts */ 734 writel(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 735 736 /* print chip status */ 737 dev_dbg(dev->dev.parent, "%s: reading mcr=0x%08x ctrl=0x%08x\n", 738 __func__, readl(®s->mcr), readl(®s->ctrl)); 739 740 return 0; 741 742 out: 743 flexcan_chip_disable(priv); 744 return err; 745} 746 747/* 748 * flexcan_chip_stop 749 * 750 * this functions is entered with clocks enabled 751 * 752 */ 753static void flexcan_chip_stop(struct net_device *dev) 754{ 755 struct flexcan_priv *priv = netdev_priv(dev); 756 struct flexcan_regs __iomem *regs = priv->base; 757 u32 reg; 758 759 /* Disable all interrupts */ 760 writel(0, ®s->imask1); 761 762 /* Disable + halt module */ 763 reg = readl(®s->mcr); 764 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT; 765 writel(reg, ®s->mcr); 766 767 flexcan_transceiver_switch(priv, 0); 768 priv->can.state = CAN_STATE_STOPPED; 769 770 return; 771} 772 773static int flexcan_open(struct net_device *dev) 774{ 775 struct flexcan_priv *priv = netdev_priv(dev); 776 int err; 777 778 clk_enable(priv->clk); 779 780 err = open_candev(dev); 781 if (err) 782 goto out; 783 784 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 785 if (err) 786 goto out_close; 787 788 /* start chip and queuing */ 789 err = flexcan_chip_start(dev); 790 if (err) 791 goto out_close; 792 napi_enable(&priv->napi); 793 netif_start_queue(dev); 794 795 return 0; 796 797 out_close: 798 close_candev(dev); 799 out: 800 clk_disable(priv->clk); 801 802 return err; 803} 804 805static int flexcan_close(struct net_device *dev) 806{ 807 struct flexcan_priv *priv = netdev_priv(dev); 808 809 netif_stop_queue(dev); 810 napi_disable(&priv->napi); 811 flexcan_chip_stop(dev); 812 813 free_irq(dev->irq, dev); 814 clk_disable(priv->clk); 815 816 close_candev(dev); 817 818 return 0; 819} 820 821static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 822{ 823 int err; 824 825 switch (mode) { 826 case CAN_MODE_START: 827 err = flexcan_chip_start(dev); 828 if (err) 829 return err; 830 831 netif_wake_queue(dev); 832 break; 833 834 default: 835 return -EOPNOTSUPP; 836 } 837 838 return 0; 839} 840 841static const struct net_device_ops flexcan_netdev_ops = { 842 .ndo_open = flexcan_open, 843 .ndo_stop = flexcan_close, 844 .ndo_start_xmit = flexcan_start_xmit, 845}; 846 847static int __devinit register_flexcandev(struct net_device *dev) 848{ 849 struct flexcan_priv *priv = netdev_priv(dev); 850 struct flexcan_regs __iomem *regs = priv->base; 851 u32 reg, err; 852 853 clk_enable(priv->clk); 854 855 /* select "bus clock", chip must be disabled */ 856 flexcan_chip_disable(priv); 857 reg = readl(®s->ctrl); 858 reg |= FLEXCAN_CTRL_CLK_SRC; 859 writel(reg, ®s->ctrl); 860 861 flexcan_chip_enable(priv); 862 863 /* set freeze, halt and activate FIFO, restrict register access */ 864 reg = readl(®s->mcr); 865 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 866 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 867 writel(reg, ®s->mcr); 868 869 /* 870 * Currently we only support newer versions of this core 871 * featuring a RX FIFO. Older cores found on some Coldfire 872 * derivates are not yet supported. 873 */ 874 reg = readl(®s->mcr); 875 if (!(reg & FLEXCAN_MCR_FEN)) { 876 dev_err(dev->dev.parent, 877 "Could not enable RX FIFO, unsupported core\n"); 878 err = -ENODEV; 879 goto out; 880 } 881 882 err = register_candev(dev); 883 884 out: 885 /* disable core and turn off clocks */ 886 flexcan_chip_disable(priv); 887 clk_disable(priv->clk); 888 889 return err; 890} 891 892static void __devexit unregister_flexcandev(struct net_device *dev) 893{ 894 unregister_candev(dev); 895} 896 897static int __devinit flexcan_probe(struct platform_device *pdev) 898{ 899 struct net_device *dev; 900 struct flexcan_priv *priv; 901 struct resource *mem; 902 struct clk *clk; 903 void __iomem *base; 904 resource_size_t mem_size; 905 int err, irq; 906 907 clk = clk_get(&pdev->dev, NULL); 908 if (IS_ERR(clk)) { 909 dev_err(&pdev->dev, "no clock defined\n"); 910 err = PTR_ERR(clk); 911 goto failed_clock; 912 } 913 914 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 915 irq = platform_get_irq(pdev, 0); 916 if (!mem || irq <= 0) { 917 err = -ENODEV; 918 goto failed_get; 919 } 920 921 mem_size = resource_size(mem); 922 if (!request_mem_region(mem->start, mem_size, pdev->name)) { 923 err = -EBUSY; 924 goto failed_get; 925 } 926 927 base = ioremap(mem->start, mem_size); 928 if (!base) { 929 err = -ENOMEM; 930 goto failed_map; 931 } 932 933 dev = alloc_candev(sizeof(struct flexcan_priv), 0); 934 if (!dev) { 935 err = -ENOMEM; 936 goto failed_alloc; 937 } 938 939 dev->netdev_ops = &flexcan_netdev_ops; 940 dev->irq = irq; 941 dev->flags |= IFF_ECHO; /* we support local echo in hardware */ 942 943 priv = netdev_priv(dev); 944 priv->can.clock.freq = clk_get_rate(clk); 945 priv->can.bittiming_const = &flexcan_bittiming_const; 946 priv->can.do_set_mode = flexcan_set_mode; 947 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 948 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 949 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 950 CAN_CTRLMODE_BERR_REPORTING; 951 priv->base = base; 952 priv->dev = dev; 953 priv->clk = clk; 954 priv->pdata = pdev->dev.platform_data; 955 956 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); 957 958 dev_set_drvdata(&pdev->dev, dev); 959 SET_NETDEV_DEV(dev, &pdev->dev); 960 961 err = register_flexcandev(dev); 962 if (err) { 963 dev_err(&pdev->dev, "registering netdev failed\n"); 964 goto failed_register; 965 } 966 967 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 968 priv->base, dev->irq); 969 970 return 0; 971 972 failed_register: 973 free_candev(dev); 974 failed_alloc: 975 iounmap(base); 976 failed_map: 977 release_mem_region(mem->start, mem_size); 978 failed_get: 979 clk_put(clk); 980 failed_clock: 981 return err; 982} 983 984static int __devexit flexcan_remove(struct platform_device *pdev) 985{ 986 struct net_device *dev = platform_get_drvdata(pdev); 987 struct flexcan_priv *priv = netdev_priv(dev); 988 struct resource *mem; 989 990 unregister_flexcandev(dev); 991 platform_set_drvdata(pdev, NULL); 992 iounmap(priv->base); 993 994 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 995 release_mem_region(mem->start, resource_size(mem)); 996 997 clk_put(priv->clk); 998 999 free_candev(dev); 1000 1001 return 0; 1002} 1003 1004static struct platform_driver flexcan_driver = { 1005 .driver.name = DRV_NAME, 1006 .probe = flexcan_probe, 1007 .remove = __devexit_p(flexcan_remove), 1008}; 1009 1010static int __init flexcan_init(void) 1011{ 1012 pr_info("%s netdevice driver\n", DRV_NAME); 1013 return platform_driver_register(&flexcan_driver); 1014} 1015 1016static void __exit flexcan_exit(void) 1017{ 1018 platform_driver_unregister(&flexcan_driver); 1019 pr_info("%s: driver removed\n", DRV_NAME); 1020} 1021 1022module_init(flexcan_init); 1023module_exit(flexcan_exit); 1024 1025MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 1026 "Marc Kleine-Budde <kernel@pengutronix.de>"); 1027MODULE_LICENSE("GPL v2"); 1028MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 1029