flexcan.c revision 4d7f7635f75da2924916946cb7ac49c5603b44c7
1/* 2 * flexcan.c - FLEXCAN CAN controller driver 3 * 4 * Copyright (c) 2005-2006 Varma Electronics Oy 5 * Copyright (c) 2009 Sascha Hauer, Pengutronix 6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix 7 * 8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com> 9 * 10 * LICENCE: 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22#include <linux/netdevice.h> 23#include <linux/can.h> 24#include <linux/can/dev.h> 25#include <linux/can/error.h> 26#include <linux/can/led.h> 27#include <linux/can/platform/flexcan.h> 28#include <linux/clk.h> 29#include <linux/delay.h> 30#include <linux/if_arp.h> 31#include <linux/if_ether.h> 32#include <linux/interrupt.h> 33#include <linux/io.h> 34#include <linux/kernel.h> 35#include <linux/list.h> 36#include <linux/module.h> 37#include <linux/of.h> 38#include <linux/of_device.h> 39#include <linux/platform_device.h> 40 41#define DRV_NAME "flexcan" 42 43/* 8 for RX fifo and 2 error handling */ 44#define FLEXCAN_NAPI_WEIGHT (8 + 2) 45 46/* FLEXCAN module configuration register (CANMCR) bits */ 47#define FLEXCAN_MCR_MDIS BIT(31) 48#define FLEXCAN_MCR_FRZ BIT(30) 49#define FLEXCAN_MCR_FEN BIT(29) 50#define FLEXCAN_MCR_HALT BIT(28) 51#define FLEXCAN_MCR_NOT_RDY BIT(27) 52#define FLEXCAN_MCR_WAK_MSK BIT(26) 53#define FLEXCAN_MCR_SOFTRST BIT(25) 54#define FLEXCAN_MCR_FRZ_ACK BIT(24) 55#define FLEXCAN_MCR_SUPV BIT(23) 56#define FLEXCAN_MCR_SLF_WAK BIT(22) 57#define FLEXCAN_MCR_WRN_EN BIT(21) 58#define FLEXCAN_MCR_LPM_ACK BIT(20) 59#define FLEXCAN_MCR_WAK_SRC BIT(19) 60#define FLEXCAN_MCR_DOZE BIT(18) 61#define FLEXCAN_MCR_SRX_DIS BIT(17) 62#define FLEXCAN_MCR_BCC BIT(16) 63#define FLEXCAN_MCR_LPRIO_EN BIT(13) 64#define FLEXCAN_MCR_AEN BIT(12) 65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf) 66#define FLEXCAN_MCR_IDAM_A (0 << 8) 67#define FLEXCAN_MCR_IDAM_B (1 << 8) 68#define FLEXCAN_MCR_IDAM_C (2 << 8) 69#define FLEXCAN_MCR_IDAM_D (3 << 8) 70 71/* FLEXCAN control register (CANCTRL) bits */ 72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 76#define FLEXCAN_CTRL_BOFF_MSK BIT(15) 77#define FLEXCAN_CTRL_ERR_MSK BIT(14) 78#define FLEXCAN_CTRL_CLK_SRC BIT(13) 79#define FLEXCAN_CTRL_LPB BIT(12) 80#define FLEXCAN_CTRL_TWRN_MSK BIT(11) 81#define FLEXCAN_CTRL_RWRN_MSK BIT(10) 82#define FLEXCAN_CTRL_SMP BIT(7) 83#define FLEXCAN_CTRL_BOFF_REC BIT(6) 84#define FLEXCAN_CTRL_TSYN BIT(5) 85#define FLEXCAN_CTRL_LBUF BIT(4) 86#define FLEXCAN_CTRL_LOM BIT(3) 87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 89#define FLEXCAN_CTRL_ERR_STATE \ 90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 91 FLEXCAN_CTRL_BOFF_MSK) 92#define FLEXCAN_CTRL_ERR_ALL \ 93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 94 95/* FLEXCAN error and status register (ESR) bits */ 96#define FLEXCAN_ESR_TWRN_INT BIT(17) 97#define FLEXCAN_ESR_RWRN_INT BIT(16) 98#define FLEXCAN_ESR_BIT1_ERR BIT(15) 99#define FLEXCAN_ESR_BIT0_ERR BIT(14) 100#define FLEXCAN_ESR_ACK_ERR BIT(13) 101#define FLEXCAN_ESR_CRC_ERR BIT(12) 102#define FLEXCAN_ESR_FRM_ERR BIT(11) 103#define FLEXCAN_ESR_STF_ERR BIT(10) 104#define FLEXCAN_ESR_TX_WRN BIT(9) 105#define FLEXCAN_ESR_RX_WRN BIT(8) 106#define FLEXCAN_ESR_IDLE BIT(7) 107#define FLEXCAN_ESR_TXRX BIT(6) 108#define FLEXCAN_EST_FLT_CONF_SHIFT (4) 109#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 110#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 111#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 112#define FLEXCAN_ESR_BOFF_INT BIT(2) 113#define FLEXCAN_ESR_ERR_INT BIT(1) 114#define FLEXCAN_ESR_WAK_INT BIT(0) 115#define FLEXCAN_ESR_ERR_BUS \ 116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 119#define FLEXCAN_ESR_ERR_STATE \ 120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 121#define FLEXCAN_ESR_ERR_ALL \ 122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 123#define FLEXCAN_ESR_ALL_INT \ 124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ 125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) 126 127/* FLEXCAN interrupt flag register (IFLAG) bits */ 128#define FLEXCAN_TX_BUF_ID 8 129#define FLEXCAN_IFLAG_BUF(x) BIT(x) 130#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 131#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 132#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 133#define FLEXCAN_IFLAG_DEFAULT \ 134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ 135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) 136 137/* FLEXCAN message buffers */ 138#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) 139#define FLEXCAN_MB_CNT_SRR BIT(22) 140#define FLEXCAN_MB_CNT_IDE BIT(21) 141#define FLEXCAN_MB_CNT_RTR BIT(20) 142#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 143#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 144 145#define FLEXCAN_MB_CODE_MASK (0xf0ffffff) 146 147/* 148 * FLEXCAN hardware feature flags 149 * 150 * Below is some version info we got: 151 * SOC Version IP-Version Glitch- [TR]WRN_INT 152 * Filter? connected? 153 * MX25 FlexCAN2 03.00.00.00 no no 154 * MX28 FlexCAN2 03.00.04.00 yes yes 155 * MX35 FlexCAN2 03.00.00.00 no no 156 * MX53 FlexCAN2 03.00.00.00 yes no 157 * MX6s FlexCAN3 10.00.12.00 yes yes 158 * 159 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected. 160 */ 161#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */ 162#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */ 163 164/* Structure of the message buffer */ 165struct flexcan_mb { 166 u32 can_ctrl; 167 u32 can_id; 168 u32 data[2]; 169}; 170 171/* Structure of the hardware registers */ 172struct flexcan_regs { 173 u32 mcr; /* 0x00 */ 174 u32 ctrl; /* 0x04 */ 175 u32 timer; /* 0x08 */ 176 u32 _reserved1; /* 0x0c */ 177 u32 rxgmask; /* 0x10 */ 178 u32 rx14mask; /* 0x14 */ 179 u32 rx15mask; /* 0x18 */ 180 u32 ecr; /* 0x1c */ 181 u32 esr; /* 0x20 */ 182 u32 imask2; /* 0x24 */ 183 u32 imask1; /* 0x28 */ 184 u32 iflag2; /* 0x2c */ 185 u32 iflag1; /* 0x30 */ 186 u32 crl2; /* 0x34 */ 187 u32 esr2; /* 0x38 */ 188 u32 imeur; /* 0x3c */ 189 u32 lrfr; /* 0x40 */ 190 u32 crcr; /* 0x44 */ 191 u32 rxfgmask; /* 0x48 */ 192 u32 rxfir; /* 0x4c */ 193 u32 _reserved3[12]; 194 struct flexcan_mb cantxfg[64]; 195}; 196 197struct flexcan_devtype_data { 198 u32 features; /* hardware controller features */ 199}; 200 201struct flexcan_priv { 202 struct can_priv can; 203 struct net_device *dev; 204 struct napi_struct napi; 205 206 void __iomem *base; 207 u32 reg_esr; 208 u32 reg_ctrl_default; 209 210 struct clk *clk_ipg; 211 struct clk *clk_per; 212 struct flexcan_platform_data *pdata; 213 const struct flexcan_devtype_data *devtype_data; 214}; 215 216static struct flexcan_devtype_data fsl_p1010_devtype_data = { 217 .features = FLEXCAN_HAS_BROKEN_ERR_STATE, 218}; 219static struct flexcan_devtype_data fsl_imx28_devtype_data; 220static struct flexcan_devtype_data fsl_imx6q_devtype_data = { 221 .features = FLEXCAN_HAS_V10_FEATURES, 222}; 223 224static const struct can_bittiming_const flexcan_bittiming_const = { 225 .name = DRV_NAME, 226 .tseg1_min = 4, 227 .tseg1_max = 16, 228 .tseg2_min = 2, 229 .tseg2_max = 8, 230 .sjw_max = 4, 231 .brp_min = 1, 232 .brp_max = 256, 233 .brp_inc = 1, 234}; 235 236/* 237 * Abstract off the read/write for arm versus ppc. 238 */ 239#if defined(__BIG_ENDIAN) 240static inline u32 flexcan_read(void __iomem *addr) 241{ 242 return in_be32(addr); 243} 244 245static inline void flexcan_write(u32 val, void __iomem *addr) 246{ 247 out_be32(addr, val); 248} 249#else 250static inline u32 flexcan_read(void __iomem *addr) 251{ 252 return readl(addr); 253} 254 255static inline void flexcan_write(u32 val, void __iomem *addr) 256{ 257 writel(val, addr); 258} 259#endif 260 261/* 262 * Swtich transceiver on or off 263 */ 264static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on) 265{ 266 if (priv->pdata && priv->pdata->transceiver_switch) 267 priv->pdata->transceiver_switch(on); 268} 269 270static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, 271 u32 reg_esr) 272{ 273 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 274 (reg_esr & FLEXCAN_ESR_ERR_BUS); 275} 276 277static inline void flexcan_chip_enable(struct flexcan_priv *priv) 278{ 279 struct flexcan_regs __iomem *regs = priv->base; 280 u32 reg; 281 282 reg = flexcan_read(®s->mcr); 283 reg &= ~FLEXCAN_MCR_MDIS; 284 flexcan_write(reg, ®s->mcr); 285 286 udelay(10); 287} 288 289static inline void flexcan_chip_disable(struct flexcan_priv *priv) 290{ 291 struct flexcan_regs __iomem *regs = priv->base; 292 u32 reg; 293 294 reg = flexcan_read(®s->mcr); 295 reg |= FLEXCAN_MCR_MDIS; 296 flexcan_write(reg, ®s->mcr); 297} 298 299static int flexcan_get_berr_counter(const struct net_device *dev, 300 struct can_berr_counter *bec) 301{ 302 const struct flexcan_priv *priv = netdev_priv(dev); 303 struct flexcan_regs __iomem *regs = priv->base; 304 u32 reg = flexcan_read(®s->ecr); 305 306 bec->txerr = (reg >> 0) & 0xff; 307 bec->rxerr = (reg >> 8) & 0xff; 308 309 return 0; 310} 311 312static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 313{ 314 const struct flexcan_priv *priv = netdev_priv(dev); 315 struct flexcan_regs __iomem *regs = priv->base; 316 struct can_frame *cf = (struct can_frame *)skb->data; 317 u32 can_id; 318 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); 319 320 if (can_dropped_invalid_skb(dev, skb)) 321 return NETDEV_TX_OK; 322 323 netif_stop_queue(dev); 324 325 if (cf->can_id & CAN_EFF_FLAG) { 326 can_id = cf->can_id & CAN_EFF_MASK; 327 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 328 } else { 329 can_id = (cf->can_id & CAN_SFF_MASK) << 18; 330 } 331 332 if (cf->can_id & CAN_RTR_FLAG) 333 ctrl |= FLEXCAN_MB_CNT_RTR; 334 335 if (cf->can_dlc > 0) { 336 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 337 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 338 } 339 if (cf->can_dlc > 3) { 340 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 341 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 342 } 343 344 can_put_echo_skb(skb, dev, 0); 345 346 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 347 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 348 349 return NETDEV_TX_OK; 350} 351 352static void do_bus_err(struct net_device *dev, 353 struct can_frame *cf, u32 reg_esr) 354{ 355 struct flexcan_priv *priv = netdev_priv(dev); 356 int rx_errors = 0, tx_errors = 0; 357 358 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 359 360 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 361 netdev_dbg(dev, "BIT1_ERR irq\n"); 362 cf->data[2] |= CAN_ERR_PROT_BIT1; 363 tx_errors = 1; 364 } 365 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 366 netdev_dbg(dev, "BIT0_ERR irq\n"); 367 cf->data[2] |= CAN_ERR_PROT_BIT0; 368 tx_errors = 1; 369 } 370 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 371 netdev_dbg(dev, "ACK_ERR irq\n"); 372 cf->can_id |= CAN_ERR_ACK; 373 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 374 tx_errors = 1; 375 } 376 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 377 netdev_dbg(dev, "CRC_ERR irq\n"); 378 cf->data[2] |= CAN_ERR_PROT_BIT; 379 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 380 rx_errors = 1; 381 } 382 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 383 netdev_dbg(dev, "FRM_ERR irq\n"); 384 cf->data[2] |= CAN_ERR_PROT_FORM; 385 rx_errors = 1; 386 } 387 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 388 netdev_dbg(dev, "STF_ERR irq\n"); 389 cf->data[2] |= CAN_ERR_PROT_STUFF; 390 rx_errors = 1; 391 } 392 393 priv->can.can_stats.bus_error++; 394 if (rx_errors) 395 dev->stats.rx_errors++; 396 if (tx_errors) 397 dev->stats.tx_errors++; 398} 399 400static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) 401{ 402 struct sk_buff *skb; 403 struct can_frame *cf; 404 405 skb = alloc_can_err_skb(dev, &cf); 406 if (unlikely(!skb)) 407 return 0; 408 409 do_bus_err(dev, cf, reg_esr); 410 netif_receive_skb(skb); 411 412 dev->stats.rx_packets++; 413 dev->stats.rx_bytes += cf->can_dlc; 414 415 return 1; 416} 417 418static void do_state(struct net_device *dev, 419 struct can_frame *cf, enum can_state new_state) 420{ 421 struct flexcan_priv *priv = netdev_priv(dev); 422 struct can_berr_counter bec; 423 424 flexcan_get_berr_counter(dev, &bec); 425 426 switch (priv->can.state) { 427 case CAN_STATE_ERROR_ACTIVE: 428 /* 429 * from: ERROR_ACTIVE 430 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 431 * => : there was a warning int 432 */ 433 if (new_state >= CAN_STATE_ERROR_WARNING && 434 new_state <= CAN_STATE_BUS_OFF) { 435 netdev_dbg(dev, "Error Warning IRQ\n"); 436 priv->can.can_stats.error_warning++; 437 438 cf->can_id |= CAN_ERR_CRTL; 439 cf->data[1] = (bec.txerr > bec.rxerr) ? 440 CAN_ERR_CRTL_TX_WARNING : 441 CAN_ERR_CRTL_RX_WARNING; 442 } 443 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 444 /* 445 * from: ERROR_ACTIVE, ERROR_WARNING 446 * to : ERROR_PASSIVE, BUS_OFF 447 * => : error passive int 448 */ 449 if (new_state >= CAN_STATE_ERROR_PASSIVE && 450 new_state <= CAN_STATE_BUS_OFF) { 451 netdev_dbg(dev, "Error Passive IRQ\n"); 452 priv->can.can_stats.error_passive++; 453 454 cf->can_id |= CAN_ERR_CRTL; 455 cf->data[1] = (bec.txerr > bec.rxerr) ? 456 CAN_ERR_CRTL_TX_PASSIVE : 457 CAN_ERR_CRTL_RX_PASSIVE; 458 } 459 break; 460 case CAN_STATE_BUS_OFF: 461 netdev_err(dev, "BUG! " 462 "hardware recovered automatically from BUS_OFF\n"); 463 break; 464 default: 465 break; 466 } 467 468 /* process state changes depending on the new state */ 469 switch (new_state) { 470 case CAN_STATE_ERROR_ACTIVE: 471 netdev_dbg(dev, "Error Active\n"); 472 cf->can_id |= CAN_ERR_PROT; 473 cf->data[2] = CAN_ERR_PROT_ACTIVE; 474 break; 475 case CAN_STATE_BUS_OFF: 476 cf->can_id |= CAN_ERR_BUSOFF; 477 can_bus_off(dev); 478 break; 479 default: 480 break; 481 } 482} 483 484static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) 485{ 486 struct flexcan_priv *priv = netdev_priv(dev); 487 struct sk_buff *skb; 488 struct can_frame *cf; 489 enum can_state new_state; 490 int flt; 491 492 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 493 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 494 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | 495 FLEXCAN_ESR_RX_WRN)))) 496 new_state = CAN_STATE_ERROR_ACTIVE; 497 else 498 new_state = CAN_STATE_ERROR_WARNING; 499 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) 500 new_state = CAN_STATE_ERROR_PASSIVE; 501 else 502 new_state = CAN_STATE_BUS_OFF; 503 504 /* state hasn't changed */ 505 if (likely(new_state == priv->can.state)) 506 return 0; 507 508 skb = alloc_can_err_skb(dev, &cf); 509 if (unlikely(!skb)) 510 return 0; 511 512 do_state(dev, cf, new_state); 513 priv->can.state = new_state; 514 netif_receive_skb(skb); 515 516 dev->stats.rx_packets++; 517 dev->stats.rx_bytes += cf->can_dlc; 518 519 return 1; 520} 521 522static void flexcan_read_fifo(const struct net_device *dev, 523 struct can_frame *cf) 524{ 525 const struct flexcan_priv *priv = netdev_priv(dev); 526 struct flexcan_regs __iomem *regs = priv->base; 527 struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; 528 u32 reg_ctrl, reg_id; 529 530 reg_ctrl = flexcan_read(&mb->can_ctrl); 531 reg_id = flexcan_read(&mb->can_id); 532 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 533 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 534 else 535 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; 536 537 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 538 cf->can_id |= CAN_RTR_FLAG; 539 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 540 541 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); 542 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); 543 544 /* mark as read */ 545 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 546 flexcan_read(®s->timer); 547} 548 549static int flexcan_read_frame(struct net_device *dev) 550{ 551 struct net_device_stats *stats = &dev->stats; 552 struct can_frame *cf; 553 struct sk_buff *skb; 554 555 skb = alloc_can_skb(dev, &cf); 556 if (unlikely(!skb)) { 557 stats->rx_dropped++; 558 return 0; 559 } 560 561 flexcan_read_fifo(dev, cf); 562 netif_receive_skb(skb); 563 564 stats->rx_packets++; 565 stats->rx_bytes += cf->can_dlc; 566 567 can_led_event(dev, CAN_LED_EVENT_RX); 568 569 return 1; 570} 571 572static int flexcan_poll(struct napi_struct *napi, int quota) 573{ 574 struct net_device *dev = napi->dev; 575 const struct flexcan_priv *priv = netdev_priv(dev); 576 struct flexcan_regs __iomem *regs = priv->base; 577 u32 reg_iflag1, reg_esr; 578 int work_done = 0; 579 580 /* 581 * The error bits are cleared on read, 582 * use saved value from irq handler. 583 */ 584 reg_esr = flexcan_read(®s->esr) | priv->reg_esr; 585 586 /* handle state changes */ 587 work_done += flexcan_poll_state(dev, reg_esr); 588 589 /* handle RX-FIFO */ 590 reg_iflag1 = flexcan_read(®s->iflag1); 591 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 592 work_done < quota) { 593 work_done += flexcan_read_frame(dev); 594 reg_iflag1 = flexcan_read(®s->iflag1); 595 } 596 597 /* report bus errors */ 598 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) 599 work_done += flexcan_poll_bus_err(dev, reg_esr); 600 601 if (work_done < quota) { 602 napi_complete(napi); 603 /* enable IRQs */ 604 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 605 flexcan_write(priv->reg_ctrl_default, ®s->ctrl); 606 } 607 608 return work_done; 609} 610 611static irqreturn_t flexcan_irq(int irq, void *dev_id) 612{ 613 struct net_device *dev = dev_id; 614 struct net_device_stats *stats = &dev->stats; 615 struct flexcan_priv *priv = netdev_priv(dev); 616 struct flexcan_regs __iomem *regs = priv->base; 617 u32 reg_iflag1, reg_esr; 618 619 reg_iflag1 = flexcan_read(®s->iflag1); 620 reg_esr = flexcan_read(®s->esr); 621 /* ACK all bus error and state change IRQ sources */ 622 if (reg_esr & FLEXCAN_ESR_ALL_INT) 623 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); 624 625 /* 626 * schedule NAPI in case of: 627 * - rx IRQ 628 * - state change IRQ 629 * - bus error IRQ and bus error reporting is activated 630 */ 631 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || 632 (reg_esr & FLEXCAN_ESR_ERR_STATE) || 633 flexcan_has_and_handle_berr(priv, reg_esr)) { 634 /* 635 * The error bits are cleared on read, 636 * save them for later use. 637 */ 638 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 639 flexcan_write(FLEXCAN_IFLAG_DEFAULT & 640 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); 641 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 642 ®s->ctrl); 643 napi_schedule(&priv->napi); 644 } 645 646 /* FIFO overflow */ 647 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 648 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); 649 dev->stats.rx_over_errors++; 650 dev->stats.rx_errors++; 651 } 652 653 /* transmission complete interrupt */ 654 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 655 stats->tx_bytes += can_get_echo_skb(dev, 0); 656 stats->tx_packets++; 657 can_led_event(dev, CAN_LED_EVENT_TX); 658 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); 659 netif_wake_queue(dev); 660 } 661 662 return IRQ_HANDLED; 663} 664 665static void flexcan_set_bittiming(struct net_device *dev) 666{ 667 const struct flexcan_priv *priv = netdev_priv(dev); 668 const struct can_bittiming *bt = &priv->can.bittiming; 669 struct flexcan_regs __iomem *regs = priv->base; 670 u32 reg; 671 672 reg = flexcan_read(®s->ctrl); 673 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 674 FLEXCAN_CTRL_RJW(0x3) | 675 FLEXCAN_CTRL_PSEG1(0x7) | 676 FLEXCAN_CTRL_PSEG2(0x7) | 677 FLEXCAN_CTRL_PROPSEG(0x7) | 678 FLEXCAN_CTRL_LPB | 679 FLEXCAN_CTRL_SMP | 680 FLEXCAN_CTRL_LOM); 681 682 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 683 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 684 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 685 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 686 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 687 688 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 689 reg |= FLEXCAN_CTRL_LPB; 690 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 691 reg |= FLEXCAN_CTRL_LOM; 692 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 693 reg |= FLEXCAN_CTRL_SMP; 694 695 netdev_info(dev, "writing ctrl=0x%08x\n", reg); 696 flexcan_write(reg, ®s->ctrl); 697 698 /* print chip status */ 699 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 700 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 701} 702 703/* 704 * flexcan_chip_start 705 * 706 * this functions is entered with clocks enabled 707 * 708 */ 709static int flexcan_chip_start(struct net_device *dev) 710{ 711 struct flexcan_priv *priv = netdev_priv(dev); 712 struct flexcan_regs __iomem *regs = priv->base; 713 unsigned int i; 714 int err; 715 u32 reg_mcr, reg_ctrl; 716 717 /* enable module */ 718 flexcan_chip_enable(priv); 719 720 /* soft reset */ 721 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 722 udelay(10); 723 724 reg_mcr = flexcan_read(®s->mcr); 725 if (reg_mcr & FLEXCAN_MCR_SOFTRST) { 726 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n", 727 reg_mcr); 728 err = -ENODEV; 729 goto out; 730 } 731 732 flexcan_set_bittiming(dev); 733 734 /* 735 * MCR 736 * 737 * enable freeze 738 * enable fifo 739 * halt now 740 * only supervisor access 741 * enable warning int 742 * choose format C 743 * disable local echo 744 * 745 */ 746 reg_mcr = flexcan_read(®s->mcr); 747 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 748 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 749 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS; 750 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); 751 flexcan_write(reg_mcr, ®s->mcr); 752 753 /* 754 * CTRL 755 * 756 * disable timer sync feature 757 * 758 * disable auto busoff recovery 759 * transmit lowest buffer first 760 * 761 * enable tx and rx warning interrupt 762 * enable bus off interrupt 763 * (== FLEXCAN_CTRL_ERR_STATE) 764 */ 765 reg_ctrl = flexcan_read(®s->ctrl); 766 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 767 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 768 FLEXCAN_CTRL_ERR_STATE; 769 /* 770 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), 771 * on most Flexcan cores, too. Otherwise we don't get 772 * any error warning or passive interrupts. 773 */ 774 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE || 775 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 776 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; 777 778 /* save for later use */ 779 priv->reg_ctrl_default = reg_ctrl; 780 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 781 flexcan_write(reg_ctrl, ®s->ctrl); 782 783 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) { 784 flexcan_write(0, ®s->cantxfg[i].can_ctrl); 785 flexcan_write(0, ®s->cantxfg[i].can_id); 786 flexcan_write(0, ®s->cantxfg[i].data[0]); 787 flexcan_write(0, ®s->cantxfg[i].data[1]); 788 789 /* put MB into rx queue */ 790 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4), 791 ®s->cantxfg[i].can_ctrl); 792 } 793 794 /* acceptance mask/acceptance code (accept everything) */ 795 flexcan_write(0x0, ®s->rxgmask); 796 flexcan_write(0x0, ®s->rx14mask); 797 flexcan_write(0x0, ®s->rx15mask); 798 799 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) 800 flexcan_write(0x0, ®s->rxfgmask); 801 802 flexcan_transceiver_switch(priv, 1); 803 804 /* synchronize with the can bus */ 805 reg_mcr = flexcan_read(®s->mcr); 806 reg_mcr &= ~FLEXCAN_MCR_HALT; 807 flexcan_write(reg_mcr, ®s->mcr); 808 809 priv->can.state = CAN_STATE_ERROR_ACTIVE; 810 811 /* enable FIFO interrupts */ 812 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 813 814 /* print chip status */ 815 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, 816 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 817 818 return 0; 819 820 out: 821 flexcan_chip_disable(priv); 822 return err; 823} 824 825/* 826 * flexcan_chip_stop 827 * 828 * this functions is entered with clocks enabled 829 * 830 */ 831static void flexcan_chip_stop(struct net_device *dev) 832{ 833 struct flexcan_priv *priv = netdev_priv(dev); 834 struct flexcan_regs __iomem *regs = priv->base; 835 u32 reg; 836 837 /* Disable all interrupts */ 838 flexcan_write(0, ®s->imask1); 839 840 /* Disable + halt module */ 841 reg = flexcan_read(®s->mcr); 842 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT; 843 flexcan_write(reg, ®s->mcr); 844 845 flexcan_transceiver_switch(priv, 0); 846 priv->can.state = CAN_STATE_STOPPED; 847 848 return; 849} 850 851static int flexcan_open(struct net_device *dev) 852{ 853 struct flexcan_priv *priv = netdev_priv(dev); 854 int err; 855 856 clk_prepare_enable(priv->clk_ipg); 857 clk_prepare_enable(priv->clk_per); 858 859 err = open_candev(dev); 860 if (err) 861 goto out; 862 863 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 864 if (err) 865 goto out_close; 866 867 /* start chip and queuing */ 868 err = flexcan_chip_start(dev); 869 if (err) 870 goto out_close; 871 872 can_led_event(dev, CAN_LED_EVENT_OPEN); 873 874 napi_enable(&priv->napi); 875 netif_start_queue(dev); 876 877 return 0; 878 879 out_close: 880 close_candev(dev); 881 out: 882 clk_disable_unprepare(priv->clk_per); 883 clk_disable_unprepare(priv->clk_ipg); 884 885 return err; 886} 887 888static int flexcan_close(struct net_device *dev) 889{ 890 struct flexcan_priv *priv = netdev_priv(dev); 891 892 netif_stop_queue(dev); 893 napi_disable(&priv->napi); 894 flexcan_chip_stop(dev); 895 896 free_irq(dev->irq, dev); 897 clk_disable_unprepare(priv->clk_per); 898 clk_disable_unprepare(priv->clk_ipg); 899 900 close_candev(dev); 901 902 can_led_event(dev, CAN_LED_EVENT_STOP); 903 904 return 0; 905} 906 907static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 908{ 909 int err; 910 911 switch (mode) { 912 case CAN_MODE_START: 913 err = flexcan_chip_start(dev); 914 if (err) 915 return err; 916 917 netif_wake_queue(dev); 918 break; 919 920 default: 921 return -EOPNOTSUPP; 922 } 923 924 return 0; 925} 926 927static const struct net_device_ops flexcan_netdev_ops = { 928 .ndo_open = flexcan_open, 929 .ndo_stop = flexcan_close, 930 .ndo_start_xmit = flexcan_start_xmit, 931}; 932 933static int register_flexcandev(struct net_device *dev) 934{ 935 struct flexcan_priv *priv = netdev_priv(dev); 936 struct flexcan_regs __iomem *regs = priv->base; 937 u32 reg, err; 938 939 clk_prepare_enable(priv->clk_ipg); 940 clk_prepare_enable(priv->clk_per); 941 942 /* select "bus clock", chip must be disabled */ 943 flexcan_chip_disable(priv); 944 reg = flexcan_read(®s->ctrl); 945 reg |= FLEXCAN_CTRL_CLK_SRC; 946 flexcan_write(reg, ®s->ctrl); 947 948 flexcan_chip_enable(priv); 949 950 /* set freeze, halt and activate FIFO, restrict register access */ 951 reg = flexcan_read(®s->mcr); 952 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 953 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 954 flexcan_write(reg, ®s->mcr); 955 956 /* 957 * Currently we only support newer versions of this core 958 * featuring a RX FIFO. Older cores found on some Coldfire 959 * derivates are not yet supported. 960 */ 961 reg = flexcan_read(®s->mcr); 962 if (!(reg & FLEXCAN_MCR_FEN)) { 963 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); 964 err = -ENODEV; 965 goto out; 966 } 967 968 err = register_candev(dev); 969 970 out: 971 /* disable core and turn off clocks */ 972 flexcan_chip_disable(priv); 973 clk_disable_unprepare(priv->clk_per); 974 clk_disable_unprepare(priv->clk_ipg); 975 976 return err; 977} 978 979static void unregister_flexcandev(struct net_device *dev) 980{ 981 unregister_candev(dev); 982} 983 984static const struct of_device_id flexcan_of_match[] = { 985 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, 986 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, 987 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, 988 { /* sentinel */ }, 989}; 990MODULE_DEVICE_TABLE(of, flexcan_of_match); 991 992static const struct platform_device_id flexcan_id_table[] = { 993 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, }, 994 { /* sentinel */ }, 995}; 996MODULE_DEVICE_TABLE(platform, flexcan_id_table); 997 998static int flexcan_probe(struct platform_device *pdev) 999{ 1000 const struct of_device_id *of_id; 1001 const struct flexcan_devtype_data *devtype_data; 1002 struct net_device *dev; 1003 struct flexcan_priv *priv; 1004 struct resource *mem; 1005 struct clk *clk_ipg = NULL, *clk_per = NULL; 1006 void __iomem *base; 1007 resource_size_t mem_size; 1008 int err, irq; 1009 u32 clock_freq = 0; 1010 1011 if (pdev->dev.of_node) 1012 of_property_read_u32(pdev->dev.of_node, 1013 "clock-frequency", &clock_freq); 1014 1015 if (!clock_freq) { 1016 clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1017 if (IS_ERR(clk_ipg)) { 1018 dev_err(&pdev->dev, "no ipg clock defined\n"); 1019 err = PTR_ERR(clk_ipg); 1020 goto failed_clock; 1021 } 1022 clock_freq = clk_get_rate(clk_ipg); 1023 1024 clk_per = devm_clk_get(&pdev->dev, "per"); 1025 if (IS_ERR(clk_per)) { 1026 dev_err(&pdev->dev, "no per clock defined\n"); 1027 err = PTR_ERR(clk_per); 1028 goto failed_clock; 1029 } 1030 } 1031 1032 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1033 irq = platform_get_irq(pdev, 0); 1034 if (!mem || irq <= 0) { 1035 err = -ENODEV; 1036 goto failed_get; 1037 } 1038 1039 mem_size = resource_size(mem); 1040 if (!request_mem_region(mem->start, mem_size, pdev->name)) { 1041 err = -EBUSY; 1042 goto failed_get; 1043 } 1044 1045 base = ioremap(mem->start, mem_size); 1046 if (!base) { 1047 err = -ENOMEM; 1048 goto failed_map; 1049 } 1050 1051 dev = alloc_candev(sizeof(struct flexcan_priv), 1); 1052 if (!dev) { 1053 err = -ENOMEM; 1054 goto failed_alloc; 1055 } 1056 1057 of_id = of_match_device(flexcan_of_match, &pdev->dev); 1058 if (of_id) { 1059 devtype_data = of_id->data; 1060 } else if (pdev->id_entry->driver_data) { 1061 devtype_data = (struct flexcan_devtype_data *) 1062 pdev->id_entry->driver_data; 1063 } else { 1064 err = -ENODEV; 1065 goto failed_devtype; 1066 } 1067 1068 dev->netdev_ops = &flexcan_netdev_ops; 1069 dev->irq = irq; 1070 dev->flags |= IFF_ECHO; 1071 1072 priv = netdev_priv(dev); 1073 priv->can.clock.freq = clock_freq; 1074 priv->can.bittiming_const = &flexcan_bittiming_const; 1075 priv->can.do_set_mode = flexcan_set_mode; 1076 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 1077 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1078 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 1079 CAN_CTRLMODE_BERR_REPORTING; 1080 priv->base = base; 1081 priv->dev = dev; 1082 priv->clk_ipg = clk_ipg; 1083 priv->clk_per = clk_per; 1084 priv->pdata = pdev->dev.platform_data; 1085 priv->devtype_data = devtype_data; 1086 1087 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); 1088 1089 dev_set_drvdata(&pdev->dev, dev); 1090 SET_NETDEV_DEV(dev, &pdev->dev); 1091 1092 err = register_flexcandev(dev); 1093 if (err) { 1094 dev_err(&pdev->dev, "registering netdev failed\n"); 1095 goto failed_register; 1096 } 1097 1098 devm_can_led_init(dev); 1099 1100 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1101 priv->base, dev->irq); 1102 1103 return 0; 1104 1105 failed_register: 1106 failed_devtype: 1107 free_candev(dev); 1108 failed_alloc: 1109 iounmap(base); 1110 failed_map: 1111 release_mem_region(mem->start, mem_size); 1112 failed_get: 1113 failed_clock: 1114 return err; 1115} 1116 1117static int flexcan_remove(struct platform_device *pdev) 1118{ 1119 struct net_device *dev = platform_get_drvdata(pdev); 1120 struct flexcan_priv *priv = netdev_priv(dev); 1121 struct resource *mem; 1122 1123 unregister_flexcandev(dev); 1124 iounmap(priv->base); 1125 1126 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1127 release_mem_region(mem->start, resource_size(mem)); 1128 1129 free_candev(dev); 1130 1131 return 0; 1132} 1133 1134#ifdef CONFIG_PM 1135static int flexcan_suspend(struct platform_device *pdev, pm_message_t state) 1136{ 1137 struct net_device *dev = platform_get_drvdata(pdev); 1138 struct flexcan_priv *priv = netdev_priv(dev); 1139 1140 flexcan_chip_disable(priv); 1141 1142 if (netif_running(dev)) { 1143 netif_stop_queue(dev); 1144 netif_device_detach(dev); 1145 } 1146 priv->can.state = CAN_STATE_SLEEPING; 1147 1148 return 0; 1149} 1150 1151static int flexcan_resume(struct platform_device *pdev) 1152{ 1153 struct net_device *dev = platform_get_drvdata(pdev); 1154 struct flexcan_priv *priv = netdev_priv(dev); 1155 1156 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1157 if (netif_running(dev)) { 1158 netif_device_attach(dev); 1159 netif_start_queue(dev); 1160 } 1161 flexcan_chip_enable(priv); 1162 1163 return 0; 1164} 1165#else 1166#define flexcan_suspend NULL 1167#define flexcan_resume NULL 1168#endif 1169 1170static struct platform_driver flexcan_driver = { 1171 .driver = { 1172 .name = DRV_NAME, 1173 .owner = THIS_MODULE, 1174 .of_match_table = flexcan_of_match, 1175 }, 1176 .probe = flexcan_probe, 1177 .remove = flexcan_remove, 1178 .suspend = flexcan_suspend, 1179 .resume = flexcan_resume, 1180 .id_table = flexcan_id_table, 1181}; 1182 1183module_platform_driver(flexcan_driver); 1184 1185MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 1186 "Marc Kleine-Budde <kernel@pengutronix.de>"); 1187MODULE_LICENSE("GPL v2"); 1188MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 1189