flexcan.c revision 61e271ee64f1da6f69e56419ecf2ca7330884564
1/* 2 * flexcan.c - FLEXCAN CAN controller driver 3 * 4 * Copyright (c) 2005-2006 Varma Electronics Oy 5 * Copyright (c) 2009 Sascha Hauer, Pengutronix 6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix 7 * 8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com> 9 * 10 * LICENCE: 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22#include <linux/netdevice.h> 23#include <linux/can.h> 24#include <linux/can/dev.h> 25#include <linux/can/error.h> 26#include <linux/can/platform/flexcan.h> 27#include <linux/clk.h> 28#include <linux/delay.h> 29#include <linux/if_arp.h> 30#include <linux/if_ether.h> 31#include <linux/interrupt.h> 32#include <linux/io.h> 33#include <linux/kernel.h> 34#include <linux/list.h> 35#include <linux/module.h> 36#include <linux/platform_device.h> 37 38#define DRV_NAME "flexcan" 39 40/* 8 for RX fifo and 2 error handling */ 41#define FLEXCAN_NAPI_WEIGHT (8 + 2) 42 43/* FLEXCAN module configuration register (CANMCR) bits */ 44#define FLEXCAN_MCR_MDIS BIT(31) 45#define FLEXCAN_MCR_FRZ BIT(30) 46#define FLEXCAN_MCR_FEN BIT(29) 47#define FLEXCAN_MCR_HALT BIT(28) 48#define FLEXCAN_MCR_NOT_RDY BIT(27) 49#define FLEXCAN_MCR_WAK_MSK BIT(26) 50#define FLEXCAN_MCR_SOFTRST BIT(25) 51#define FLEXCAN_MCR_FRZ_ACK BIT(24) 52#define FLEXCAN_MCR_SUPV BIT(23) 53#define FLEXCAN_MCR_SLF_WAK BIT(22) 54#define FLEXCAN_MCR_WRN_EN BIT(21) 55#define FLEXCAN_MCR_LPM_ACK BIT(20) 56#define FLEXCAN_MCR_WAK_SRC BIT(19) 57#define FLEXCAN_MCR_DOZE BIT(18) 58#define FLEXCAN_MCR_SRX_DIS BIT(17) 59#define FLEXCAN_MCR_BCC BIT(16) 60#define FLEXCAN_MCR_LPRIO_EN BIT(13) 61#define FLEXCAN_MCR_AEN BIT(12) 62#define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf) 63#define FLEXCAN_MCR_IDAM_A (0 << 8) 64#define FLEXCAN_MCR_IDAM_B (1 << 8) 65#define FLEXCAN_MCR_IDAM_C (2 << 8) 66#define FLEXCAN_MCR_IDAM_D (3 << 8) 67 68/* FLEXCAN control register (CANCTRL) bits */ 69#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 70#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 71#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 72#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 73#define FLEXCAN_CTRL_BOFF_MSK BIT(15) 74#define FLEXCAN_CTRL_ERR_MSK BIT(14) 75#define FLEXCAN_CTRL_CLK_SRC BIT(13) 76#define FLEXCAN_CTRL_LPB BIT(12) 77#define FLEXCAN_CTRL_TWRN_MSK BIT(11) 78#define FLEXCAN_CTRL_RWRN_MSK BIT(10) 79#define FLEXCAN_CTRL_SMP BIT(7) 80#define FLEXCAN_CTRL_BOFF_REC BIT(6) 81#define FLEXCAN_CTRL_TSYN BIT(5) 82#define FLEXCAN_CTRL_LBUF BIT(4) 83#define FLEXCAN_CTRL_LOM BIT(3) 84#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 85#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 86#define FLEXCAN_CTRL_ERR_STATE \ 87 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 88 FLEXCAN_CTRL_BOFF_MSK) 89#define FLEXCAN_CTRL_ERR_ALL \ 90 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 91 92/* FLEXCAN error and status register (ESR) bits */ 93#define FLEXCAN_ESR_TWRN_INT BIT(17) 94#define FLEXCAN_ESR_RWRN_INT BIT(16) 95#define FLEXCAN_ESR_BIT1_ERR BIT(15) 96#define FLEXCAN_ESR_BIT0_ERR BIT(14) 97#define FLEXCAN_ESR_ACK_ERR BIT(13) 98#define FLEXCAN_ESR_CRC_ERR BIT(12) 99#define FLEXCAN_ESR_FRM_ERR BIT(11) 100#define FLEXCAN_ESR_STF_ERR BIT(10) 101#define FLEXCAN_ESR_TX_WRN BIT(9) 102#define FLEXCAN_ESR_RX_WRN BIT(8) 103#define FLEXCAN_ESR_IDLE BIT(7) 104#define FLEXCAN_ESR_TXRX BIT(6) 105#define FLEXCAN_EST_FLT_CONF_SHIFT (4) 106#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 107#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 108#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 109#define FLEXCAN_ESR_BOFF_INT BIT(2) 110#define FLEXCAN_ESR_ERR_INT BIT(1) 111#define FLEXCAN_ESR_WAK_INT BIT(0) 112#define FLEXCAN_ESR_ERR_BUS \ 113 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 114 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 115 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 116#define FLEXCAN_ESR_ERR_STATE \ 117 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 118#define FLEXCAN_ESR_ERR_ALL \ 119 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 120 121/* FLEXCAN interrupt flag register (IFLAG) bits */ 122#define FLEXCAN_TX_BUF_ID 8 123#define FLEXCAN_IFLAG_BUF(x) BIT(x) 124#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 125#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 126#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 127#define FLEXCAN_IFLAG_DEFAULT \ 128 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ 129 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) 130 131/* FLEXCAN message buffers */ 132#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) 133#define FLEXCAN_MB_CNT_SRR BIT(22) 134#define FLEXCAN_MB_CNT_IDE BIT(21) 135#define FLEXCAN_MB_CNT_RTR BIT(20) 136#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 137#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 138 139#define FLEXCAN_MB_CODE_MASK (0xf0ffffff) 140 141/* Structure of the message buffer */ 142struct flexcan_mb { 143 u32 can_ctrl; 144 u32 can_id; 145 u32 data[2]; 146}; 147 148/* Structure of the hardware registers */ 149struct flexcan_regs { 150 u32 mcr; /* 0x00 */ 151 u32 ctrl; /* 0x04 */ 152 u32 timer; /* 0x08 */ 153 u32 _reserved1; /* 0x0c */ 154 u32 rxgmask; /* 0x10 */ 155 u32 rx14mask; /* 0x14 */ 156 u32 rx15mask; /* 0x18 */ 157 u32 ecr; /* 0x1c */ 158 u32 esr; /* 0x20 */ 159 u32 imask2; /* 0x24 */ 160 u32 imask1; /* 0x28 */ 161 u32 iflag2; /* 0x2c */ 162 u32 iflag1; /* 0x30 */ 163 u32 _reserved2[19]; 164 struct flexcan_mb cantxfg[64]; 165}; 166 167struct flexcan_priv { 168 struct can_priv can; 169 struct net_device *dev; 170 struct napi_struct napi; 171 172 void __iomem *base; 173 u32 reg_esr; 174 u32 reg_ctrl_default; 175 176 struct clk *clk; 177 struct flexcan_platform_data *pdata; 178}; 179 180static struct can_bittiming_const flexcan_bittiming_const = { 181 .name = DRV_NAME, 182 .tseg1_min = 4, 183 .tseg1_max = 16, 184 .tseg2_min = 2, 185 .tseg2_max = 8, 186 .sjw_max = 4, 187 .brp_min = 1, 188 .brp_max = 256, 189 .brp_inc = 1, 190}; 191 192/* 193 * Abstract off the read/write for arm versus ppc. 194 */ 195#if defined(__BIG_ENDIAN) 196static inline u32 flexcan_read(void __iomem *addr) 197{ 198 return in_be32(addr); 199} 200 201static inline void flexcan_write(u32 val, void __iomem *addr) 202{ 203 out_be32(addr, val); 204} 205#else 206static inline u32 flexcan_read(void __iomem *addr) 207{ 208 return readl(addr); 209} 210 211static inline void flexcan_write(u32 val, void __iomem *addr) 212{ 213 writel(val, addr); 214} 215#endif 216 217/* 218 * Swtich transceiver on or off 219 */ 220static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on) 221{ 222 if (priv->pdata && priv->pdata->transceiver_switch) 223 priv->pdata->transceiver_switch(on); 224} 225 226static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, 227 u32 reg_esr) 228{ 229 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 230 (reg_esr & FLEXCAN_ESR_ERR_BUS); 231} 232 233static inline void flexcan_chip_enable(struct flexcan_priv *priv) 234{ 235 struct flexcan_regs __iomem *regs = priv->base; 236 u32 reg; 237 238 reg = flexcan_read(®s->mcr); 239 reg &= ~FLEXCAN_MCR_MDIS; 240 flexcan_write(reg, ®s->mcr); 241 242 udelay(10); 243} 244 245static inline void flexcan_chip_disable(struct flexcan_priv *priv) 246{ 247 struct flexcan_regs __iomem *regs = priv->base; 248 u32 reg; 249 250 reg = flexcan_read(®s->mcr); 251 reg |= FLEXCAN_MCR_MDIS; 252 flexcan_write(reg, ®s->mcr); 253} 254 255static int flexcan_get_berr_counter(const struct net_device *dev, 256 struct can_berr_counter *bec) 257{ 258 const struct flexcan_priv *priv = netdev_priv(dev); 259 struct flexcan_regs __iomem *regs = priv->base; 260 u32 reg = flexcan_read(®s->ecr); 261 262 bec->txerr = (reg >> 0) & 0xff; 263 bec->rxerr = (reg >> 8) & 0xff; 264 265 return 0; 266} 267 268static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 269{ 270 const struct flexcan_priv *priv = netdev_priv(dev); 271 struct net_device_stats *stats = &dev->stats; 272 struct flexcan_regs __iomem *regs = priv->base; 273 struct can_frame *cf = (struct can_frame *)skb->data; 274 u32 can_id; 275 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); 276 277 if (can_dropped_invalid_skb(dev, skb)) 278 return NETDEV_TX_OK; 279 280 netif_stop_queue(dev); 281 282 if (cf->can_id & CAN_EFF_FLAG) { 283 can_id = cf->can_id & CAN_EFF_MASK; 284 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 285 } else { 286 can_id = (cf->can_id & CAN_SFF_MASK) << 18; 287 } 288 289 if (cf->can_id & CAN_RTR_FLAG) 290 ctrl |= FLEXCAN_MB_CNT_RTR; 291 292 if (cf->can_dlc > 0) { 293 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 294 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 295 } 296 if (cf->can_dlc > 3) { 297 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 298 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 299 } 300 301 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 302 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 303 304 kfree_skb(skb); 305 306 /* tx_packets is incremented in flexcan_irq */ 307 stats->tx_bytes += cf->can_dlc; 308 309 return NETDEV_TX_OK; 310} 311 312static void do_bus_err(struct net_device *dev, 313 struct can_frame *cf, u32 reg_esr) 314{ 315 struct flexcan_priv *priv = netdev_priv(dev); 316 int rx_errors = 0, tx_errors = 0; 317 318 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 319 320 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 321 dev_dbg(dev->dev.parent, "BIT1_ERR irq\n"); 322 cf->data[2] |= CAN_ERR_PROT_BIT1; 323 tx_errors = 1; 324 } 325 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 326 dev_dbg(dev->dev.parent, "BIT0_ERR irq\n"); 327 cf->data[2] |= CAN_ERR_PROT_BIT0; 328 tx_errors = 1; 329 } 330 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 331 dev_dbg(dev->dev.parent, "ACK_ERR irq\n"); 332 cf->can_id |= CAN_ERR_ACK; 333 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 334 tx_errors = 1; 335 } 336 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 337 dev_dbg(dev->dev.parent, "CRC_ERR irq\n"); 338 cf->data[2] |= CAN_ERR_PROT_BIT; 339 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 340 rx_errors = 1; 341 } 342 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 343 dev_dbg(dev->dev.parent, "FRM_ERR irq\n"); 344 cf->data[2] |= CAN_ERR_PROT_FORM; 345 rx_errors = 1; 346 } 347 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 348 dev_dbg(dev->dev.parent, "STF_ERR irq\n"); 349 cf->data[2] |= CAN_ERR_PROT_STUFF; 350 rx_errors = 1; 351 } 352 353 priv->can.can_stats.bus_error++; 354 if (rx_errors) 355 dev->stats.rx_errors++; 356 if (tx_errors) 357 dev->stats.tx_errors++; 358} 359 360static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) 361{ 362 struct sk_buff *skb; 363 struct can_frame *cf; 364 365 skb = alloc_can_err_skb(dev, &cf); 366 if (unlikely(!skb)) 367 return 0; 368 369 do_bus_err(dev, cf, reg_esr); 370 netif_receive_skb(skb); 371 372 dev->stats.rx_packets++; 373 dev->stats.rx_bytes += cf->can_dlc; 374 375 return 1; 376} 377 378static void do_state(struct net_device *dev, 379 struct can_frame *cf, enum can_state new_state) 380{ 381 struct flexcan_priv *priv = netdev_priv(dev); 382 struct can_berr_counter bec; 383 384 flexcan_get_berr_counter(dev, &bec); 385 386 switch (priv->can.state) { 387 case CAN_STATE_ERROR_ACTIVE: 388 /* 389 * from: ERROR_ACTIVE 390 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 391 * => : there was a warning int 392 */ 393 if (new_state >= CAN_STATE_ERROR_WARNING && 394 new_state <= CAN_STATE_BUS_OFF) { 395 dev_dbg(dev->dev.parent, "Error Warning IRQ\n"); 396 priv->can.can_stats.error_warning++; 397 398 cf->can_id |= CAN_ERR_CRTL; 399 cf->data[1] = (bec.txerr > bec.rxerr) ? 400 CAN_ERR_CRTL_TX_WARNING : 401 CAN_ERR_CRTL_RX_WARNING; 402 } 403 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 404 /* 405 * from: ERROR_ACTIVE, ERROR_WARNING 406 * to : ERROR_PASSIVE, BUS_OFF 407 * => : error passive int 408 */ 409 if (new_state >= CAN_STATE_ERROR_PASSIVE && 410 new_state <= CAN_STATE_BUS_OFF) { 411 dev_dbg(dev->dev.parent, "Error Passive IRQ\n"); 412 priv->can.can_stats.error_passive++; 413 414 cf->can_id |= CAN_ERR_CRTL; 415 cf->data[1] = (bec.txerr > bec.rxerr) ? 416 CAN_ERR_CRTL_TX_PASSIVE : 417 CAN_ERR_CRTL_RX_PASSIVE; 418 } 419 break; 420 case CAN_STATE_BUS_OFF: 421 dev_err(dev->dev.parent, 422 "BUG! hardware recovered automatically from BUS_OFF\n"); 423 break; 424 default: 425 break; 426 } 427 428 /* process state changes depending on the new state */ 429 switch (new_state) { 430 case CAN_STATE_ERROR_ACTIVE: 431 dev_dbg(dev->dev.parent, "Error Active\n"); 432 cf->can_id |= CAN_ERR_PROT; 433 cf->data[2] = CAN_ERR_PROT_ACTIVE; 434 break; 435 case CAN_STATE_BUS_OFF: 436 cf->can_id |= CAN_ERR_BUSOFF; 437 can_bus_off(dev); 438 break; 439 default: 440 break; 441 } 442} 443 444static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) 445{ 446 struct flexcan_priv *priv = netdev_priv(dev); 447 struct sk_buff *skb; 448 struct can_frame *cf; 449 enum can_state new_state; 450 int flt; 451 452 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 453 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 454 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | 455 FLEXCAN_ESR_RX_WRN)))) 456 new_state = CAN_STATE_ERROR_ACTIVE; 457 else 458 new_state = CAN_STATE_ERROR_WARNING; 459 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) 460 new_state = CAN_STATE_ERROR_PASSIVE; 461 else 462 new_state = CAN_STATE_BUS_OFF; 463 464 /* state hasn't changed */ 465 if (likely(new_state == priv->can.state)) 466 return 0; 467 468 skb = alloc_can_err_skb(dev, &cf); 469 if (unlikely(!skb)) 470 return 0; 471 472 do_state(dev, cf, new_state); 473 priv->can.state = new_state; 474 netif_receive_skb(skb); 475 476 dev->stats.rx_packets++; 477 dev->stats.rx_bytes += cf->can_dlc; 478 479 return 1; 480} 481 482static void flexcan_read_fifo(const struct net_device *dev, 483 struct can_frame *cf) 484{ 485 const struct flexcan_priv *priv = netdev_priv(dev); 486 struct flexcan_regs __iomem *regs = priv->base; 487 struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; 488 u32 reg_ctrl, reg_id; 489 490 reg_ctrl = flexcan_read(&mb->can_ctrl); 491 reg_id = flexcan_read(&mb->can_id); 492 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 493 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 494 else 495 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; 496 497 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 498 cf->can_id |= CAN_RTR_FLAG; 499 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 500 501 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); 502 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); 503 504 /* mark as read */ 505 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 506 flexcan_read(®s->timer); 507} 508 509static int flexcan_read_frame(struct net_device *dev) 510{ 511 struct net_device_stats *stats = &dev->stats; 512 struct can_frame *cf; 513 struct sk_buff *skb; 514 515 skb = alloc_can_skb(dev, &cf); 516 if (unlikely(!skb)) { 517 stats->rx_dropped++; 518 return 0; 519 } 520 521 flexcan_read_fifo(dev, cf); 522 netif_receive_skb(skb); 523 524 stats->rx_packets++; 525 stats->rx_bytes += cf->can_dlc; 526 527 return 1; 528} 529 530static int flexcan_poll(struct napi_struct *napi, int quota) 531{ 532 struct net_device *dev = napi->dev; 533 const struct flexcan_priv *priv = netdev_priv(dev); 534 struct flexcan_regs __iomem *regs = priv->base; 535 u32 reg_iflag1, reg_esr; 536 int work_done = 0; 537 538 /* 539 * The error bits are cleared on read, 540 * use saved value from irq handler. 541 */ 542 reg_esr = flexcan_read(®s->esr) | priv->reg_esr; 543 544 /* handle state changes */ 545 work_done += flexcan_poll_state(dev, reg_esr); 546 547 /* handle RX-FIFO */ 548 reg_iflag1 = flexcan_read(®s->iflag1); 549 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 550 work_done < quota) { 551 work_done += flexcan_read_frame(dev); 552 reg_iflag1 = flexcan_read(®s->iflag1); 553 } 554 555 /* report bus errors */ 556 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) 557 work_done += flexcan_poll_bus_err(dev, reg_esr); 558 559 if (work_done < quota) { 560 napi_complete(napi); 561 /* enable IRQs */ 562 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 563 flexcan_write(priv->reg_ctrl_default, ®s->ctrl); 564 } 565 566 return work_done; 567} 568 569static irqreturn_t flexcan_irq(int irq, void *dev_id) 570{ 571 struct net_device *dev = dev_id; 572 struct net_device_stats *stats = &dev->stats; 573 struct flexcan_priv *priv = netdev_priv(dev); 574 struct flexcan_regs __iomem *regs = priv->base; 575 u32 reg_iflag1, reg_esr; 576 577 reg_iflag1 = flexcan_read(®s->iflag1); 578 reg_esr = flexcan_read(®s->esr); 579 flexcan_write(FLEXCAN_ESR_ERR_INT, ®s->esr); /* ACK err IRQ */ 580 581 /* 582 * schedule NAPI in case of: 583 * - rx IRQ 584 * - state change IRQ 585 * - bus error IRQ and bus error reporting is activated 586 */ 587 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || 588 (reg_esr & FLEXCAN_ESR_ERR_STATE) || 589 flexcan_has_and_handle_berr(priv, reg_esr)) { 590 /* 591 * The error bits are cleared on read, 592 * save them for later use. 593 */ 594 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 595 flexcan_write(FLEXCAN_IFLAG_DEFAULT & 596 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); 597 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 598 ®s->ctrl); 599 napi_schedule(&priv->napi); 600 } 601 602 /* FIFO overflow */ 603 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 604 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); 605 dev->stats.rx_over_errors++; 606 dev->stats.rx_errors++; 607 } 608 609 /* transmission complete interrupt */ 610 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 611 /* tx_bytes is incremented in flexcan_start_xmit */ 612 stats->tx_packets++; 613 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); 614 netif_wake_queue(dev); 615 } 616 617 return IRQ_HANDLED; 618} 619 620static void flexcan_set_bittiming(struct net_device *dev) 621{ 622 const struct flexcan_priv *priv = netdev_priv(dev); 623 const struct can_bittiming *bt = &priv->can.bittiming; 624 struct flexcan_regs __iomem *regs = priv->base; 625 u32 reg; 626 627 reg = flexcan_read(®s->ctrl); 628 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 629 FLEXCAN_CTRL_RJW(0x3) | 630 FLEXCAN_CTRL_PSEG1(0x7) | 631 FLEXCAN_CTRL_PSEG2(0x7) | 632 FLEXCAN_CTRL_PROPSEG(0x7) | 633 FLEXCAN_CTRL_LPB | 634 FLEXCAN_CTRL_SMP | 635 FLEXCAN_CTRL_LOM); 636 637 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 638 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 639 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 640 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 641 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 642 643 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 644 reg |= FLEXCAN_CTRL_LPB; 645 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 646 reg |= FLEXCAN_CTRL_LOM; 647 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 648 reg |= FLEXCAN_CTRL_SMP; 649 650 dev_info(dev->dev.parent, "writing ctrl=0x%08x\n", reg); 651 flexcan_write(reg, ®s->ctrl); 652 653 /* print chip status */ 654 dev_dbg(dev->dev.parent, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 655 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 656} 657 658/* 659 * flexcan_chip_start 660 * 661 * this functions is entered with clocks enabled 662 * 663 */ 664static int flexcan_chip_start(struct net_device *dev) 665{ 666 struct flexcan_priv *priv = netdev_priv(dev); 667 struct flexcan_regs __iomem *regs = priv->base; 668 unsigned int i; 669 int err; 670 u32 reg_mcr, reg_ctrl; 671 672 /* enable module */ 673 flexcan_chip_enable(priv); 674 675 /* soft reset */ 676 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 677 udelay(10); 678 679 reg_mcr = flexcan_read(®s->mcr); 680 if (reg_mcr & FLEXCAN_MCR_SOFTRST) { 681 dev_err(dev->dev.parent, 682 "Failed to softreset can module (mcr=0x%08x)\n", 683 reg_mcr); 684 err = -ENODEV; 685 goto out; 686 } 687 688 flexcan_set_bittiming(dev); 689 690 /* 691 * MCR 692 * 693 * enable freeze 694 * enable fifo 695 * halt now 696 * only supervisor access 697 * enable warning int 698 * choose format C 699 * 700 */ 701 reg_mcr = flexcan_read(®s->mcr); 702 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 703 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 704 FLEXCAN_MCR_IDAM_C; 705 dev_dbg(dev->dev.parent, "%s: writing mcr=0x%08x", __func__, reg_mcr); 706 flexcan_write(reg_mcr, ®s->mcr); 707 708 /* 709 * CTRL 710 * 711 * disable timer sync feature 712 * 713 * disable auto busoff recovery 714 * transmit lowest buffer first 715 * 716 * enable tx and rx warning interrupt 717 * enable bus off interrupt 718 * (== FLEXCAN_CTRL_ERR_STATE) 719 * 720 * _note_: we enable the "error interrupt" 721 * (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any 722 * warning or bus passive interrupts. 723 */ 724 reg_ctrl = flexcan_read(®s->ctrl); 725 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 726 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 727 FLEXCAN_CTRL_ERR_STATE | FLEXCAN_CTRL_ERR_MSK; 728 729 /* save for later use */ 730 priv->reg_ctrl_default = reg_ctrl; 731 dev_dbg(dev->dev.parent, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 732 flexcan_write(reg_ctrl, ®s->ctrl); 733 734 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) { 735 flexcan_write(0, ®s->cantxfg[i].can_ctrl); 736 flexcan_write(0, ®s->cantxfg[i].can_id); 737 flexcan_write(0, ®s->cantxfg[i].data[0]); 738 flexcan_write(0, ®s->cantxfg[i].data[1]); 739 740 /* put MB into rx queue */ 741 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4), 742 ®s->cantxfg[i].can_ctrl); 743 } 744 745 /* acceptance mask/acceptance code (accept everything) */ 746 flexcan_write(0x0, ®s->rxgmask); 747 flexcan_write(0x0, ®s->rx14mask); 748 flexcan_write(0x0, ®s->rx15mask); 749 750 flexcan_transceiver_switch(priv, 1); 751 752 /* synchronize with the can bus */ 753 reg_mcr = flexcan_read(®s->mcr); 754 reg_mcr &= ~FLEXCAN_MCR_HALT; 755 flexcan_write(reg_mcr, ®s->mcr); 756 757 priv->can.state = CAN_STATE_ERROR_ACTIVE; 758 759 /* enable FIFO interrupts */ 760 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 761 762 /* print chip status */ 763 dev_dbg(dev->dev.parent, "%s: reading mcr=0x%08x ctrl=0x%08x\n", 764 __func__, flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 765 766 return 0; 767 768 out: 769 flexcan_chip_disable(priv); 770 return err; 771} 772 773/* 774 * flexcan_chip_stop 775 * 776 * this functions is entered with clocks enabled 777 * 778 */ 779static void flexcan_chip_stop(struct net_device *dev) 780{ 781 struct flexcan_priv *priv = netdev_priv(dev); 782 struct flexcan_regs __iomem *regs = priv->base; 783 u32 reg; 784 785 /* Disable all interrupts */ 786 flexcan_write(0, ®s->imask1); 787 788 /* Disable + halt module */ 789 reg = flexcan_read(®s->mcr); 790 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT; 791 flexcan_write(reg, ®s->mcr); 792 793 flexcan_transceiver_switch(priv, 0); 794 priv->can.state = CAN_STATE_STOPPED; 795 796 return; 797} 798 799static int flexcan_open(struct net_device *dev) 800{ 801 struct flexcan_priv *priv = netdev_priv(dev); 802 int err; 803 804 clk_enable(priv->clk); 805 806 err = open_candev(dev); 807 if (err) 808 goto out; 809 810 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 811 if (err) 812 goto out_close; 813 814 /* start chip and queuing */ 815 err = flexcan_chip_start(dev); 816 if (err) 817 goto out_close; 818 napi_enable(&priv->napi); 819 netif_start_queue(dev); 820 821 return 0; 822 823 out_close: 824 close_candev(dev); 825 out: 826 clk_disable(priv->clk); 827 828 return err; 829} 830 831static int flexcan_close(struct net_device *dev) 832{ 833 struct flexcan_priv *priv = netdev_priv(dev); 834 835 netif_stop_queue(dev); 836 napi_disable(&priv->napi); 837 flexcan_chip_stop(dev); 838 839 free_irq(dev->irq, dev); 840 clk_disable(priv->clk); 841 842 close_candev(dev); 843 844 return 0; 845} 846 847static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 848{ 849 int err; 850 851 switch (mode) { 852 case CAN_MODE_START: 853 err = flexcan_chip_start(dev); 854 if (err) 855 return err; 856 857 netif_wake_queue(dev); 858 break; 859 860 default: 861 return -EOPNOTSUPP; 862 } 863 864 return 0; 865} 866 867static const struct net_device_ops flexcan_netdev_ops = { 868 .ndo_open = flexcan_open, 869 .ndo_stop = flexcan_close, 870 .ndo_start_xmit = flexcan_start_xmit, 871}; 872 873static int __devinit register_flexcandev(struct net_device *dev) 874{ 875 struct flexcan_priv *priv = netdev_priv(dev); 876 struct flexcan_regs __iomem *regs = priv->base; 877 u32 reg, err; 878 879 clk_enable(priv->clk); 880 881 /* select "bus clock", chip must be disabled */ 882 flexcan_chip_disable(priv); 883 reg = flexcan_read(®s->ctrl); 884 reg |= FLEXCAN_CTRL_CLK_SRC; 885 flexcan_write(reg, ®s->ctrl); 886 887 flexcan_chip_enable(priv); 888 889 /* set freeze, halt and activate FIFO, restrict register access */ 890 reg = flexcan_read(®s->mcr); 891 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 892 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 893 flexcan_write(reg, ®s->mcr); 894 895 /* 896 * Currently we only support newer versions of this core 897 * featuring a RX FIFO. Older cores found on some Coldfire 898 * derivates are not yet supported. 899 */ 900 reg = flexcan_read(®s->mcr); 901 if (!(reg & FLEXCAN_MCR_FEN)) { 902 dev_err(dev->dev.parent, 903 "Could not enable RX FIFO, unsupported core\n"); 904 err = -ENODEV; 905 goto out; 906 } 907 908 err = register_candev(dev); 909 910 out: 911 /* disable core and turn off clocks */ 912 flexcan_chip_disable(priv); 913 clk_disable(priv->clk); 914 915 return err; 916} 917 918static void __devexit unregister_flexcandev(struct net_device *dev) 919{ 920 unregister_candev(dev); 921} 922 923static int __devinit flexcan_probe(struct platform_device *pdev) 924{ 925 struct net_device *dev; 926 struct flexcan_priv *priv; 927 struct resource *mem; 928 struct clk *clk; 929 void __iomem *base; 930 resource_size_t mem_size; 931 int err, irq; 932 933 clk = clk_get(&pdev->dev, NULL); 934 if (IS_ERR(clk)) { 935 dev_err(&pdev->dev, "no clock defined\n"); 936 err = PTR_ERR(clk); 937 goto failed_clock; 938 } 939 940 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 941 irq = platform_get_irq(pdev, 0); 942 if (!mem || irq <= 0) { 943 err = -ENODEV; 944 goto failed_get; 945 } 946 947 mem_size = resource_size(mem); 948 if (!request_mem_region(mem->start, mem_size, pdev->name)) { 949 err = -EBUSY; 950 goto failed_get; 951 } 952 953 base = ioremap(mem->start, mem_size); 954 if (!base) { 955 err = -ENOMEM; 956 goto failed_map; 957 } 958 959 dev = alloc_candev(sizeof(struct flexcan_priv), 0); 960 if (!dev) { 961 err = -ENOMEM; 962 goto failed_alloc; 963 } 964 965 dev->netdev_ops = &flexcan_netdev_ops; 966 dev->irq = irq; 967 dev->flags |= IFF_ECHO; /* we support local echo in hardware */ 968 969 priv = netdev_priv(dev); 970 priv->can.clock.freq = clk_get_rate(clk); 971 priv->can.bittiming_const = &flexcan_bittiming_const; 972 priv->can.do_set_mode = flexcan_set_mode; 973 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 974 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 975 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 976 CAN_CTRLMODE_BERR_REPORTING; 977 priv->base = base; 978 priv->dev = dev; 979 priv->clk = clk; 980 priv->pdata = pdev->dev.platform_data; 981 982 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); 983 984 dev_set_drvdata(&pdev->dev, dev); 985 SET_NETDEV_DEV(dev, &pdev->dev); 986 987 err = register_flexcandev(dev); 988 if (err) { 989 dev_err(&pdev->dev, "registering netdev failed\n"); 990 goto failed_register; 991 } 992 993 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 994 priv->base, dev->irq); 995 996 return 0; 997 998 failed_register: 999 free_candev(dev); 1000 failed_alloc: 1001 iounmap(base); 1002 failed_map: 1003 release_mem_region(mem->start, mem_size); 1004 failed_get: 1005 clk_put(clk); 1006 failed_clock: 1007 return err; 1008} 1009 1010static int __devexit flexcan_remove(struct platform_device *pdev) 1011{ 1012 struct net_device *dev = platform_get_drvdata(pdev); 1013 struct flexcan_priv *priv = netdev_priv(dev); 1014 struct resource *mem; 1015 1016 unregister_flexcandev(dev); 1017 platform_set_drvdata(pdev, NULL); 1018 iounmap(priv->base); 1019 1020 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1021 release_mem_region(mem->start, resource_size(mem)); 1022 1023 clk_put(priv->clk); 1024 1025 free_candev(dev); 1026 1027 return 0; 1028} 1029 1030static struct platform_driver flexcan_driver = { 1031 .driver.name = DRV_NAME, 1032 .probe = flexcan_probe, 1033 .remove = __devexit_p(flexcan_remove), 1034}; 1035 1036static int __init flexcan_init(void) 1037{ 1038 pr_info("%s netdevice driver\n", DRV_NAME); 1039 return platform_driver_register(&flexcan_driver); 1040} 1041 1042static void __exit flexcan_exit(void) 1043{ 1044 platform_driver_unregister(&flexcan_driver); 1045 pr_info("%s: driver removed\n", DRV_NAME); 1046} 1047 1048module_init(flexcan_init); 1049module_exit(flexcan_exit); 1050 1051MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 1052 "Marc Kleine-Budde <kernel@pengutronix.de>"); 1053MODULE_LICENSE("GPL v2"); 1054MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 1055