flexcan.c revision 85f2f834e85517307f13e30e630a5fc86f757cb5
1/* 2 * flexcan.c - FLEXCAN CAN controller driver 3 * 4 * Copyright (c) 2005-2006 Varma Electronics Oy 5 * Copyright (c) 2009 Sascha Hauer, Pengutronix 6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix 7 * 8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com> 9 * 10 * LICENCE: 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22#include <linux/netdevice.h> 23#include <linux/can.h> 24#include <linux/can/dev.h> 25#include <linux/can/error.h> 26#include <linux/can/platform/flexcan.h> 27#include <linux/clk.h> 28#include <linux/delay.h> 29#include <linux/if_arp.h> 30#include <linux/if_ether.h> 31#include <linux/interrupt.h> 32#include <linux/io.h> 33#include <linux/kernel.h> 34#include <linux/list.h> 35#include <linux/module.h> 36#include <linux/of.h> 37#include <linux/platform_device.h> 38#include <linux/pinctrl/consumer.h> 39 40#define DRV_NAME "flexcan" 41 42/* 8 for RX fifo and 2 error handling */ 43#define FLEXCAN_NAPI_WEIGHT (8 + 2) 44 45/* FLEXCAN module configuration register (CANMCR) bits */ 46#define FLEXCAN_MCR_MDIS BIT(31) 47#define FLEXCAN_MCR_FRZ BIT(30) 48#define FLEXCAN_MCR_FEN BIT(29) 49#define FLEXCAN_MCR_HALT BIT(28) 50#define FLEXCAN_MCR_NOT_RDY BIT(27) 51#define FLEXCAN_MCR_WAK_MSK BIT(26) 52#define FLEXCAN_MCR_SOFTRST BIT(25) 53#define FLEXCAN_MCR_FRZ_ACK BIT(24) 54#define FLEXCAN_MCR_SUPV BIT(23) 55#define FLEXCAN_MCR_SLF_WAK BIT(22) 56#define FLEXCAN_MCR_WRN_EN BIT(21) 57#define FLEXCAN_MCR_LPM_ACK BIT(20) 58#define FLEXCAN_MCR_WAK_SRC BIT(19) 59#define FLEXCAN_MCR_DOZE BIT(18) 60#define FLEXCAN_MCR_SRX_DIS BIT(17) 61#define FLEXCAN_MCR_BCC BIT(16) 62#define FLEXCAN_MCR_LPRIO_EN BIT(13) 63#define FLEXCAN_MCR_AEN BIT(12) 64#define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf) 65#define FLEXCAN_MCR_IDAM_A (0 << 8) 66#define FLEXCAN_MCR_IDAM_B (1 << 8) 67#define FLEXCAN_MCR_IDAM_C (2 << 8) 68#define FLEXCAN_MCR_IDAM_D (3 << 8) 69 70/* FLEXCAN control register (CANCTRL) bits */ 71#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 72#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 73#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 74#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 75#define FLEXCAN_CTRL_BOFF_MSK BIT(15) 76#define FLEXCAN_CTRL_ERR_MSK BIT(14) 77#define FLEXCAN_CTRL_CLK_SRC BIT(13) 78#define FLEXCAN_CTRL_LPB BIT(12) 79#define FLEXCAN_CTRL_TWRN_MSK BIT(11) 80#define FLEXCAN_CTRL_RWRN_MSK BIT(10) 81#define FLEXCAN_CTRL_SMP BIT(7) 82#define FLEXCAN_CTRL_BOFF_REC BIT(6) 83#define FLEXCAN_CTRL_TSYN BIT(5) 84#define FLEXCAN_CTRL_LBUF BIT(4) 85#define FLEXCAN_CTRL_LOM BIT(3) 86#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 87#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 88#define FLEXCAN_CTRL_ERR_STATE \ 89 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 90 FLEXCAN_CTRL_BOFF_MSK) 91#define FLEXCAN_CTRL_ERR_ALL \ 92 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 93 94/* FLEXCAN error and status register (ESR) bits */ 95#define FLEXCAN_ESR_TWRN_INT BIT(17) 96#define FLEXCAN_ESR_RWRN_INT BIT(16) 97#define FLEXCAN_ESR_BIT1_ERR BIT(15) 98#define FLEXCAN_ESR_BIT0_ERR BIT(14) 99#define FLEXCAN_ESR_ACK_ERR BIT(13) 100#define FLEXCAN_ESR_CRC_ERR BIT(12) 101#define FLEXCAN_ESR_FRM_ERR BIT(11) 102#define FLEXCAN_ESR_STF_ERR BIT(10) 103#define FLEXCAN_ESR_TX_WRN BIT(9) 104#define FLEXCAN_ESR_RX_WRN BIT(8) 105#define FLEXCAN_ESR_IDLE BIT(7) 106#define FLEXCAN_ESR_TXRX BIT(6) 107#define FLEXCAN_EST_FLT_CONF_SHIFT (4) 108#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 109#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 110#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 111#define FLEXCAN_ESR_BOFF_INT BIT(2) 112#define FLEXCAN_ESR_ERR_INT BIT(1) 113#define FLEXCAN_ESR_WAK_INT BIT(0) 114#define FLEXCAN_ESR_ERR_BUS \ 115 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 116 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 117 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 118#define FLEXCAN_ESR_ERR_STATE \ 119 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 120#define FLEXCAN_ESR_ERR_ALL \ 121 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 122#define FLEXCAN_ESR_ALL_INT \ 123 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ 124 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) 125 126/* FLEXCAN interrupt flag register (IFLAG) bits */ 127#define FLEXCAN_TX_BUF_ID 8 128#define FLEXCAN_IFLAG_BUF(x) BIT(x) 129#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 130#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 131#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 132#define FLEXCAN_IFLAG_DEFAULT \ 133 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ 134 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) 135 136/* FLEXCAN message buffers */ 137#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) 138#define FLEXCAN_MB_CNT_SRR BIT(22) 139#define FLEXCAN_MB_CNT_IDE BIT(21) 140#define FLEXCAN_MB_CNT_RTR BIT(20) 141#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 142#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 143 144#define FLEXCAN_MB_CODE_MASK (0xf0ffffff) 145 146/* Structure of the message buffer */ 147struct flexcan_mb { 148 u32 can_ctrl; 149 u32 can_id; 150 u32 data[2]; 151}; 152 153/* Structure of the hardware registers */ 154struct flexcan_regs { 155 u32 mcr; /* 0x00 */ 156 u32 ctrl; /* 0x04 */ 157 u32 timer; /* 0x08 */ 158 u32 _reserved1; /* 0x0c */ 159 u32 rxgmask; /* 0x10 */ 160 u32 rx14mask; /* 0x14 */ 161 u32 rx15mask; /* 0x18 */ 162 u32 ecr; /* 0x1c */ 163 u32 esr; /* 0x20 */ 164 u32 imask2; /* 0x24 */ 165 u32 imask1; /* 0x28 */ 166 u32 iflag2; /* 0x2c */ 167 u32 iflag1; /* 0x30 */ 168 u32 _reserved2[19]; 169 struct flexcan_mb cantxfg[64]; 170}; 171 172struct flexcan_priv { 173 struct can_priv can; 174 struct net_device *dev; 175 struct napi_struct napi; 176 177 void __iomem *base; 178 u32 reg_esr; 179 u32 reg_ctrl_default; 180 181 struct clk *clk; 182 struct flexcan_platform_data *pdata; 183}; 184 185static struct can_bittiming_const flexcan_bittiming_const = { 186 .name = DRV_NAME, 187 .tseg1_min = 4, 188 .tseg1_max = 16, 189 .tseg2_min = 2, 190 .tseg2_max = 8, 191 .sjw_max = 4, 192 .brp_min = 1, 193 .brp_max = 256, 194 .brp_inc = 1, 195}; 196 197/* 198 * Abstract off the read/write for arm versus ppc. 199 */ 200#if defined(__BIG_ENDIAN) 201static inline u32 flexcan_read(void __iomem *addr) 202{ 203 return in_be32(addr); 204} 205 206static inline void flexcan_write(u32 val, void __iomem *addr) 207{ 208 out_be32(addr, val); 209} 210#else 211static inline u32 flexcan_read(void __iomem *addr) 212{ 213 return readl(addr); 214} 215 216static inline void flexcan_write(u32 val, void __iomem *addr) 217{ 218 writel(val, addr); 219} 220#endif 221 222/* 223 * Swtich transceiver on or off 224 */ 225static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on) 226{ 227 if (priv->pdata && priv->pdata->transceiver_switch) 228 priv->pdata->transceiver_switch(on); 229} 230 231static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, 232 u32 reg_esr) 233{ 234 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 235 (reg_esr & FLEXCAN_ESR_ERR_BUS); 236} 237 238static inline void flexcan_chip_enable(struct flexcan_priv *priv) 239{ 240 struct flexcan_regs __iomem *regs = priv->base; 241 u32 reg; 242 243 reg = flexcan_read(®s->mcr); 244 reg &= ~FLEXCAN_MCR_MDIS; 245 flexcan_write(reg, ®s->mcr); 246 247 udelay(10); 248} 249 250static inline void flexcan_chip_disable(struct flexcan_priv *priv) 251{ 252 struct flexcan_regs __iomem *regs = priv->base; 253 u32 reg; 254 255 reg = flexcan_read(®s->mcr); 256 reg |= FLEXCAN_MCR_MDIS; 257 flexcan_write(reg, ®s->mcr); 258} 259 260static int flexcan_get_berr_counter(const struct net_device *dev, 261 struct can_berr_counter *bec) 262{ 263 const struct flexcan_priv *priv = netdev_priv(dev); 264 struct flexcan_regs __iomem *regs = priv->base; 265 u32 reg = flexcan_read(®s->ecr); 266 267 bec->txerr = (reg >> 0) & 0xff; 268 bec->rxerr = (reg >> 8) & 0xff; 269 270 return 0; 271} 272 273static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 274{ 275 const struct flexcan_priv *priv = netdev_priv(dev); 276 struct flexcan_regs __iomem *regs = priv->base; 277 struct can_frame *cf = (struct can_frame *)skb->data; 278 u32 can_id; 279 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); 280 281 if (can_dropped_invalid_skb(dev, skb)) 282 return NETDEV_TX_OK; 283 284 netif_stop_queue(dev); 285 286 if (cf->can_id & CAN_EFF_FLAG) { 287 can_id = cf->can_id & CAN_EFF_MASK; 288 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 289 } else { 290 can_id = (cf->can_id & CAN_SFF_MASK) << 18; 291 } 292 293 if (cf->can_id & CAN_RTR_FLAG) 294 ctrl |= FLEXCAN_MB_CNT_RTR; 295 296 if (cf->can_dlc > 0) { 297 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 298 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 299 } 300 if (cf->can_dlc > 3) { 301 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 302 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 303 } 304 305 can_put_echo_skb(skb, dev, 0); 306 307 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 308 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 309 310 return NETDEV_TX_OK; 311} 312 313static void do_bus_err(struct net_device *dev, 314 struct can_frame *cf, u32 reg_esr) 315{ 316 struct flexcan_priv *priv = netdev_priv(dev); 317 int rx_errors = 0, tx_errors = 0; 318 319 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 320 321 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 322 netdev_dbg(dev, "BIT1_ERR irq\n"); 323 cf->data[2] |= CAN_ERR_PROT_BIT1; 324 tx_errors = 1; 325 } 326 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 327 netdev_dbg(dev, "BIT0_ERR irq\n"); 328 cf->data[2] |= CAN_ERR_PROT_BIT0; 329 tx_errors = 1; 330 } 331 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 332 netdev_dbg(dev, "ACK_ERR irq\n"); 333 cf->can_id |= CAN_ERR_ACK; 334 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 335 tx_errors = 1; 336 } 337 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 338 netdev_dbg(dev, "CRC_ERR irq\n"); 339 cf->data[2] |= CAN_ERR_PROT_BIT; 340 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 341 rx_errors = 1; 342 } 343 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 344 netdev_dbg(dev, "FRM_ERR irq\n"); 345 cf->data[2] |= CAN_ERR_PROT_FORM; 346 rx_errors = 1; 347 } 348 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 349 netdev_dbg(dev, "STF_ERR irq\n"); 350 cf->data[2] |= CAN_ERR_PROT_STUFF; 351 rx_errors = 1; 352 } 353 354 priv->can.can_stats.bus_error++; 355 if (rx_errors) 356 dev->stats.rx_errors++; 357 if (tx_errors) 358 dev->stats.tx_errors++; 359} 360 361static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) 362{ 363 struct sk_buff *skb; 364 struct can_frame *cf; 365 366 skb = alloc_can_err_skb(dev, &cf); 367 if (unlikely(!skb)) 368 return 0; 369 370 do_bus_err(dev, cf, reg_esr); 371 netif_receive_skb(skb); 372 373 dev->stats.rx_packets++; 374 dev->stats.rx_bytes += cf->can_dlc; 375 376 return 1; 377} 378 379static void do_state(struct net_device *dev, 380 struct can_frame *cf, enum can_state new_state) 381{ 382 struct flexcan_priv *priv = netdev_priv(dev); 383 struct can_berr_counter bec; 384 385 flexcan_get_berr_counter(dev, &bec); 386 387 switch (priv->can.state) { 388 case CAN_STATE_ERROR_ACTIVE: 389 /* 390 * from: ERROR_ACTIVE 391 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 392 * => : there was a warning int 393 */ 394 if (new_state >= CAN_STATE_ERROR_WARNING && 395 new_state <= CAN_STATE_BUS_OFF) { 396 netdev_dbg(dev, "Error Warning IRQ\n"); 397 priv->can.can_stats.error_warning++; 398 399 cf->can_id |= CAN_ERR_CRTL; 400 cf->data[1] = (bec.txerr > bec.rxerr) ? 401 CAN_ERR_CRTL_TX_WARNING : 402 CAN_ERR_CRTL_RX_WARNING; 403 } 404 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 405 /* 406 * from: ERROR_ACTIVE, ERROR_WARNING 407 * to : ERROR_PASSIVE, BUS_OFF 408 * => : error passive int 409 */ 410 if (new_state >= CAN_STATE_ERROR_PASSIVE && 411 new_state <= CAN_STATE_BUS_OFF) { 412 netdev_dbg(dev, "Error Passive IRQ\n"); 413 priv->can.can_stats.error_passive++; 414 415 cf->can_id |= CAN_ERR_CRTL; 416 cf->data[1] = (bec.txerr > bec.rxerr) ? 417 CAN_ERR_CRTL_TX_PASSIVE : 418 CAN_ERR_CRTL_RX_PASSIVE; 419 } 420 break; 421 case CAN_STATE_BUS_OFF: 422 netdev_err(dev, "BUG! " 423 "hardware recovered automatically from BUS_OFF\n"); 424 break; 425 default: 426 break; 427 } 428 429 /* process state changes depending on the new state */ 430 switch (new_state) { 431 case CAN_STATE_ERROR_ACTIVE: 432 netdev_dbg(dev, "Error Active\n"); 433 cf->can_id |= CAN_ERR_PROT; 434 cf->data[2] = CAN_ERR_PROT_ACTIVE; 435 break; 436 case CAN_STATE_BUS_OFF: 437 cf->can_id |= CAN_ERR_BUSOFF; 438 can_bus_off(dev); 439 break; 440 default: 441 break; 442 } 443} 444 445static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) 446{ 447 struct flexcan_priv *priv = netdev_priv(dev); 448 struct sk_buff *skb; 449 struct can_frame *cf; 450 enum can_state new_state; 451 int flt; 452 453 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 454 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 455 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | 456 FLEXCAN_ESR_RX_WRN)))) 457 new_state = CAN_STATE_ERROR_ACTIVE; 458 else 459 new_state = CAN_STATE_ERROR_WARNING; 460 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) 461 new_state = CAN_STATE_ERROR_PASSIVE; 462 else 463 new_state = CAN_STATE_BUS_OFF; 464 465 /* state hasn't changed */ 466 if (likely(new_state == priv->can.state)) 467 return 0; 468 469 skb = alloc_can_err_skb(dev, &cf); 470 if (unlikely(!skb)) 471 return 0; 472 473 do_state(dev, cf, new_state); 474 priv->can.state = new_state; 475 netif_receive_skb(skb); 476 477 dev->stats.rx_packets++; 478 dev->stats.rx_bytes += cf->can_dlc; 479 480 return 1; 481} 482 483static void flexcan_read_fifo(const struct net_device *dev, 484 struct can_frame *cf) 485{ 486 const struct flexcan_priv *priv = netdev_priv(dev); 487 struct flexcan_regs __iomem *regs = priv->base; 488 struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; 489 u32 reg_ctrl, reg_id; 490 491 reg_ctrl = flexcan_read(&mb->can_ctrl); 492 reg_id = flexcan_read(&mb->can_id); 493 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 494 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 495 else 496 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; 497 498 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 499 cf->can_id |= CAN_RTR_FLAG; 500 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 501 502 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); 503 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); 504 505 /* mark as read */ 506 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 507 flexcan_read(®s->timer); 508} 509 510static int flexcan_read_frame(struct net_device *dev) 511{ 512 struct net_device_stats *stats = &dev->stats; 513 struct can_frame *cf; 514 struct sk_buff *skb; 515 516 skb = alloc_can_skb(dev, &cf); 517 if (unlikely(!skb)) { 518 stats->rx_dropped++; 519 return 0; 520 } 521 522 flexcan_read_fifo(dev, cf); 523 netif_receive_skb(skb); 524 525 stats->rx_packets++; 526 stats->rx_bytes += cf->can_dlc; 527 528 return 1; 529} 530 531static int flexcan_poll(struct napi_struct *napi, int quota) 532{ 533 struct net_device *dev = napi->dev; 534 const struct flexcan_priv *priv = netdev_priv(dev); 535 struct flexcan_regs __iomem *regs = priv->base; 536 u32 reg_iflag1, reg_esr; 537 int work_done = 0; 538 539 /* 540 * The error bits are cleared on read, 541 * use saved value from irq handler. 542 */ 543 reg_esr = flexcan_read(®s->esr) | priv->reg_esr; 544 545 /* handle state changes */ 546 work_done += flexcan_poll_state(dev, reg_esr); 547 548 /* handle RX-FIFO */ 549 reg_iflag1 = flexcan_read(®s->iflag1); 550 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 551 work_done < quota) { 552 work_done += flexcan_read_frame(dev); 553 reg_iflag1 = flexcan_read(®s->iflag1); 554 } 555 556 /* report bus errors */ 557 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) 558 work_done += flexcan_poll_bus_err(dev, reg_esr); 559 560 if (work_done < quota) { 561 napi_complete(napi); 562 /* enable IRQs */ 563 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 564 flexcan_write(priv->reg_ctrl_default, ®s->ctrl); 565 } 566 567 return work_done; 568} 569 570static irqreturn_t flexcan_irq(int irq, void *dev_id) 571{ 572 struct net_device *dev = dev_id; 573 struct net_device_stats *stats = &dev->stats; 574 struct flexcan_priv *priv = netdev_priv(dev); 575 struct flexcan_regs __iomem *regs = priv->base; 576 u32 reg_iflag1, reg_esr; 577 578 reg_iflag1 = flexcan_read(®s->iflag1); 579 reg_esr = flexcan_read(®s->esr); 580 /* ACK all bus error and state change IRQ sources */ 581 if (reg_esr & FLEXCAN_ESR_ALL_INT) 582 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); 583 584 /* 585 * schedule NAPI in case of: 586 * - rx IRQ 587 * - state change IRQ 588 * - bus error IRQ and bus error reporting is activated 589 */ 590 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || 591 (reg_esr & FLEXCAN_ESR_ERR_STATE) || 592 flexcan_has_and_handle_berr(priv, reg_esr)) { 593 /* 594 * The error bits are cleared on read, 595 * save them for later use. 596 */ 597 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 598 flexcan_write(FLEXCAN_IFLAG_DEFAULT & 599 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); 600 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 601 ®s->ctrl); 602 napi_schedule(&priv->napi); 603 } 604 605 /* FIFO overflow */ 606 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 607 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); 608 dev->stats.rx_over_errors++; 609 dev->stats.rx_errors++; 610 } 611 612 /* transmission complete interrupt */ 613 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 614 stats->tx_bytes += can_get_echo_skb(dev, 0); 615 stats->tx_packets++; 616 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); 617 netif_wake_queue(dev); 618 } 619 620 return IRQ_HANDLED; 621} 622 623static void flexcan_set_bittiming(struct net_device *dev) 624{ 625 const struct flexcan_priv *priv = netdev_priv(dev); 626 const struct can_bittiming *bt = &priv->can.bittiming; 627 struct flexcan_regs __iomem *regs = priv->base; 628 u32 reg; 629 630 reg = flexcan_read(®s->ctrl); 631 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 632 FLEXCAN_CTRL_RJW(0x3) | 633 FLEXCAN_CTRL_PSEG1(0x7) | 634 FLEXCAN_CTRL_PSEG2(0x7) | 635 FLEXCAN_CTRL_PROPSEG(0x7) | 636 FLEXCAN_CTRL_LPB | 637 FLEXCAN_CTRL_SMP | 638 FLEXCAN_CTRL_LOM); 639 640 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 641 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 642 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 643 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 644 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 645 646 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 647 reg |= FLEXCAN_CTRL_LPB; 648 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 649 reg |= FLEXCAN_CTRL_LOM; 650 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 651 reg |= FLEXCAN_CTRL_SMP; 652 653 netdev_info(dev, "writing ctrl=0x%08x\n", reg); 654 flexcan_write(reg, ®s->ctrl); 655 656 /* print chip status */ 657 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 658 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 659} 660 661/* 662 * flexcan_chip_start 663 * 664 * this functions is entered with clocks enabled 665 * 666 */ 667static int flexcan_chip_start(struct net_device *dev) 668{ 669 struct flexcan_priv *priv = netdev_priv(dev); 670 struct flexcan_regs __iomem *regs = priv->base; 671 unsigned int i; 672 int err; 673 u32 reg_mcr, reg_ctrl; 674 675 /* enable module */ 676 flexcan_chip_enable(priv); 677 678 /* soft reset */ 679 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 680 udelay(10); 681 682 reg_mcr = flexcan_read(®s->mcr); 683 if (reg_mcr & FLEXCAN_MCR_SOFTRST) { 684 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n", 685 reg_mcr); 686 err = -ENODEV; 687 goto out; 688 } 689 690 flexcan_set_bittiming(dev); 691 692 /* 693 * MCR 694 * 695 * enable freeze 696 * enable fifo 697 * halt now 698 * only supervisor access 699 * enable warning int 700 * choose format C 701 * disable local echo 702 * 703 */ 704 reg_mcr = flexcan_read(®s->mcr); 705 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 706 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 707 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS; 708 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); 709 flexcan_write(reg_mcr, ®s->mcr); 710 711 /* 712 * CTRL 713 * 714 * disable timer sync feature 715 * 716 * disable auto busoff recovery 717 * transmit lowest buffer first 718 * 719 * enable tx and rx warning interrupt 720 * enable bus off interrupt 721 * (== FLEXCAN_CTRL_ERR_STATE) 722 * 723 * _note_: we enable the "error interrupt" 724 * (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any 725 * warning or bus passive interrupts. 726 */ 727 reg_ctrl = flexcan_read(®s->ctrl); 728 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 729 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 730 FLEXCAN_CTRL_ERR_STATE | FLEXCAN_CTRL_ERR_MSK; 731 732 /* save for later use */ 733 priv->reg_ctrl_default = reg_ctrl; 734 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 735 flexcan_write(reg_ctrl, ®s->ctrl); 736 737 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) { 738 flexcan_write(0, ®s->cantxfg[i].can_ctrl); 739 flexcan_write(0, ®s->cantxfg[i].can_id); 740 flexcan_write(0, ®s->cantxfg[i].data[0]); 741 flexcan_write(0, ®s->cantxfg[i].data[1]); 742 743 /* put MB into rx queue */ 744 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4), 745 ®s->cantxfg[i].can_ctrl); 746 } 747 748 /* acceptance mask/acceptance code (accept everything) */ 749 flexcan_write(0x0, ®s->rxgmask); 750 flexcan_write(0x0, ®s->rx14mask); 751 flexcan_write(0x0, ®s->rx15mask); 752 753 flexcan_transceiver_switch(priv, 1); 754 755 /* synchronize with the can bus */ 756 reg_mcr = flexcan_read(®s->mcr); 757 reg_mcr &= ~FLEXCAN_MCR_HALT; 758 flexcan_write(reg_mcr, ®s->mcr); 759 760 priv->can.state = CAN_STATE_ERROR_ACTIVE; 761 762 /* enable FIFO interrupts */ 763 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 764 765 /* print chip status */ 766 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, 767 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 768 769 return 0; 770 771 out: 772 flexcan_chip_disable(priv); 773 return err; 774} 775 776/* 777 * flexcan_chip_stop 778 * 779 * this functions is entered with clocks enabled 780 * 781 */ 782static void flexcan_chip_stop(struct net_device *dev) 783{ 784 struct flexcan_priv *priv = netdev_priv(dev); 785 struct flexcan_regs __iomem *regs = priv->base; 786 u32 reg; 787 788 /* Disable all interrupts */ 789 flexcan_write(0, ®s->imask1); 790 791 /* Disable + halt module */ 792 reg = flexcan_read(®s->mcr); 793 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT; 794 flexcan_write(reg, ®s->mcr); 795 796 flexcan_transceiver_switch(priv, 0); 797 priv->can.state = CAN_STATE_STOPPED; 798 799 return; 800} 801 802static int flexcan_open(struct net_device *dev) 803{ 804 struct flexcan_priv *priv = netdev_priv(dev); 805 int err; 806 807 clk_prepare_enable(priv->clk); 808 809 err = open_candev(dev); 810 if (err) 811 goto out; 812 813 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 814 if (err) 815 goto out_close; 816 817 /* start chip and queuing */ 818 err = flexcan_chip_start(dev); 819 if (err) 820 goto out_close; 821 napi_enable(&priv->napi); 822 netif_start_queue(dev); 823 824 return 0; 825 826 out_close: 827 close_candev(dev); 828 out: 829 clk_disable_unprepare(priv->clk); 830 831 return err; 832} 833 834static int flexcan_close(struct net_device *dev) 835{ 836 struct flexcan_priv *priv = netdev_priv(dev); 837 838 netif_stop_queue(dev); 839 napi_disable(&priv->napi); 840 flexcan_chip_stop(dev); 841 842 free_irq(dev->irq, dev); 843 clk_disable_unprepare(priv->clk); 844 845 close_candev(dev); 846 847 return 0; 848} 849 850static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 851{ 852 int err; 853 854 switch (mode) { 855 case CAN_MODE_START: 856 err = flexcan_chip_start(dev); 857 if (err) 858 return err; 859 860 netif_wake_queue(dev); 861 break; 862 863 default: 864 return -EOPNOTSUPP; 865 } 866 867 return 0; 868} 869 870static const struct net_device_ops flexcan_netdev_ops = { 871 .ndo_open = flexcan_open, 872 .ndo_stop = flexcan_close, 873 .ndo_start_xmit = flexcan_start_xmit, 874}; 875 876static int __devinit register_flexcandev(struct net_device *dev) 877{ 878 struct flexcan_priv *priv = netdev_priv(dev); 879 struct flexcan_regs __iomem *regs = priv->base; 880 u32 reg, err; 881 882 clk_prepare_enable(priv->clk); 883 884 /* select "bus clock", chip must be disabled */ 885 flexcan_chip_disable(priv); 886 reg = flexcan_read(®s->ctrl); 887 reg |= FLEXCAN_CTRL_CLK_SRC; 888 flexcan_write(reg, ®s->ctrl); 889 890 flexcan_chip_enable(priv); 891 892 /* set freeze, halt and activate FIFO, restrict register access */ 893 reg = flexcan_read(®s->mcr); 894 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 895 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 896 flexcan_write(reg, ®s->mcr); 897 898 /* 899 * Currently we only support newer versions of this core 900 * featuring a RX FIFO. Older cores found on some Coldfire 901 * derivates are not yet supported. 902 */ 903 reg = flexcan_read(®s->mcr); 904 if (!(reg & FLEXCAN_MCR_FEN)) { 905 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); 906 err = -ENODEV; 907 goto out; 908 } 909 910 err = register_candev(dev); 911 912 out: 913 /* disable core and turn off clocks */ 914 flexcan_chip_disable(priv); 915 clk_disable_unprepare(priv->clk); 916 917 return err; 918} 919 920static void __devexit unregister_flexcandev(struct net_device *dev) 921{ 922 unregister_candev(dev); 923} 924 925static int __devinit flexcan_probe(struct platform_device *pdev) 926{ 927 struct net_device *dev; 928 struct flexcan_priv *priv; 929 struct resource *mem; 930 struct clk *clk = NULL; 931 struct pinctrl *pinctrl; 932 void __iomem *base; 933 resource_size_t mem_size; 934 int err, irq; 935 u32 clock_freq = 0; 936 937 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 938 if (IS_ERR(pinctrl)) 939 return PTR_ERR(pinctrl); 940 941 if (pdev->dev.of_node) { 942 const __be32 *clock_freq_p; 943 944 clock_freq_p = of_get_property(pdev->dev.of_node, 945 "clock-frequency", NULL); 946 if (clock_freq_p) 947 clock_freq = be32_to_cpup(clock_freq_p); 948 } 949 950 if (!clock_freq) { 951 clk = clk_get(&pdev->dev, NULL); 952 if (IS_ERR(clk)) { 953 dev_err(&pdev->dev, "no clock defined\n"); 954 err = PTR_ERR(clk); 955 goto failed_clock; 956 } 957 clock_freq = clk_get_rate(clk); 958 } 959 960 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 961 irq = platform_get_irq(pdev, 0); 962 if (!mem || irq <= 0) { 963 err = -ENODEV; 964 goto failed_get; 965 } 966 967 mem_size = resource_size(mem); 968 if (!request_mem_region(mem->start, mem_size, pdev->name)) { 969 err = -EBUSY; 970 goto failed_get; 971 } 972 973 base = ioremap(mem->start, mem_size); 974 if (!base) { 975 err = -ENOMEM; 976 goto failed_map; 977 } 978 979 dev = alloc_candev(sizeof(struct flexcan_priv), 1); 980 if (!dev) { 981 err = -ENOMEM; 982 goto failed_alloc; 983 } 984 985 dev->netdev_ops = &flexcan_netdev_ops; 986 dev->irq = irq; 987 dev->flags |= IFF_ECHO; 988 989 priv = netdev_priv(dev); 990 priv->can.clock.freq = clock_freq; 991 priv->can.bittiming_const = &flexcan_bittiming_const; 992 priv->can.do_set_mode = flexcan_set_mode; 993 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 994 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 995 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 996 CAN_CTRLMODE_BERR_REPORTING; 997 priv->base = base; 998 priv->dev = dev; 999 priv->clk = clk; 1000 priv->pdata = pdev->dev.platform_data; 1001 1002 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); 1003 1004 dev_set_drvdata(&pdev->dev, dev); 1005 SET_NETDEV_DEV(dev, &pdev->dev); 1006 1007 err = register_flexcandev(dev); 1008 if (err) { 1009 dev_err(&pdev->dev, "registering netdev failed\n"); 1010 goto failed_register; 1011 } 1012 1013 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1014 priv->base, dev->irq); 1015 1016 return 0; 1017 1018 failed_register: 1019 free_candev(dev); 1020 failed_alloc: 1021 iounmap(base); 1022 failed_map: 1023 release_mem_region(mem->start, mem_size); 1024 failed_get: 1025 if (clk) 1026 clk_put(clk); 1027 failed_clock: 1028 return err; 1029} 1030 1031static int __devexit flexcan_remove(struct platform_device *pdev) 1032{ 1033 struct net_device *dev = platform_get_drvdata(pdev); 1034 struct flexcan_priv *priv = netdev_priv(dev); 1035 struct resource *mem; 1036 1037 unregister_flexcandev(dev); 1038 platform_set_drvdata(pdev, NULL); 1039 iounmap(priv->base); 1040 1041 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1042 release_mem_region(mem->start, resource_size(mem)); 1043 1044 if (priv->clk) 1045 clk_put(priv->clk); 1046 1047 free_candev(dev); 1048 1049 return 0; 1050} 1051 1052static struct of_device_id flexcan_of_match[] = { 1053 { 1054 .compatible = "fsl,p1010-flexcan", 1055 }, 1056 {}, 1057}; 1058 1059static struct platform_driver flexcan_driver = { 1060 .driver = { 1061 .name = DRV_NAME, 1062 .owner = THIS_MODULE, 1063 .of_match_table = flexcan_of_match, 1064 }, 1065 .probe = flexcan_probe, 1066 .remove = __devexit_p(flexcan_remove), 1067}; 1068 1069module_platform_driver(flexcan_driver); 1070 1071MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 1072 "Marc Kleine-Budde <kernel@pengutronix.de>"); 1073MODULE_LICENSE("GPL v2"); 1074MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 1075