flexcan.c revision 97efe9aef1ae8922666d32f28d712745a86859e9
1/* 2 * flexcan.c - FLEXCAN CAN controller driver 3 * 4 * Copyright (c) 2005-2006 Varma Electronics Oy 5 * Copyright (c) 2009 Sascha Hauer, Pengutronix 6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix 7 * 8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com> 9 * 10 * LICENCE: 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22#include <linux/netdevice.h> 23#include <linux/can.h> 24#include <linux/can/dev.h> 25#include <linux/can/error.h> 26#include <linux/can/platform/flexcan.h> 27#include <linux/clk.h> 28#include <linux/delay.h> 29#include <linux/if_arp.h> 30#include <linux/if_ether.h> 31#include <linux/interrupt.h> 32#include <linux/io.h> 33#include <linux/kernel.h> 34#include <linux/list.h> 35#include <linux/module.h> 36#include <linux/of.h> 37#include <linux/platform_device.h> 38 39#define DRV_NAME "flexcan" 40 41/* 8 for RX fifo and 2 error handling */ 42#define FLEXCAN_NAPI_WEIGHT (8 + 2) 43 44/* FLEXCAN module configuration register (CANMCR) bits */ 45#define FLEXCAN_MCR_MDIS BIT(31) 46#define FLEXCAN_MCR_FRZ BIT(30) 47#define FLEXCAN_MCR_FEN BIT(29) 48#define FLEXCAN_MCR_HALT BIT(28) 49#define FLEXCAN_MCR_NOT_RDY BIT(27) 50#define FLEXCAN_MCR_WAK_MSK BIT(26) 51#define FLEXCAN_MCR_SOFTRST BIT(25) 52#define FLEXCAN_MCR_FRZ_ACK BIT(24) 53#define FLEXCAN_MCR_SUPV BIT(23) 54#define FLEXCAN_MCR_SLF_WAK BIT(22) 55#define FLEXCAN_MCR_WRN_EN BIT(21) 56#define FLEXCAN_MCR_LPM_ACK BIT(20) 57#define FLEXCAN_MCR_WAK_SRC BIT(19) 58#define FLEXCAN_MCR_DOZE BIT(18) 59#define FLEXCAN_MCR_SRX_DIS BIT(17) 60#define FLEXCAN_MCR_BCC BIT(16) 61#define FLEXCAN_MCR_LPRIO_EN BIT(13) 62#define FLEXCAN_MCR_AEN BIT(12) 63#define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf) 64#define FLEXCAN_MCR_IDAM_A (0 << 8) 65#define FLEXCAN_MCR_IDAM_B (1 << 8) 66#define FLEXCAN_MCR_IDAM_C (2 << 8) 67#define FLEXCAN_MCR_IDAM_D (3 << 8) 68 69/* FLEXCAN control register (CANCTRL) bits */ 70#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 71#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 72#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 73#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 74#define FLEXCAN_CTRL_BOFF_MSK BIT(15) 75#define FLEXCAN_CTRL_ERR_MSK BIT(14) 76#define FLEXCAN_CTRL_CLK_SRC BIT(13) 77#define FLEXCAN_CTRL_LPB BIT(12) 78#define FLEXCAN_CTRL_TWRN_MSK BIT(11) 79#define FLEXCAN_CTRL_RWRN_MSK BIT(10) 80#define FLEXCAN_CTRL_SMP BIT(7) 81#define FLEXCAN_CTRL_BOFF_REC BIT(6) 82#define FLEXCAN_CTRL_TSYN BIT(5) 83#define FLEXCAN_CTRL_LBUF BIT(4) 84#define FLEXCAN_CTRL_LOM BIT(3) 85#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 86#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 87#define FLEXCAN_CTRL_ERR_STATE \ 88 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 89 FLEXCAN_CTRL_BOFF_MSK) 90#define FLEXCAN_CTRL_ERR_ALL \ 91 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 92 93/* FLEXCAN error and status register (ESR) bits */ 94#define FLEXCAN_ESR_TWRN_INT BIT(17) 95#define FLEXCAN_ESR_RWRN_INT BIT(16) 96#define FLEXCAN_ESR_BIT1_ERR BIT(15) 97#define FLEXCAN_ESR_BIT0_ERR BIT(14) 98#define FLEXCAN_ESR_ACK_ERR BIT(13) 99#define FLEXCAN_ESR_CRC_ERR BIT(12) 100#define FLEXCAN_ESR_FRM_ERR BIT(11) 101#define FLEXCAN_ESR_STF_ERR BIT(10) 102#define FLEXCAN_ESR_TX_WRN BIT(9) 103#define FLEXCAN_ESR_RX_WRN BIT(8) 104#define FLEXCAN_ESR_IDLE BIT(7) 105#define FLEXCAN_ESR_TXRX BIT(6) 106#define FLEXCAN_EST_FLT_CONF_SHIFT (4) 107#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 108#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 109#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 110#define FLEXCAN_ESR_BOFF_INT BIT(2) 111#define FLEXCAN_ESR_ERR_INT BIT(1) 112#define FLEXCAN_ESR_WAK_INT BIT(0) 113#define FLEXCAN_ESR_ERR_BUS \ 114 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 115 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 116 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 117#define FLEXCAN_ESR_ERR_STATE \ 118 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 119#define FLEXCAN_ESR_ERR_ALL \ 120 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 121 122/* FLEXCAN interrupt flag register (IFLAG) bits */ 123#define FLEXCAN_TX_BUF_ID 8 124#define FLEXCAN_IFLAG_BUF(x) BIT(x) 125#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 126#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 127#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 128#define FLEXCAN_IFLAG_DEFAULT \ 129 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ 130 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) 131 132/* FLEXCAN message buffers */ 133#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) 134#define FLEXCAN_MB_CNT_SRR BIT(22) 135#define FLEXCAN_MB_CNT_IDE BIT(21) 136#define FLEXCAN_MB_CNT_RTR BIT(20) 137#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 138#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 139 140#define FLEXCAN_MB_CODE_MASK (0xf0ffffff) 141 142/* Structure of the message buffer */ 143struct flexcan_mb { 144 u32 can_ctrl; 145 u32 can_id; 146 u32 data[2]; 147}; 148 149/* Structure of the hardware registers */ 150struct flexcan_regs { 151 u32 mcr; /* 0x00 */ 152 u32 ctrl; /* 0x04 */ 153 u32 timer; /* 0x08 */ 154 u32 _reserved1; /* 0x0c */ 155 u32 rxgmask; /* 0x10 */ 156 u32 rx14mask; /* 0x14 */ 157 u32 rx15mask; /* 0x18 */ 158 u32 ecr; /* 0x1c */ 159 u32 esr; /* 0x20 */ 160 u32 imask2; /* 0x24 */ 161 u32 imask1; /* 0x28 */ 162 u32 iflag2; /* 0x2c */ 163 u32 iflag1; /* 0x30 */ 164 u32 _reserved2[19]; 165 struct flexcan_mb cantxfg[64]; 166}; 167 168struct flexcan_priv { 169 struct can_priv can; 170 struct net_device *dev; 171 struct napi_struct napi; 172 173 void __iomem *base; 174 u32 reg_esr; 175 u32 reg_ctrl_default; 176 177 struct clk *clk; 178 struct flexcan_platform_data *pdata; 179}; 180 181static struct can_bittiming_const flexcan_bittiming_const = { 182 .name = DRV_NAME, 183 .tseg1_min = 4, 184 .tseg1_max = 16, 185 .tseg2_min = 2, 186 .tseg2_max = 8, 187 .sjw_max = 4, 188 .brp_min = 1, 189 .brp_max = 256, 190 .brp_inc = 1, 191}; 192 193/* 194 * Abstract off the read/write for arm versus ppc. 195 */ 196#if defined(__BIG_ENDIAN) 197static inline u32 flexcan_read(void __iomem *addr) 198{ 199 return in_be32(addr); 200} 201 202static inline void flexcan_write(u32 val, void __iomem *addr) 203{ 204 out_be32(addr, val); 205} 206#else 207static inline u32 flexcan_read(void __iomem *addr) 208{ 209 return readl(addr); 210} 211 212static inline void flexcan_write(u32 val, void __iomem *addr) 213{ 214 writel(val, addr); 215} 216#endif 217 218/* 219 * Swtich transceiver on or off 220 */ 221static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on) 222{ 223 if (priv->pdata && priv->pdata->transceiver_switch) 224 priv->pdata->transceiver_switch(on); 225} 226 227static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, 228 u32 reg_esr) 229{ 230 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 231 (reg_esr & FLEXCAN_ESR_ERR_BUS); 232} 233 234static inline void flexcan_chip_enable(struct flexcan_priv *priv) 235{ 236 struct flexcan_regs __iomem *regs = priv->base; 237 u32 reg; 238 239 reg = flexcan_read(®s->mcr); 240 reg &= ~FLEXCAN_MCR_MDIS; 241 flexcan_write(reg, ®s->mcr); 242 243 udelay(10); 244} 245 246static inline void flexcan_chip_disable(struct flexcan_priv *priv) 247{ 248 struct flexcan_regs __iomem *regs = priv->base; 249 u32 reg; 250 251 reg = flexcan_read(®s->mcr); 252 reg |= FLEXCAN_MCR_MDIS; 253 flexcan_write(reg, ®s->mcr); 254} 255 256static int flexcan_get_berr_counter(const struct net_device *dev, 257 struct can_berr_counter *bec) 258{ 259 const struct flexcan_priv *priv = netdev_priv(dev); 260 struct flexcan_regs __iomem *regs = priv->base; 261 u32 reg = flexcan_read(®s->ecr); 262 263 bec->txerr = (reg >> 0) & 0xff; 264 bec->rxerr = (reg >> 8) & 0xff; 265 266 return 0; 267} 268 269static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 270{ 271 const struct flexcan_priv *priv = netdev_priv(dev); 272 struct net_device_stats *stats = &dev->stats; 273 struct flexcan_regs __iomem *regs = priv->base; 274 struct can_frame *cf = (struct can_frame *)skb->data; 275 u32 can_id; 276 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); 277 278 if (can_dropped_invalid_skb(dev, skb)) 279 return NETDEV_TX_OK; 280 281 netif_stop_queue(dev); 282 283 if (cf->can_id & CAN_EFF_FLAG) { 284 can_id = cf->can_id & CAN_EFF_MASK; 285 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 286 } else { 287 can_id = (cf->can_id & CAN_SFF_MASK) << 18; 288 } 289 290 if (cf->can_id & CAN_RTR_FLAG) 291 ctrl |= FLEXCAN_MB_CNT_RTR; 292 293 if (cf->can_dlc > 0) { 294 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 295 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 296 } 297 if (cf->can_dlc > 3) { 298 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 299 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 300 } 301 302 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 303 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 304 305 kfree_skb(skb); 306 307 /* tx_packets is incremented in flexcan_irq */ 308 stats->tx_bytes += cf->can_dlc; 309 310 return NETDEV_TX_OK; 311} 312 313static void do_bus_err(struct net_device *dev, 314 struct can_frame *cf, u32 reg_esr) 315{ 316 struct flexcan_priv *priv = netdev_priv(dev); 317 int rx_errors = 0, tx_errors = 0; 318 319 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 320 321 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 322 dev_dbg(dev->dev.parent, "BIT1_ERR irq\n"); 323 cf->data[2] |= CAN_ERR_PROT_BIT1; 324 tx_errors = 1; 325 } 326 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 327 dev_dbg(dev->dev.parent, "BIT0_ERR irq\n"); 328 cf->data[2] |= CAN_ERR_PROT_BIT0; 329 tx_errors = 1; 330 } 331 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 332 dev_dbg(dev->dev.parent, "ACK_ERR irq\n"); 333 cf->can_id |= CAN_ERR_ACK; 334 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 335 tx_errors = 1; 336 } 337 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 338 dev_dbg(dev->dev.parent, "CRC_ERR irq\n"); 339 cf->data[2] |= CAN_ERR_PROT_BIT; 340 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 341 rx_errors = 1; 342 } 343 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 344 dev_dbg(dev->dev.parent, "FRM_ERR irq\n"); 345 cf->data[2] |= CAN_ERR_PROT_FORM; 346 rx_errors = 1; 347 } 348 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 349 dev_dbg(dev->dev.parent, "STF_ERR irq\n"); 350 cf->data[2] |= CAN_ERR_PROT_STUFF; 351 rx_errors = 1; 352 } 353 354 priv->can.can_stats.bus_error++; 355 if (rx_errors) 356 dev->stats.rx_errors++; 357 if (tx_errors) 358 dev->stats.tx_errors++; 359} 360 361static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) 362{ 363 struct sk_buff *skb; 364 struct can_frame *cf; 365 366 skb = alloc_can_err_skb(dev, &cf); 367 if (unlikely(!skb)) 368 return 0; 369 370 do_bus_err(dev, cf, reg_esr); 371 netif_receive_skb(skb); 372 373 dev->stats.rx_packets++; 374 dev->stats.rx_bytes += cf->can_dlc; 375 376 return 1; 377} 378 379static void do_state(struct net_device *dev, 380 struct can_frame *cf, enum can_state new_state) 381{ 382 struct flexcan_priv *priv = netdev_priv(dev); 383 struct can_berr_counter bec; 384 385 flexcan_get_berr_counter(dev, &bec); 386 387 switch (priv->can.state) { 388 case CAN_STATE_ERROR_ACTIVE: 389 /* 390 * from: ERROR_ACTIVE 391 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 392 * => : there was a warning int 393 */ 394 if (new_state >= CAN_STATE_ERROR_WARNING && 395 new_state <= CAN_STATE_BUS_OFF) { 396 dev_dbg(dev->dev.parent, "Error Warning IRQ\n"); 397 priv->can.can_stats.error_warning++; 398 399 cf->can_id |= CAN_ERR_CRTL; 400 cf->data[1] = (bec.txerr > bec.rxerr) ? 401 CAN_ERR_CRTL_TX_WARNING : 402 CAN_ERR_CRTL_RX_WARNING; 403 } 404 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 405 /* 406 * from: ERROR_ACTIVE, ERROR_WARNING 407 * to : ERROR_PASSIVE, BUS_OFF 408 * => : error passive int 409 */ 410 if (new_state >= CAN_STATE_ERROR_PASSIVE && 411 new_state <= CAN_STATE_BUS_OFF) { 412 dev_dbg(dev->dev.parent, "Error Passive IRQ\n"); 413 priv->can.can_stats.error_passive++; 414 415 cf->can_id |= CAN_ERR_CRTL; 416 cf->data[1] = (bec.txerr > bec.rxerr) ? 417 CAN_ERR_CRTL_TX_PASSIVE : 418 CAN_ERR_CRTL_RX_PASSIVE; 419 } 420 break; 421 case CAN_STATE_BUS_OFF: 422 dev_err(dev->dev.parent, 423 "BUG! hardware recovered automatically from BUS_OFF\n"); 424 break; 425 default: 426 break; 427 } 428 429 /* process state changes depending on the new state */ 430 switch (new_state) { 431 case CAN_STATE_ERROR_ACTIVE: 432 dev_dbg(dev->dev.parent, "Error Active\n"); 433 cf->can_id |= CAN_ERR_PROT; 434 cf->data[2] = CAN_ERR_PROT_ACTIVE; 435 break; 436 case CAN_STATE_BUS_OFF: 437 cf->can_id |= CAN_ERR_BUSOFF; 438 can_bus_off(dev); 439 break; 440 default: 441 break; 442 } 443} 444 445static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) 446{ 447 struct flexcan_priv *priv = netdev_priv(dev); 448 struct sk_buff *skb; 449 struct can_frame *cf; 450 enum can_state new_state; 451 int flt; 452 453 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 454 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 455 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | 456 FLEXCAN_ESR_RX_WRN)))) 457 new_state = CAN_STATE_ERROR_ACTIVE; 458 else 459 new_state = CAN_STATE_ERROR_WARNING; 460 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) 461 new_state = CAN_STATE_ERROR_PASSIVE; 462 else 463 new_state = CAN_STATE_BUS_OFF; 464 465 /* state hasn't changed */ 466 if (likely(new_state == priv->can.state)) 467 return 0; 468 469 skb = alloc_can_err_skb(dev, &cf); 470 if (unlikely(!skb)) 471 return 0; 472 473 do_state(dev, cf, new_state); 474 priv->can.state = new_state; 475 netif_receive_skb(skb); 476 477 dev->stats.rx_packets++; 478 dev->stats.rx_bytes += cf->can_dlc; 479 480 return 1; 481} 482 483static void flexcan_read_fifo(const struct net_device *dev, 484 struct can_frame *cf) 485{ 486 const struct flexcan_priv *priv = netdev_priv(dev); 487 struct flexcan_regs __iomem *regs = priv->base; 488 struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; 489 u32 reg_ctrl, reg_id; 490 491 reg_ctrl = flexcan_read(&mb->can_ctrl); 492 reg_id = flexcan_read(&mb->can_id); 493 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 494 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 495 else 496 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; 497 498 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 499 cf->can_id |= CAN_RTR_FLAG; 500 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 501 502 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); 503 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); 504 505 /* mark as read */ 506 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 507 flexcan_read(®s->timer); 508} 509 510static int flexcan_read_frame(struct net_device *dev) 511{ 512 struct net_device_stats *stats = &dev->stats; 513 struct can_frame *cf; 514 struct sk_buff *skb; 515 516 skb = alloc_can_skb(dev, &cf); 517 if (unlikely(!skb)) { 518 stats->rx_dropped++; 519 return 0; 520 } 521 522 flexcan_read_fifo(dev, cf); 523 netif_receive_skb(skb); 524 525 stats->rx_packets++; 526 stats->rx_bytes += cf->can_dlc; 527 528 return 1; 529} 530 531static int flexcan_poll(struct napi_struct *napi, int quota) 532{ 533 struct net_device *dev = napi->dev; 534 const struct flexcan_priv *priv = netdev_priv(dev); 535 struct flexcan_regs __iomem *regs = priv->base; 536 u32 reg_iflag1, reg_esr; 537 int work_done = 0; 538 539 /* 540 * The error bits are cleared on read, 541 * use saved value from irq handler. 542 */ 543 reg_esr = flexcan_read(®s->esr) | priv->reg_esr; 544 545 /* handle state changes */ 546 work_done += flexcan_poll_state(dev, reg_esr); 547 548 /* handle RX-FIFO */ 549 reg_iflag1 = flexcan_read(®s->iflag1); 550 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 551 work_done < quota) { 552 work_done += flexcan_read_frame(dev); 553 reg_iflag1 = flexcan_read(®s->iflag1); 554 } 555 556 /* report bus errors */ 557 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) 558 work_done += flexcan_poll_bus_err(dev, reg_esr); 559 560 if (work_done < quota) { 561 napi_complete(napi); 562 /* enable IRQs */ 563 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 564 flexcan_write(priv->reg_ctrl_default, ®s->ctrl); 565 } 566 567 return work_done; 568} 569 570static irqreturn_t flexcan_irq(int irq, void *dev_id) 571{ 572 struct net_device *dev = dev_id; 573 struct net_device_stats *stats = &dev->stats; 574 struct flexcan_priv *priv = netdev_priv(dev); 575 struct flexcan_regs __iomem *regs = priv->base; 576 u32 reg_iflag1, reg_esr; 577 578 reg_iflag1 = flexcan_read(®s->iflag1); 579 reg_esr = flexcan_read(®s->esr); 580 flexcan_write(FLEXCAN_ESR_ERR_INT, ®s->esr); /* ACK err IRQ */ 581 582 /* 583 * schedule NAPI in case of: 584 * - rx IRQ 585 * - state change IRQ 586 * - bus error IRQ and bus error reporting is activated 587 */ 588 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || 589 (reg_esr & FLEXCAN_ESR_ERR_STATE) || 590 flexcan_has_and_handle_berr(priv, reg_esr)) { 591 /* 592 * The error bits are cleared on read, 593 * save them for later use. 594 */ 595 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 596 flexcan_write(FLEXCAN_IFLAG_DEFAULT & 597 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); 598 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 599 ®s->ctrl); 600 napi_schedule(&priv->napi); 601 } 602 603 /* FIFO overflow */ 604 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 605 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); 606 dev->stats.rx_over_errors++; 607 dev->stats.rx_errors++; 608 } 609 610 /* transmission complete interrupt */ 611 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 612 /* tx_bytes is incremented in flexcan_start_xmit */ 613 stats->tx_packets++; 614 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); 615 netif_wake_queue(dev); 616 } 617 618 return IRQ_HANDLED; 619} 620 621static void flexcan_set_bittiming(struct net_device *dev) 622{ 623 const struct flexcan_priv *priv = netdev_priv(dev); 624 const struct can_bittiming *bt = &priv->can.bittiming; 625 struct flexcan_regs __iomem *regs = priv->base; 626 u32 reg; 627 628 reg = flexcan_read(®s->ctrl); 629 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 630 FLEXCAN_CTRL_RJW(0x3) | 631 FLEXCAN_CTRL_PSEG1(0x7) | 632 FLEXCAN_CTRL_PSEG2(0x7) | 633 FLEXCAN_CTRL_PROPSEG(0x7) | 634 FLEXCAN_CTRL_LPB | 635 FLEXCAN_CTRL_SMP | 636 FLEXCAN_CTRL_LOM); 637 638 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 639 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 640 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 641 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 642 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 643 644 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 645 reg |= FLEXCAN_CTRL_LPB; 646 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 647 reg |= FLEXCAN_CTRL_LOM; 648 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 649 reg |= FLEXCAN_CTRL_SMP; 650 651 dev_info(dev->dev.parent, "writing ctrl=0x%08x\n", reg); 652 flexcan_write(reg, ®s->ctrl); 653 654 /* print chip status */ 655 dev_dbg(dev->dev.parent, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 656 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 657} 658 659/* 660 * flexcan_chip_start 661 * 662 * this functions is entered with clocks enabled 663 * 664 */ 665static int flexcan_chip_start(struct net_device *dev) 666{ 667 struct flexcan_priv *priv = netdev_priv(dev); 668 struct flexcan_regs __iomem *regs = priv->base; 669 unsigned int i; 670 int err; 671 u32 reg_mcr, reg_ctrl; 672 673 /* enable module */ 674 flexcan_chip_enable(priv); 675 676 /* soft reset */ 677 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 678 udelay(10); 679 680 reg_mcr = flexcan_read(®s->mcr); 681 if (reg_mcr & FLEXCAN_MCR_SOFTRST) { 682 dev_err(dev->dev.parent, 683 "Failed to softreset can module (mcr=0x%08x)\n", 684 reg_mcr); 685 err = -ENODEV; 686 goto out; 687 } 688 689 flexcan_set_bittiming(dev); 690 691 /* 692 * MCR 693 * 694 * enable freeze 695 * enable fifo 696 * halt now 697 * only supervisor access 698 * enable warning int 699 * choose format C 700 * 701 */ 702 reg_mcr = flexcan_read(®s->mcr); 703 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 704 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 705 FLEXCAN_MCR_IDAM_C; 706 dev_dbg(dev->dev.parent, "%s: writing mcr=0x%08x", __func__, reg_mcr); 707 flexcan_write(reg_mcr, ®s->mcr); 708 709 /* 710 * CTRL 711 * 712 * disable timer sync feature 713 * 714 * disable auto busoff recovery 715 * transmit lowest buffer first 716 * 717 * enable tx and rx warning interrupt 718 * enable bus off interrupt 719 * (== FLEXCAN_CTRL_ERR_STATE) 720 * 721 * _note_: we enable the "error interrupt" 722 * (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any 723 * warning or bus passive interrupts. 724 */ 725 reg_ctrl = flexcan_read(®s->ctrl); 726 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 727 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 728 FLEXCAN_CTRL_ERR_STATE | FLEXCAN_CTRL_ERR_MSK; 729 730 /* save for later use */ 731 priv->reg_ctrl_default = reg_ctrl; 732 dev_dbg(dev->dev.parent, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 733 flexcan_write(reg_ctrl, ®s->ctrl); 734 735 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) { 736 flexcan_write(0, ®s->cantxfg[i].can_ctrl); 737 flexcan_write(0, ®s->cantxfg[i].can_id); 738 flexcan_write(0, ®s->cantxfg[i].data[0]); 739 flexcan_write(0, ®s->cantxfg[i].data[1]); 740 741 /* put MB into rx queue */ 742 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4), 743 ®s->cantxfg[i].can_ctrl); 744 } 745 746 /* acceptance mask/acceptance code (accept everything) */ 747 flexcan_write(0x0, ®s->rxgmask); 748 flexcan_write(0x0, ®s->rx14mask); 749 flexcan_write(0x0, ®s->rx15mask); 750 751 flexcan_transceiver_switch(priv, 1); 752 753 /* synchronize with the can bus */ 754 reg_mcr = flexcan_read(®s->mcr); 755 reg_mcr &= ~FLEXCAN_MCR_HALT; 756 flexcan_write(reg_mcr, ®s->mcr); 757 758 priv->can.state = CAN_STATE_ERROR_ACTIVE; 759 760 /* enable FIFO interrupts */ 761 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 762 763 /* print chip status */ 764 dev_dbg(dev->dev.parent, "%s: reading mcr=0x%08x ctrl=0x%08x\n", 765 __func__, flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 766 767 return 0; 768 769 out: 770 flexcan_chip_disable(priv); 771 return err; 772} 773 774/* 775 * flexcan_chip_stop 776 * 777 * this functions is entered with clocks enabled 778 * 779 */ 780static void flexcan_chip_stop(struct net_device *dev) 781{ 782 struct flexcan_priv *priv = netdev_priv(dev); 783 struct flexcan_regs __iomem *regs = priv->base; 784 u32 reg; 785 786 /* Disable all interrupts */ 787 flexcan_write(0, ®s->imask1); 788 789 /* Disable + halt module */ 790 reg = flexcan_read(®s->mcr); 791 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT; 792 flexcan_write(reg, ®s->mcr); 793 794 flexcan_transceiver_switch(priv, 0); 795 priv->can.state = CAN_STATE_STOPPED; 796 797 return; 798} 799 800static int flexcan_open(struct net_device *dev) 801{ 802 struct flexcan_priv *priv = netdev_priv(dev); 803 int err; 804 805 clk_enable(priv->clk); 806 807 err = open_candev(dev); 808 if (err) 809 goto out; 810 811 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 812 if (err) 813 goto out_close; 814 815 /* start chip and queuing */ 816 err = flexcan_chip_start(dev); 817 if (err) 818 goto out_close; 819 napi_enable(&priv->napi); 820 netif_start_queue(dev); 821 822 return 0; 823 824 out_close: 825 close_candev(dev); 826 out: 827 clk_disable(priv->clk); 828 829 return err; 830} 831 832static int flexcan_close(struct net_device *dev) 833{ 834 struct flexcan_priv *priv = netdev_priv(dev); 835 836 netif_stop_queue(dev); 837 napi_disable(&priv->napi); 838 flexcan_chip_stop(dev); 839 840 free_irq(dev->irq, dev); 841 clk_disable(priv->clk); 842 843 close_candev(dev); 844 845 return 0; 846} 847 848static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 849{ 850 int err; 851 852 switch (mode) { 853 case CAN_MODE_START: 854 err = flexcan_chip_start(dev); 855 if (err) 856 return err; 857 858 netif_wake_queue(dev); 859 break; 860 861 default: 862 return -EOPNOTSUPP; 863 } 864 865 return 0; 866} 867 868static const struct net_device_ops flexcan_netdev_ops = { 869 .ndo_open = flexcan_open, 870 .ndo_stop = flexcan_close, 871 .ndo_start_xmit = flexcan_start_xmit, 872}; 873 874static int __devinit register_flexcandev(struct net_device *dev) 875{ 876 struct flexcan_priv *priv = netdev_priv(dev); 877 struct flexcan_regs __iomem *regs = priv->base; 878 u32 reg, err; 879 880 clk_enable(priv->clk); 881 882 /* select "bus clock", chip must be disabled */ 883 flexcan_chip_disable(priv); 884 reg = flexcan_read(®s->ctrl); 885 reg |= FLEXCAN_CTRL_CLK_SRC; 886 flexcan_write(reg, ®s->ctrl); 887 888 flexcan_chip_enable(priv); 889 890 /* set freeze, halt and activate FIFO, restrict register access */ 891 reg = flexcan_read(®s->mcr); 892 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 893 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 894 flexcan_write(reg, ®s->mcr); 895 896 /* 897 * Currently we only support newer versions of this core 898 * featuring a RX FIFO. Older cores found on some Coldfire 899 * derivates are not yet supported. 900 */ 901 reg = flexcan_read(®s->mcr); 902 if (!(reg & FLEXCAN_MCR_FEN)) { 903 dev_err(dev->dev.parent, 904 "Could not enable RX FIFO, unsupported core\n"); 905 err = -ENODEV; 906 goto out; 907 } 908 909 err = register_candev(dev); 910 911 out: 912 /* disable core and turn off clocks */ 913 flexcan_chip_disable(priv); 914 clk_disable(priv->clk); 915 916 return err; 917} 918 919static void __devexit unregister_flexcandev(struct net_device *dev) 920{ 921 unregister_candev(dev); 922} 923 924static int __devinit flexcan_probe(struct platform_device *pdev) 925{ 926 struct net_device *dev; 927 struct flexcan_priv *priv; 928 struct resource *mem; 929 struct clk *clk = NULL; 930 void __iomem *base; 931 resource_size_t mem_size; 932 int err, irq; 933 u32 clock_freq = 0; 934 935 if (pdev->dev.of_node) { 936 const u32 *clock_freq_p; 937 938 clock_freq_p = of_get_property(pdev->dev.of_node, 939 "clock-frequency", NULL); 940 if (clock_freq_p) 941 clock_freq = *clock_freq_p; 942 } 943 944 if (!clock_freq) { 945 clk = clk_get(&pdev->dev, NULL); 946 if (IS_ERR(clk)) { 947 dev_err(&pdev->dev, "no clock defined\n"); 948 err = PTR_ERR(clk); 949 goto failed_clock; 950 } 951 clock_freq = clk_get_rate(clk); 952 } 953 954 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 955 irq = platform_get_irq(pdev, 0); 956 if (!mem || irq <= 0) { 957 err = -ENODEV; 958 goto failed_get; 959 } 960 961 mem_size = resource_size(mem); 962 if (!request_mem_region(mem->start, mem_size, pdev->name)) { 963 err = -EBUSY; 964 goto failed_get; 965 } 966 967 base = ioremap(mem->start, mem_size); 968 if (!base) { 969 err = -ENOMEM; 970 goto failed_map; 971 } 972 973 dev = alloc_candev(sizeof(struct flexcan_priv), 0); 974 if (!dev) { 975 err = -ENOMEM; 976 goto failed_alloc; 977 } 978 979 dev->netdev_ops = &flexcan_netdev_ops; 980 dev->irq = irq; 981 dev->flags |= IFF_ECHO; /* we support local echo in hardware */ 982 983 priv = netdev_priv(dev); 984 priv->can.clock.freq = clock_freq; 985 priv->can.bittiming_const = &flexcan_bittiming_const; 986 priv->can.do_set_mode = flexcan_set_mode; 987 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 988 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 989 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 990 CAN_CTRLMODE_BERR_REPORTING; 991 priv->base = base; 992 priv->dev = dev; 993 priv->clk = clk; 994 priv->pdata = pdev->dev.platform_data; 995 996 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); 997 998 dev_set_drvdata(&pdev->dev, dev); 999 SET_NETDEV_DEV(dev, &pdev->dev); 1000 1001 err = register_flexcandev(dev); 1002 if (err) { 1003 dev_err(&pdev->dev, "registering netdev failed\n"); 1004 goto failed_register; 1005 } 1006 1007 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1008 priv->base, dev->irq); 1009 1010 return 0; 1011 1012 failed_register: 1013 free_candev(dev); 1014 failed_alloc: 1015 iounmap(base); 1016 failed_map: 1017 release_mem_region(mem->start, mem_size); 1018 failed_get: 1019 if (clk) 1020 clk_put(clk); 1021 failed_clock: 1022 return err; 1023} 1024 1025static int __devexit flexcan_remove(struct platform_device *pdev) 1026{ 1027 struct net_device *dev = platform_get_drvdata(pdev); 1028 struct flexcan_priv *priv = netdev_priv(dev); 1029 struct resource *mem; 1030 1031 unregister_flexcandev(dev); 1032 platform_set_drvdata(pdev, NULL); 1033 iounmap(priv->base); 1034 1035 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1036 release_mem_region(mem->start, resource_size(mem)); 1037 1038 if (priv->clk) 1039 clk_put(priv->clk); 1040 1041 free_candev(dev); 1042 1043 return 0; 1044} 1045 1046static struct of_device_id flexcan_of_match[] = { 1047 { 1048 .compatible = "fsl,p1010-flexcan", 1049 }, 1050 {}, 1051}; 1052 1053static struct platform_driver flexcan_driver = { 1054 .driver = { 1055 .name = DRV_NAME, 1056 .owner = THIS_MODULE, 1057 .of_match_table = flexcan_of_match, 1058 }, 1059 .probe = flexcan_probe, 1060 .remove = __devexit_p(flexcan_remove), 1061}; 1062 1063static int __init flexcan_init(void) 1064{ 1065 pr_info("%s netdevice driver\n", DRV_NAME); 1066 return platform_driver_register(&flexcan_driver); 1067} 1068 1069static void __exit flexcan_exit(void) 1070{ 1071 platform_driver_unregister(&flexcan_driver); 1072 pr_info("%s: driver removed\n", DRV_NAME); 1073} 1074 1075module_init(flexcan_init); 1076module_exit(flexcan_exit); 1077 1078MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 1079 "Marc Kleine-Budde <kernel@pengutronix.de>"); 1080MODULE_LICENSE("GPL v2"); 1081MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 1082