flexcan.c revision b7c4114b07bbacfe0aee1d04ad1ade9e42309620
1/* 2 * flexcan.c - FLEXCAN CAN controller driver 3 * 4 * Copyright (c) 2005-2006 Varma Electronics Oy 5 * Copyright (c) 2009 Sascha Hauer, Pengutronix 6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix 7 * 8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com> 9 * 10 * LICENCE: 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22#include <linux/netdevice.h> 23#include <linux/can.h> 24#include <linux/can/dev.h> 25#include <linux/can/error.h> 26#include <linux/can/led.h> 27#include <linux/clk.h> 28#include <linux/delay.h> 29#include <linux/if_arp.h> 30#include <linux/if_ether.h> 31#include <linux/interrupt.h> 32#include <linux/io.h> 33#include <linux/kernel.h> 34#include <linux/list.h> 35#include <linux/module.h> 36#include <linux/of.h> 37#include <linux/of_device.h> 38#include <linux/platform_device.h> 39#include <linux/regulator/consumer.h> 40 41#define DRV_NAME "flexcan" 42 43/* 8 for RX fifo and 2 error handling */ 44#define FLEXCAN_NAPI_WEIGHT (8 + 2) 45 46/* FLEXCAN module configuration register (CANMCR) bits */ 47#define FLEXCAN_MCR_MDIS BIT(31) 48#define FLEXCAN_MCR_FRZ BIT(30) 49#define FLEXCAN_MCR_FEN BIT(29) 50#define FLEXCAN_MCR_HALT BIT(28) 51#define FLEXCAN_MCR_NOT_RDY BIT(27) 52#define FLEXCAN_MCR_WAK_MSK BIT(26) 53#define FLEXCAN_MCR_SOFTRST BIT(25) 54#define FLEXCAN_MCR_FRZ_ACK BIT(24) 55#define FLEXCAN_MCR_SUPV BIT(23) 56#define FLEXCAN_MCR_SLF_WAK BIT(22) 57#define FLEXCAN_MCR_WRN_EN BIT(21) 58#define FLEXCAN_MCR_LPM_ACK BIT(20) 59#define FLEXCAN_MCR_WAK_SRC BIT(19) 60#define FLEXCAN_MCR_DOZE BIT(18) 61#define FLEXCAN_MCR_SRX_DIS BIT(17) 62#define FLEXCAN_MCR_BCC BIT(16) 63#define FLEXCAN_MCR_LPRIO_EN BIT(13) 64#define FLEXCAN_MCR_AEN BIT(12) 65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf) 66#define FLEXCAN_MCR_IDAM_A (0 << 8) 67#define FLEXCAN_MCR_IDAM_B (1 << 8) 68#define FLEXCAN_MCR_IDAM_C (2 << 8) 69#define FLEXCAN_MCR_IDAM_D (3 << 8) 70 71/* FLEXCAN control register (CANCTRL) bits */ 72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 76#define FLEXCAN_CTRL_BOFF_MSK BIT(15) 77#define FLEXCAN_CTRL_ERR_MSK BIT(14) 78#define FLEXCAN_CTRL_CLK_SRC BIT(13) 79#define FLEXCAN_CTRL_LPB BIT(12) 80#define FLEXCAN_CTRL_TWRN_MSK BIT(11) 81#define FLEXCAN_CTRL_RWRN_MSK BIT(10) 82#define FLEXCAN_CTRL_SMP BIT(7) 83#define FLEXCAN_CTRL_BOFF_REC BIT(6) 84#define FLEXCAN_CTRL_TSYN BIT(5) 85#define FLEXCAN_CTRL_LBUF BIT(4) 86#define FLEXCAN_CTRL_LOM BIT(3) 87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 89#define FLEXCAN_CTRL_ERR_STATE \ 90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 91 FLEXCAN_CTRL_BOFF_MSK) 92#define FLEXCAN_CTRL_ERR_ALL \ 93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 94 95/* FLEXCAN error and status register (ESR) bits */ 96#define FLEXCAN_ESR_TWRN_INT BIT(17) 97#define FLEXCAN_ESR_RWRN_INT BIT(16) 98#define FLEXCAN_ESR_BIT1_ERR BIT(15) 99#define FLEXCAN_ESR_BIT0_ERR BIT(14) 100#define FLEXCAN_ESR_ACK_ERR BIT(13) 101#define FLEXCAN_ESR_CRC_ERR BIT(12) 102#define FLEXCAN_ESR_FRM_ERR BIT(11) 103#define FLEXCAN_ESR_STF_ERR BIT(10) 104#define FLEXCAN_ESR_TX_WRN BIT(9) 105#define FLEXCAN_ESR_RX_WRN BIT(8) 106#define FLEXCAN_ESR_IDLE BIT(7) 107#define FLEXCAN_ESR_TXRX BIT(6) 108#define FLEXCAN_EST_FLT_CONF_SHIFT (4) 109#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 110#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 111#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 112#define FLEXCAN_ESR_BOFF_INT BIT(2) 113#define FLEXCAN_ESR_ERR_INT BIT(1) 114#define FLEXCAN_ESR_WAK_INT BIT(0) 115#define FLEXCAN_ESR_ERR_BUS \ 116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 119#define FLEXCAN_ESR_ERR_STATE \ 120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 121#define FLEXCAN_ESR_ERR_ALL \ 122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 123#define FLEXCAN_ESR_ALL_INT \ 124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ 125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) 126 127/* FLEXCAN interrupt flag register (IFLAG) bits */ 128#define FLEXCAN_TX_BUF_ID 8 129#define FLEXCAN_IFLAG_BUF(x) BIT(x) 130#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 131#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 132#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 133#define FLEXCAN_IFLAG_DEFAULT \ 134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ 135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) 136 137/* FLEXCAN message buffers */ 138#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) 139#define FLEXCAN_MB_CNT_SRR BIT(22) 140#define FLEXCAN_MB_CNT_IDE BIT(21) 141#define FLEXCAN_MB_CNT_RTR BIT(20) 142#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 143#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 144 145#define FLEXCAN_MB_CODE_MASK (0xf0ffffff) 146 147/* 148 * FLEXCAN hardware feature flags 149 * 150 * Below is some version info we got: 151 * SOC Version IP-Version Glitch- [TR]WRN_INT 152 * Filter? connected? 153 * MX25 FlexCAN2 03.00.00.00 no no 154 * MX28 FlexCAN2 03.00.04.00 yes yes 155 * MX35 FlexCAN2 03.00.00.00 no no 156 * MX53 FlexCAN2 03.00.00.00 yes no 157 * MX6s FlexCAN3 10.00.12.00 yes yes 158 * 159 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected. 160 */ 161#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */ 162#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */ 163 164/* Structure of the message buffer */ 165struct flexcan_mb { 166 u32 can_ctrl; 167 u32 can_id; 168 u32 data[2]; 169}; 170 171/* Structure of the hardware registers */ 172struct flexcan_regs { 173 u32 mcr; /* 0x00 */ 174 u32 ctrl; /* 0x04 */ 175 u32 timer; /* 0x08 */ 176 u32 _reserved1; /* 0x0c */ 177 u32 rxgmask; /* 0x10 */ 178 u32 rx14mask; /* 0x14 */ 179 u32 rx15mask; /* 0x18 */ 180 u32 ecr; /* 0x1c */ 181 u32 esr; /* 0x20 */ 182 u32 imask2; /* 0x24 */ 183 u32 imask1; /* 0x28 */ 184 u32 iflag2; /* 0x2c */ 185 u32 iflag1; /* 0x30 */ 186 u32 crl2; /* 0x34 */ 187 u32 esr2; /* 0x38 */ 188 u32 imeur; /* 0x3c */ 189 u32 lrfr; /* 0x40 */ 190 u32 crcr; /* 0x44 */ 191 u32 rxfgmask; /* 0x48 */ 192 u32 rxfir; /* 0x4c */ 193 u32 _reserved3[12]; 194 struct flexcan_mb cantxfg[64]; 195}; 196 197struct flexcan_devtype_data { 198 u32 features; /* hardware controller features */ 199}; 200 201struct flexcan_priv { 202 struct can_priv can; 203 struct net_device *dev; 204 struct napi_struct napi; 205 206 void __iomem *base; 207 u32 reg_esr; 208 u32 reg_ctrl_default; 209 210 struct clk *clk_ipg; 211 struct clk *clk_per; 212 struct flexcan_platform_data *pdata; 213 const struct flexcan_devtype_data *devtype_data; 214 struct regulator *reg_xceiver; 215}; 216 217static struct flexcan_devtype_data fsl_p1010_devtype_data = { 218 .features = FLEXCAN_HAS_BROKEN_ERR_STATE, 219}; 220static struct flexcan_devtype_data fsl_imx28_devtype_data; 221static struct flexcan_devtype_data fsl_imx6q_devtype_data = { 222 .features = FLEXCAN_HAS_V10_FEATURES, 223}; 224 225static const struct can_bittiming_const flexcan_bittiming_const = { 226 .name = DRV_NAME, 227 .tseg1_min = 4, 228 .tseg1_max = 16, 229 .tseg2_min = 2, 230 .tseg2_max = 8, 231 .sjw_max = 4, 232 .brp_min = 1, 233 .brp_max = 256, 234 .brp_inc = 1, 235}; 236 237/* 238 * Abstract off the read/write for arm versus ppc. 239 */ 240#if defined(__BIG_ENDIAN) 241static inline u32 flexcan_read(void __iomem *addr) 242{ 243 return in_be32(addr); 244} 245 246static inline void flexcan_write(u32 val, void __iomem *addr) 247{ 248 out_be32(addr, val); 249} 250#else 251static inline u32 flexcan_read(void __iomem *addr) 252{ 253 return readl(addr); 254} 255 256static inline void flexcan_write(u32 val, void __iomem *addr) 257{ 258 writel(val, addr); 259} 260#endif 261 262static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, 263 u32 reg_esr) 264{ 265 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 266 (reg_esr & FLEXCAN_ESR_ERR_BUS); 267} 268 269static inline void flexcan_chip_enable(struct flexcan_priv *priv) 270{ 271 struct flexcan_regs __iomem *regs = priv->base; 272 u32 reg; 273 274 reg = flexcan_read(®s->mcr); 275 reg &= ~FLEXCAN_MCR_MDIS; 276 flexcan_write(reg, ®s->mcr); 277 278 udelay(10); 279} 280 281static inline void flexcan_chip_disable(struct flexcan_priv *priv) 282{ 283 struct flexcan_regs __iomem *regs = priv->base; 284 u32 reg; 285 286 reg = flexcan_read(®s->mcr); 287 reg |= FLEXCAN_MCR_MDIS; 288 flexcan_write(reg, ®s->mcr); 289} 290 291static int flexcan_get_berr_counter(const struct net_device *dev, 292 struct can_berr_counter *bec) 293{ 294 const struct flexcan_priv *priv = netdev_priv(dev); 295 struct flexcan_regs __iomem *regs = priv->base; 296 u32 reg = flexcan_read(®s->ecr); 297 298 bec->txerr = (reg >> 0) & 0xff; 299 bec->rxerr = (reg >> 8) & 0xff; 300 301 return 0; 302} 303 304static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 305{ 306 const struct flexcan_priv *priv = netdev_priv(dev); 307 struct flexcan_regs __iomem *regs = priv->base; 308 struct can_frame *cf = (struct can_frame *)skb->data; 309 u32 can_id; 310 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); 311 312 if (can_dropped_invalid_skb(dev, skb)) 313 return NETDEV_TX_OK; 314 315 netif_stop_queue(dev); 316 317 if (cf->can_id & CAN_EFF_FLAG) { 318 can_id = cf->can_id & CAN_EFF_MASK; 319 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 320 } else { 321 can_id = (cf->can_id & CAN_SFF_MASK) << 18; 322 } 323 324 if (cf->can_id & CAN_RTR_FLAG) 325 ctrl |= FLEXCAN_MB_CNT_RTR; 326 327 if (cf->can_dlc > 0) { 328 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 329 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 330 } 331 if (cf->can_dlc > 3) { 332 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 333 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 334 } 335 336 can_put_echo_skb(skb, dev, 0); 337 338 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 339 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 340 341 return NETDEV_TX_OK; 342} 343 344static void do_bus_err(struct net_device *dev, 345 struct can_frame *cf, u32 reg_esr) 346{ 347 struct flexcan_priv *priv = netdev_priv(dev); 348 int rx_errors = 0, tx_errors = 0; 349 350 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 351 352 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 353 netdev_dbg(dev, "BIT1_ERR irq\n"); 354 cf->data[2] |= CAN_ERR_PROT_BIT1; 355 tx_errors = 1; 356 } 357 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 358 netdev_dbg(dev, "BIT0_ERR irq\n"); 359 cf->data[2] |= CAN_ERR_PROT_BIT0; 360 tx_errors = 1; 361 } 362 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 363 netdev_dbg(dev, "ACK_ERR irq\n"); 364 cf->can_id |= CAN_ERR_ACK; 365 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 366 tx_errors = 1; 367 } 368 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 369 netdev_dbg(dev, "CRC_ERR irq\n"); 370 cf->data[2] |= CAN_ERR_PROT_BIT; 371 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 372 rx_errors = 1; 373 } 374 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 375 netdev_dbg(dev, "FRM_ERR irq\n"); 376 cf->data[2] |= CAN_ERR_PROT_FORM; 377 rx_errors = 1; 378 } 379 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 380 netdev_dbg(dev, "STF_ERR irq\n"); 381 cf->data[2] |= CAN_ERR_PROT_STUFF; 382 rx_errors = 1; 383 } 384 385 priv->can.can_stats.bus_error++; 386 if (rx_errors) 387 dev->stats.rx_errors++; 388 if (tx_errors) 389 dev->stats.tx_errors++; 390} 391 392static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) 393{ 394 struct sk_buff *skb; 395 struct can_frame *cf; 396 397 skb = alloc_can_err_skb(dev, &cf); 398 if (unlikely(!skb)) 399 return 0; 400 401 do_bus_err(dev, cf, reg_esr); 402 netif_receive_skb(skb); 403 404 dev->stats.rx_packets++; 405 dev->stats.rx_bytes += cf->can_dlc; 406 407 return 1; 408} 409 410static void do_state(struct net_device *dev, 411 struct can_frame *cf, enum can_state new_state) 412{ 413 struct flexcan_priv *priv = netdev_priv(dev); 414 struct can_berr_counter bec; 415 416 flexcan_get_berr_counter(dev, &bec); 417 418 switch (priv->can.state) { 419 case CAN_STATE_ERROR_ACTIVE: 420 /* 421 * from: ERROR_ACTIVE 422 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 423 * => : there was a warning int 424 */ 425 if (new_state >= CAN_STATE_ERROR_WARNING && 426 new_state <= CAN_STATE_BUS_OFF) { 427 netdev_dbg(dev, "Error Warning IRQ\n"); 428 priv->can.can_stats.error_warning++; 429 430 cf->can_id |= CAN_ERR_CRTL; 431 cf->data[1] = (bec.txerr > bec.rxerr) ? 432 CAN_ERR_CRTL_TX_WARNING : 433 CAN_ERR_CRTL_RX_WARNING; 434 } 435 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 436 /* 437 * from: ERROR_ACTIVE, ERROR_WARNING 438 * to : ERROR_PASSIVE, BUS_OFF 439 * => : error passive int 440 */ 441 if (new_state >= CAN_STATE_ERROR_PASSIVE && 442 new_state <= CAN_STATE_BUS_OFF) { 443 netdev_dbg(dev, "Error Passive IRQ\n"); 444 priv->can.can_stats.error_passive++; 445 446 cf->can_id |= CAN_ERR_CRTL; 447 cf->data[1] = (bec.txerr > bec.rxerr) ? 448 CAN_ERR_CRTL_TX_PASSIVE : 449 CAN_ERR_CRTL_RX_PASSIVE; 450 } 451 break; 452 case CAN_STATE_BUS_OFF: 453 netdev_err(dev, "BUG! " 454 "hardware recovered automatically from BUS_OFF\n"); 455 break; 456 default: 457 break; 458 } 459 460 /* process state changes depending on the new state */ 461 switch (new_state) { 462 case CAN_STATE_ERROR_ACTIVE: 463 netdev_dbg(dev, "Error Active\n"); 464 cf->can_id |= CAN_ERR_PROT; 465 cf->data[2] = CAN_ERR_PROT_ACTIVE; 466 break; 467 case CAN_STATE_BUS_OFF: 468 cf->can_id |= CAN_ERR_BUSOFF; 469 can_bus_off(dev); 470 break; 471 default: 472 break; 473 } 474} 475 476static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) 477{ 478 struct flexcan_priv *priv = netdev_priv(dev); 479 struct sk_buff *skb; 480 struct can_frame *cf; 481 enum can_state new_state; 482 int flt; 483 484 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 485 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 486 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | 487 FLEXCAN_ESR_RX_WRN)))) 488 new_state = CAN_STATE_ERROR_ACTIVE; 489 else 490 new_state = CAN_STATE_ERROR_WARNING; 491 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) 492 new_state = CAN_STATE_ERROR_PASSIVE; 493 else 494 new_state = CAN_STATE_BUS_OFF; 495 496 /* state hasn't changed */ 497 if (likely(new_state == priv->can.state)) 498 return 0; 499 500 skb = alloc_can_err_skb(dev, &cf); 501 if (unlikely(!skb)) 502 return 0; 503 504 do_state(dev, cf, new_state); 505 priv->can.state = new_state; 506 netif_receive_skb(skb); 507 508 dev->stats.rx_packets++; 509 dev->stats.rx_bytes += cf->can_dlc; 510 511 return 1; 512} 513 514static void flexcan_read_fifo(const struct net_device *dev, 515 struct can_frame *cf) 516{ 517 const struct flexcan_priv *priv = netdev_priv(dev); 518 struct flexcan_regs __iomem *regs = priv->base; 519 struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; 520 u32 reg_ctrl, reg_id; 521 522 reg_ctrl = flexcan_read(&mb->can_ctrl); 523 reg_id = flexcan_read(&mb->can_id); 524 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 525 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 526 else 527 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; 528 529 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 530 cf->can_id |= CAN_RTR_FLAG; 531 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 532 533 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); 534 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); 535 536 /* mark as read */ 537 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 538 flexcan_read(®s->timer); 539} 540 541static int flexcan_read_frame(struct net_device *dev) 542{ 543 struct net_device_stats *stats = &dev->stats; 544 struct can_frame *cf; 545 struct sk_buff *skb; 546 547 skb = alloc_can_skb(dev, &cf); 548 if (unlikely(!skb)) { 549 stats->rx_dropped++; 550 return 0; 551 } 552 553 flexcan_read_fifo(dev, cf); 554 netif_receive_skb(skb); 555 556 stats->rx_packets++; 557 stats->rx_bytes += cf->can_dlc; 558 559 can_led_event(dev, CAN_LED_EVENT_RX); 560 561 return 1; 562} 563 564static int flexcan_poll(struct napi_struct *napi, int quota) 565{ 566 struct net_device *dev = napi->dev; 567 const struct flexcan_priv *priv = netdev_priv(dev); 568 struct flexcan_regs __iomem *regs = priv->base; 569 u32 reg_iflag1, reg_esr; 570 int work_done = 0; 571 572 /* 573 * The error bits are cleared on read, 574 * use saved value from irq handler. 575 */ 576 reg_esr = flexcan_read(®s->esr) | priv->reg_esr; 577 578 /* handle state changes */ 579 work_done += flexcan_poll_state(dev, reg_esr); 580 581 /* handle RX-FIFO */ 582 reg_iflag1 = flexcan_read(®s->iflag1); 583 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 584 work_done < quota) { 585 work_done += flexcan_read_frame(dev); 586 reg_iflag1 = flexcan_read(®s->iflag1); 587 } 588 589 /* report bus errors */ 590 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) 591 work_done += flexcan_poll_bus_err(dev, reg_esr); 592 593 if (work_done < quota) { 594 napi_complete(napi); 595 /* enable IRQs */ 596 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 597 flexcan_write(priv->reg_ctrl_default, ®s->ctrl); 598 } 599 600 return work_done; 601} 602 603static irqreturn_t flexcan_irq(int irq, void *dev_id) 604{ 605 struct net_device *dev = dev_id; 606 struct net_device_stats *stats = &dev->stats; 607 struct flexcan_priv *priv = netdev_priv(dev); 608 struct flexcan_regs __iomem *regs = priv->base; 609 u32 reg_iflag1, reg_esr; 610 611 reg_iflag1 = flexcan_read(®s->iflag1); 612 reg_esr = flexcan_read(®s->esr); 613 /* ACK all bus error and state change IRQ sources */ 614 if (reg_esr & FLEXCAN_ESR_ALL_INT) 615 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); 616 617 /* 618 * schedule NAPI in case of: 619 * - rx IRQ 620 * - state change IRQ 621 * - bus error IRQ and bus error reporting is activated 622 */ 623 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || 624 (reg_esr & FLEXCAN_ESR_ERR_STATE) || 625 flexcan_has_and_handle_berr(priv, reg_esr)) { 626 /* 627 * The error bits are cleared on read, 628 * save them for later use. 629 */ 630 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 631 flexcan_write(FLEXCAN_IFLAG_DEFAULT & 632 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); 633 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 634 ®s->ctrl); 635 napi_schedule(&priv->napi); 636 } 637 638 /* FIFO overflow */ 639 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 640 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); 641 dev->stats.rx_over_errors++; 642 dev->stats.rx_errors++; 643 } 644 645 /* transmission complete interrupt */ 646 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 647 stats->tx_bytes += can_get_echo_skb(dev, 0); 648 stats->tx_packets++; 649 can_led_event(dev, CAN_LED_EVENT_TX); 650 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); 651 netif_wake_queue(dev); 652 } 653 654 return IRQ_HANDLED; 655} 656 657static void flexcan_set_bittiming(struct net_device *dev) 658{ 659 const struct flexcan_priv *priv = netdev_priv(dev); 660 const struct can_bittiming *bt = &priv->can.bittiming; 661 struct flexcan_regs __iomem *regs = priv->base; 662 u32 reg; 663 664 reg = flexcan_read(®s->ctrl); 665 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 666 FLEXCAN_CTRL_RJW(0x3) | 667 FLEXCAN_CTRL_PSEG1(0x7) | 668 FLEXCAN_CTRL_PSEG2(0x7) | 669 FLEXCAN_CTRL_PROPSEG(0x7) | 670 FLEXCAN_CTRL_LPB | 671 FLEXCAN_CTRL_SMP | 672 FLEXCAN_CTRL_LOM); 673 674 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 675 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 676 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 677 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 678 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 679 680 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 681 reg |= FLEXCAN_CTRL_LPB; 682 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 683 reg |= FLEXCAN_CTRL_LOM; 684 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 685 reg |= FLEXCAN_CTRL_SMP; 686 687 netdev_info(dev, "writing ctrl=0x%08x\n", reg); 688 flexcan_write(reg, ®s->ctrl); 689 690 /* print chip status */ 691 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 692 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 693} 694 695/* 696 * flexcan_chip_start 697 * 698 * this functions is entered with clocks enabled 699 * 700 */ 701static int flexcan_chip_start(struct net_device *dev) 702{ 703 struct flexcan_priv *priv = netdev_priv(dev); 704 struct flexcan_regs __iomem *regs = priv->base; 705 unsigned int i; 706 int err; 707 u32 reg_mcr, reg_ctrl; 708 709 /* enable module */ 710 flexcan_chip_enable(priv); 711 712 /* soft reset */ 713 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 714 udelay(10); 715 716 reg_mcr = flexcan_read(®s->mcr); 717 if (reg_mcr & FLEXCAN_MCR_SOFTRST) { 718 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n", 719 reg_mcr); 720 err = -ENODEV; 721 goto out; 722 } 723 724 flexcan_set_bittiming(dev); 725 726 /* 727 * MCR 728 * 729 * enable freeze 730 * enable fifo 731 * halt now 732 * only supervisor access 733 * enable warning int 734 * choose format C 735 * disable local echo 736 * 737 */ 738 reg_mcr = flexcan_read(®s->mcr); 739 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 740 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 741 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS; 742 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); 743 flexcan_write(reg_mcr, ®s->mcr); 744 745 /* 746 * CTRL 747 * 748 * disable timer sync feature 749 * 750 * disable auto busoff recovery 751 * transmit lowest buffer first 752 * 753 * enable tx and rx warning interrupt 754 * enable bus off interrupt 755 * (== FLEXCAN_CTRL_ERR_STATE) 756 */ 757 reg_ctrl = flexcan_read(®s->ctrl); 758 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 759 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 760 FLEXCAN_CTRL_ERR_STATE; 761 /* 762 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), 763 * on most Flexcan cores, too. Otherwise we don't get 764 * any error warning or passive interrupts. 765 */ 766 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE || 767 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 768 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; 769 770 /* save for later use */ 771 priv->reg_ctrl_default = reg_ctrl; 772 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 773 flexcan_write(reg_ctrl, ®s->ctrl); 774 775 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) { 776 flexcan_write(0, ®s->cantxfg[i].can_ctrl); 777 flexcan_write(0, ®s->cantxfg[i].can_id); 778 flexcan_write(0, ®s->cantxfg[i].data[0]); 779 flexcan_write(0, ®s->cantxfg[i].data[1]); 780 781 /* put MB into rx queue */ 782 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4), 783 ®s->cantxfg[i].can_ctrl); 784 } 785 786 /* acceptance mask/acceptance code (accept everything) */ 787 flexcan_write(0x0, ®s->rxgmask); 788 flexcan_write(0x0, ®s->rx14mask); 789 flexcan_write(0x0, ®s->rx15mask); 790 791 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) 792 flexcan_write(0x0, ®s->rxfgmask); 793 794 if (priv->reg_xceiver) { 795 err = regulator_enable(priv->reg_xceiver); 796 if (err) 797 goto out; 798 } 799 800 /* synchronize with the can bus */ 801 reg_mcr = flexcan_read(®s->mcr); 802 reg_mcr &= ~FLEXCAN_MCR_HALT; 803 flexcan_write(reg_mcr, ®s->mcr); 804 805 priv->can.state = CAN_STATE_ERROR_ACTIVE; 806 807 /* enable FIFO interrupts */ 808 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 809 810 /* print chip status */ 811 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, 812 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 813 814 return 0; 815 816 out: 817 flexcan_chip_disable(priv); 818 return err; 819} 820 821/* 822 * flexcan_chip_stop 823 * 824 * this functions is entered with clocks enabled 825 * 826 */ 827static void flexcan_chip_stop(struct net_device *dev) 828{ 829 struct flexcan_priv *priv = netdev_priv(dev); 830 struct flexcan_regs __iomem *regs = priv->base; 831 u32 reg; 832 833 /* Disable all interrupts */ 834 flexcan_write(0, ®s->imask1); 835 836 /* Disable + halt module */ 837 reg = flexcan_read(®s->mcr); 838 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT; 839 flexcan_write(reg, ®s->mcr); 840 841 if (priv->reg_xceiver) 842 regulator_disable(priv->reg_xceiver); 843 priv->can.state = CAN_STATE_STOPPED; 844 845 return; 846} 847 848static int flexcan_open(struct net_device *dev) 849{ 850 struct flexcan_priv *priv = netdev_priv(dev); 851 int err; 852 853 clk_prepare_enable(priv->clk_ipg); 854 clk_prepare_enable(priv->clk_per); 855 856 err = open_candev(dev); 857 if (err) 858 goto out; 859 860 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 861 if (err) 862 goto out_close; 863 864 /* start chip and queuing */ 865 err = flexcan_chip_start(dev); 866 if (err) 867 goto out_close; 868 869 can_led_event(dev, CAN_LED_EVENT_OPEN); 870 871 napi_enable(&priv->napi); 872 netif_start_queue(dev); 873 874 return 0; 875 876 out_close: 877 close_candev(dev); 878 out: 879 clk_disable_unprepare(priv->clk_per); 880 clk_disable_unprepare(priv->clk_ipg); 881 882 return err; 883} 884 885static int flexcan_close(struct net_device *dev) 886{ 887 struct flexcan_priv *priv = netdev_priv(dev); 888 889 netif_stop_queue(dev); 890 napi_disable(&priv->napi); 891 flexcan_chip_stop(dev); 892 893 free_irq(dev->irq, dev); 894 clk_disable_unprepare(priv->clk_per); 895 clk_disable_unprepare(priv->clk_ipg); 896 897 close_candev(dev); 898 899 can_led_event(dev, CAN_LED_EVENT_STOP); 900 901 return 0; 902} 903 904static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 905{ 906 int err; 907 908 switch (mode) { 909 case CAN_MODE_START: 910 err = flexcan_chip_start(dev); 911 if (err) 912 return err; 913 914 netif_wake_queue(dev); 915 break; 916 917 default: 918 return -EOPNOTSUPP; 919 } 920 921 return 0; 922} 923 924static const struct net_device_ops flexcan_netdev_ops = { 925 .ndo_open = flexcan_open, 926 .ndo_stop = flexcan_close, 927 .ndo_start_xmit = flexcan_start_xmit, 928}; 929 930static int register_flexcandev(struct net_device *dev) 931{ 932 struct flexcan_priv *priv = netdev_priv(dev); 933 struct flexcan_regs __iomem *regs = priv->base; 934 u32 reg, err; 935 936 clk_prepare_enable(priv->clk_ipg); 937 clk_prepare_enable(priv->clk_per); 938 939 /* select "bus clock", chip must be disabled */ 940 flexcan_chip_disable(priv); 941 reg = flexcan_read(®s->ctrl); 942 reg |= FLEXCAN_CTRL_CLK_SRC; 943 flexcan_write(reg, ®s->ctrl); 944 945 flexcan_chip_enable(priv); 946 947 /* set freeze, halt and activate FIFO, restrict register access */ 948 reg = flexcan_read(®s->mcr); 949 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 950 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 951 flexcan_write(reg, ®s->mcr); 952 953 /* 954 * Currently we only support newer versions of this core 955 * featuring a RX FIFO. Older cores found on some Coldfire 956 * derivates are not yet supported. 957 */ 958 reg = flexcan_read(®s->mcr); 959 if (!(reg & FLEXCAN_MCR_FEN)) { 960 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); 961 err = -ENODEV; 962 goto out; 963 } 964 965 err = register_candev(dev); 966 967 out: 968 /* disable core and turn off clocks */ 969 flexcan_chip_disable(priv); 970 clk_disable_unprepare(priv->clk_per); 971 clk_disable_unprepare(priv->clk_ipg); 972 973 return err; 974} 975 976static void unregister_flexcandev(struct net_device *dev) 977{ 978 unregister_candev(dev); 979} 980 981static const struct of_device_id flexcan_of_match[] = { 982 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, 983 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, 984 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, 985 { /* sentinel */ }, 986}; 987MODULE_DEVICE_TABLE(of, flexcan_of_match); 988 989static const struct platform_device_id flexcan_id_table[] = { 990 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, }, 991 { /* sentinel */ }, 992}; 993MODULE_DEVICE_TABLE(platform, flexcan_id_table); 994 995static int flexcan_probe(struct platform_device *pdev) 996{ 997 const struct of_device_id *of_id; 998 const struct flexcan_devtype_data *devtype_data; 999 struct net_device *dev; 1000 struct flexcan_priv *priv; 1001 struct resource *mem; 1002 struct clk *clk_ipg = NULL, *clk_per = NULL; 1003 void __iomem *base; 1004 resource_size_t mem_size; 1005 int err, irq; 1006 u32 clock_freq = 0; 1007 1008 if (pdev->dev.of_node) 1009 of_property_read_u32(pdev->dev.of_node, 1010 "clock-frequency", &clock_freq); 1011 1012 if (!clock_freq) { 1013 clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1014 if (IS_ERR(clk_ipg)) { 1015 dev_err(&pdev->dev, "no ipg clock defined\n"); 1016 err = PTR_ERR(clk_ipg); 1017 goto failed_clock; 1018 } 1019 clock_freq = clk_get_rate(clk_ipg); 1020 1021 clk_per = devm_clk_get(&pdev->dev, "per"); 1022 if (IS_ERR(clk_per)) { 1023 dev_err(&pdev->dev, "no per clock defined\n"); 1024 err = PTR_ERR(clk_per); 1025 goto failed_clock; 1026 } 1027 } 1028 1029 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1030 irq = platform_get_irq(pdev, 0); 1031 if (!mem || irq <= 0) { 1032 err = -ENODEV; 1033 goto failed_get; 1034 } 1035 1036 mem_size = resource_size(mem); 1037 if (!request_mem_region(mem->start, mem_size, pdev->name)) { 1038 err = -EBUSY; 1039 goto failed_get; 1040 } 1041 1042 base = ioremap(mem->start, mem_size); 1043 if (!base) { 1044 err = -ENOMEM; 1045 goto failed_map; 1046 } 1047 1048 dev = alloc_candev(sizeof(struct flexcan_priv), 1); 1049 if (!dev) { 1050 err = -ENOMEM; 1051 goto failed_alloc; 1052 } 1053 1054 of_id = of_match_device(flexcan_of_match, &pdev->dev); 1055 if (of_id) { 1056 devtype_data = of_id->data; 1057 } else if (pdev->id_entry->driver_data) { 1058 devtype_data = (struct flexcan_devtype_data *) 1059 pdev->id_entry->driver_data; 1060 } else { 1061 err = -ENODEV; 1062 goto failed_devtype; 1063 } 1064 1065 dev->netdev_ops = &flexcan_netdev_ops; 1066 dev->irq = irq; 1067 dev->flags |= IFF_ECHO; 1068 1069 priv = netdev_priv(dev); 1070 priv->can.clock.freq = clock_freq; 1071 priv->can.bittiming_const = &flexcan_bittiming_const; 1072 priv->can.do_set_mode = flexcan_set_mode; 1073 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 1074 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1075 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 1076 CAN_CTRLMODE_BERR_REPORTING; 1077 priv->base = base; 1078 priv->dev = dev; 1079 priv->clk_ipg = clk_ipg; 1080 priv->clk_per = clk_per; 1081 priv->pdata = pdev->dev.platform_data; 1082 priv->devtype_data = devtype_data; 1083 1084 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); 1085 if (IS_ERR(priv->reg_xceiver)) 1086 priv->reg_xceiver = NULL; 1087 1088 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); 1089 1090 dev_set_drvdata(&pdev->dev, dev); 1091 SET_NETDEV_DEV(dev, &pdev->dev); 1092 1093 err = register_flexcandev(dev); 1094 if (err) { 1095 dev_err(&pdev->dev, "registering netdev failed\n"); 1096 goto failed_register; 1097 } 1098 1099 devm_can_led_init(dev); 1100 1101 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1102 priv->base, dev->irq); 1103 1104 return 0; 1105 1106 failed_register: 1107 failed_devtype: 1108 free_candev(dev); 1109 failed_alloc: 1110 iounmap(base); 1111 failed_map: 1112 release_mem_region(mem->start, mem_size); 1113 failed_get: 1114 failed_clock: 1115 return err; 1116} 1117 1118static int flexcan_remove(struct platform_device *pdev) 1119{ 1120 struct net_device *dev = platform_get_drvdata(pdev); 1121 struct flexcan_priv *priv = netdev_priv(dev); 1122 struct resource *mem; 1123 1124 unregister_flexcandev(dev); 1125 iounmap(priv->base); 1126 1127 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1128 release_mem_region(mem->start, resource_size(mem)); 1129 1130 free_candev(dev); 1131 1132 return 0; 1133} 1134 1135#ifdef CONFIG_PM_SLEEP 1136static int flexcan_suspend(struct device *device) 1137{ 1138 struct net_device *dev = dev_get_drvdata(device); 1139 struct flexcan_priv *priv = netdev_priv(dev); 1140 1141 flexcan_chip_disable(priv); 1142 1143 if (netif_running(dev)) { 1144 netif_stop_queue(dev); 1145 netif_device_detach(dev); 1146 } 1147 priv->can.state = CAN_STATE_SLEEPING; 1148 1149 return 0; 1150} 1151 1152static int flexcan_resume(struct device *device) 1153{ 1154 struct net_device *dev = dev_get_drvdata(device); 1155 struct flexcan_priv *priv = netdev_priv(dev); 1156 1157 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1158 if (netif_running(dev)) { 1159 netif_device_attach(dev); 1160 netif_start_queue(dev); 1161 } 1162 flexcan_chip_enable(priv); 1163 1164 return 0; 1165} 1166#endif /* CONFIG_PM_SLEEP */ 1167 1168static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume); 1169 1170static struct platform_driver flexcan_driver = { 1171 .driver = { 1172 .name = DRV_NAME, 1173 .owner = THIS_MODULE, 1174 .pm = &flexcan_pm_ops, 1175 .of_match_table = flexcan_of_match, 1176 }, 1177 .probe = flexcan_probe, 1178 .remove = flexcan_remove, 1179 .id_table = flexcan_id_table, 1180}; 1181 1182module_platform_driver(flexcan_driver); 1183 1184MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 1185 "Marc Kleine-Budde <kernel@pengutronix.de>"); 1186MODULE_LICENSE("GPL v2"); 1187MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 1188