flexcan.c revision cdce844865bea6869b34bacc98af3711774f5bb5
1/* 2 * flexcan.c - FLEXCAN CAN controller driver 3 * 4 * Copyright (c) 2005-2006 Varma Electronics Oy 5 * Copyright (c) 2009 Sascha Hauer, Pengutronix 6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix 7 * 8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com> 9 * 10 * LICENCE: 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22#include <linux/netdevice.h> 23#include <linux/can.h> 24#include <linux/can/dev.h> 25#include <linux/can/error.h> 26#include <linux/can/led.h> 27#include <linux/clk.h> 28#include <linux/delay.h> 29#include <linux/if_arp.h> 30#include <linux/if_ether.h> 31#include <linux/interrupt.h> 32#include <linux/io.h> 33#include <linux/kernel.h> 34#include <linux/list.h> 35#include <linux/module.h> 36#include <linux/of.h> 37#include <linux/of_device.h> 38#include <linux/platform_device.h> 39#include <linux/regulator/consumer.h> 40 41#define DRV_NAME "flexcan" 42 43/* 8 for RX fifo and 2 error handling */ 44#define FLEXCAN_NAPI_WEIGHT (8 + 2) 45 46/* FLEXCAN module configuration register (CANMCR) bits */ 47#define FLEXCAN_MCR_MDIS BIT(31) 48#define FLEXCAN_MCR_FRZ BIT(30) 49#define FLEXCAN_MCR_FEN BIT(29) 50#define FLEXCAN_MCR_HALT BIT(28) 51#define FLEXCAN_MCR_NOT_RDY BIT(27) 52#define FLEXCAN_MCR_WAK_MSK BIT(26) 53#define FLEXCAN_MCR_SOFTRST BIT(25) 54#define FLEXCAN_MCR_FRZ_ACK BIT(24) 55#define FLEXCAN_MCR_SUPV BIT(23) 56#define FLEXCAN_MCR_SLF_WAK BIT(22) 57#define FLEXCAN_MCR_WRN_EN BIT(21) 58#define FLEXCAN_MCR_LPM_ACK BIT(20) 59#define FLEXCAN_MCR_WAK_SRC BIT(19) 60#define FLEXCAN_MCR_DOZE BIT(18) 61#define FLEXCAN_MCR_SRX_DIS BIT(17) 62#define FLEXCAN_MCR_BCC BIT(16) 63#define FLEXCAN_MCR_LPRIO_EN BIT(13) 64#define FLEXCAN_MCR_AEN BIT(12) 65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f) 66#define FLEXCAN_MCR_IDAM_A (0 << 8) 67#define FLEXCAN_MCR_IDAM_B (1 << 8) 68#define FLEXCAN_MCR_IDAM_C (2 << 8) 69#define FLEXCAN_MCR_IDAM_D (3 << 8) 70 71/* FLEXCAN control register (CANCTRL) bits */ 72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 76#define FLEXCAN_CTRL_BOFF_MSK BIT(15) 77#define FLEXCAN_CTRL_ERR_MSK BIT(14) 78#define FLEXCAN_CTRL_CLK_SRC BIT(13) 79#define FLEXCAN_CTRL_LPB BIT(12) 80#define FLEXCAN_CTRL_TWRN_MSK BIT(11) 81#define FLEXCAN_CTRL_RWRN_MSK BIT(10) 82#define FLEXCAN_CTRL_SMP BIT(7) 83#define FLEXCAN_CTRL_BOFF_REC BIT(6) 84#define FLEXCAN_CTRL_TSYN BIT(5) 85#define FLEXCAN_CTRL_LBUF BIT(4) 86#define FLEXCAN_CTRL_LOM BIT(3) 87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 89#define FLEXCAN_CTRL_ERR_STATE \ 90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 91 FLEXCAN_CTRL_BOFF_MSK) 92#define FLEXCAN_CTRL_ERR_ALL \ 93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 94 95/* FLEXCAN control register 2 (CTRL2) bits */ 96#define FLEXCAN_CRL2_ECRWRE BIT(29) 97#define FLEXCAN_CRL2_WRMFRZ BIT(28) 98#define FLEXCAN_CRL2_RFFN(x) (((x) & 0x0f) << 24) 99#define FLEXCAN_CRL2_TASD(x) (((x) & 0x1f) << 19) 100#define FLEXCAN_CRL2_MRP BIT(18) 101#define FLEXCAN_CRL2_RRS BIT(17) 102#define FLEXCAN_CRL2_EACEN BIT(16) 103 104/* FLEXCAN memory error control register (MECR) bits */ 105#define FLEXCAN_MECR_ECRWRDIS BIT(31) 106#define FLEXCAN_MECR_HANCEI_MSK BIT(19) 107#define FLEXCAN_MECR_FANCEI_MSK BIT(18) 108#define FLEXCAN_MECR_CEI_MSK BIT(16) 109#define FLEXCAN_MECR_HAERRIE BIT(15) 110#define FLEXCAN_MECR_FAERRIE BIT(14) 111#define FLEXCAN_MECR_EXTERRIE BIT(13) 112#define FLEXCAN_MECR_RERRDIS BIT(9) 113#define FLEXCAN_MECR_ECCDIS BIT(8) 114#define FLEXCAN_MECR_NCEFAFRZ BIT(7) 115 116/* FLEXCAN error and status register (ESR) bits */ 117#define FLEXCAN_ESR_TWRN_INT BIT(17) 118#define FLEXCAN_ESR_RWRN_INT BIT(16) 119#define FLEXCAN_ESR_BIT1_ERR BIT(15) 120#define FLEXCAN_ESR_BIT0_ERR BIT(14) 121#define FLEXCAN_ESR_ACK_ERR BIT(13) 122#define FLEXCAN_ESR_CRC_ERR BIT(12) 123#define FLEXCAN_ESR_FRM_ERR BIT(11) 124#define FLEXCAN_ESR_STF_ERR BIT(10) 125#define FLEXCAN_ESR_TX_WRN BIT(9) 126#define FLEXCAN_ESR_RX_WRN BIT(8) 127#define FLEXCAN_ESR_IDLE BIT(7) 128#define FLEXCAN_ESR_TXRX BIT(6) 129#define FLEXCAN_EST_FLT_CONF_SHIFT (4) 130#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 131#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 132#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 133#define FLEXCAN_ESR_BOFF_INT BIT(2) 134#define FLEXCAN_ESR_ERR_INT BIT(1) 135#define FLEXCAN_ESR_WAK_INT BIT(0) 136#define FLEXCAN_ESR_ERR_BUS \ 137 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 138 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 139 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 140#define FLEXCAN_ESR_ERR_STATE \ 141 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 142#define FLEXCAN_ESR_ERR_ALL \ 143 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 144#define FLEXCAN_ESR_ALL_INT \ 145 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ 146 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) 147 148/* FLEXCAN interrupt flag register (IFLAG) bits */ 149#define FLEXCAN_TX_BUF_ID 8 150#define FLEXCAN_IFLAG_BUF(x) BIT(x) 151#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 152#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 153#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 154#define FLEXCAN_IFLAG_DEFAULT \ 155 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ 156 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) 157 158/* FLEXCAN message buffers */ 159#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) 160#define FLEXCAN_MB_CNT_SRR BIT(22) 161#define FLEXCAN_MB_CNT_IDE BIT(21) 162#define FLEXCAN_MB_CNT_RTR BIT(20) 163#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 164#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 165 166#define FLEXCAN_MB_CODE_MASK (0xf0ffffff) 167 168#define FLEXCAN_TIMEOUT_US (50) 169 170/* 171 * FLEXCAN hardware feature flags 172 * 173 * Below is some version info we got: 174 * SOC Version IP-Version Glitch- [TR]WRN_INT Memory err 175 * Filter? connected? detection 176 * MX25 FlexCAN2 03.00.00.00 no no no 177 * MX28 FlexCAN2 03.00.04.00 yes yes no 178 * MX35 FlexCAN2 03.00.00.00 no no no 179 * MX53 FlexCAN2 03.00.00.00 yes no no 180 * MX6s FlexCAN3 10.00.12.00 yes yes no 181 * VF610 FlexCAN3 ? no yes yes 182 * 183 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected. 184 */ 185#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */ 186#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */ 187#define FLEXCAN_HAS_MECR_FEATURES BIT(3) /* Memory error detection */ 188 189/* Structure of the message buffer */ 190struct flexcan_mb { 191 u32 can_ctrl; 192 u32 can_id; 193 u32 data[2]; 194}; 195 196/* Structure of the hardware registers */ 197struct flexcan_regs { 198 u32 mcr; /* 0x00 */ 199 u32 ctrl; /* 0x04 */ 200 u32 timer; /* 0x08 */ 201 u32 _reserved1; /* 0x0c */ 202 u32 rxgmask; /* 0x10 */ 203 u32 rx14mask; /* 0x14 */ 204 u32 rx15mask; /* 0x18 */ 205 u32 ecr; /* 0x1c */ 206 u32 esr; /* 0x20 */ 207 u32 imask2; /* 0x24 */ 208 u32 imask1; /* 0x28 */ 209 u32 iflag2; /* 0x2c */ 210 u32 iflag1; /* 0x30 */ 211 u32 crl2; /* 0x34 */ 212 u32 esr2; /* 0x38 */ 213 u32 imeur; /* 0x3c */ 214 u32 lrfr; /* 0x40 */ 215 u32 crcr; /* 0x44 */ 216 u32 rxfgmask; /* 0x48 */ 217 u32 rxfir; /* 0x4c */ 218 u32 _reserved3[12]; /* 0x50 */ 219 struct flexcan_mb cantxfg[64]; /* 0x80 */ 220 u32 _reserved4[408]; 221 u32 mecr; /* 0xae0 */ 222 u32 erriar; /* 0xae4 */ 223 u32 erridpr; /* 0xae8 */ 224 u32 errippr; /* 0xaec */ 225 u32 rerrar; /* 0xaf0 */ 226 u32 rerrdr; /* 0xaf4 */ 227 u32 rerrsynr; /* 0xaf8 */ 228 u32 errsr; /* 0xafc */ 229}; 230 231struct flexcan_devtype_data { 232 u32 features; /* hardware controller features */ 233}; 234 235struct flexcan_priv { 236 struct can_priv can; 237 struct net_device *dev; 238 struct napi_struct napi; 239 240 void __iomem *base; 241 u32 reg_esr; 242 u32 reg_ctrl_default; 243 244 struct clk *clk_ipg; 245 struct clk *clk_per; 246 struct flexcan_platform_data *pdata; 247 const struct flexcan_devtype_data *devtype_data; 248 struct regulator *reg_xceiver; 249}; 250 251static struct flexcan_devtype_data fsl_p1010_devtype_data = { 252 .features = FLEXCAN_HAS_BROKEN_ERR_STATE, 253}; 254static struct flexcan_devtype_data fsl_imx28_devtype_data; 255static struct flexcan_devtype_data fsl_imx6q_devtype_data = { 256 .features = FLEXCAN_HAS_V10_FEATURES, 257}; 258static struct flexcan_devtype_data fsl_vf610_devtype_data = { 259 .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES, 260}; 261 262static const struct can_bittiming_const flexcan_bittiming_const = { 263 .name = DRV_NAME, 264 .tseg1_min = 4, 265 .tseg1_max = 16, 266 .tseg2_min = 2, 267 .tseg2_max = 8, 268 .sjw_max = 4, 269 .brp_min = 1, 270 .brp_max = 256, 271 .brp_inc = 1, 272}; 273 274/* 275 * Abstract off the read/write for arm versus ppc. This 276 * assumes that PPC uses big-endian registers and everything 277 * else uses little-endian registers, independent of CPU 278 * endianess. 279 */ 280#if defined(CONFIG_PPC) 281static inline u32 flexcan_read(void __iomem *addr) 282{ 283 return in_be32(addr); 284} 285 286static inline void flexcan_write(u32 val, void __iomem *addr) 287{ 288 out_be32(addr, val); 289} 290#else 291static inline u32 flexcan_read(void __iomem *addr) 292{ 293 return readl(addr); 294} 295 296static inline void flexcan_write(u32 val, void __iomem *addr) 297{ 298 writel(val, addr); 299} 300#endif 301 302static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv) 303{ 304 if (!priv->reg_xceiver) 305 return 0; 306 307 return regulator_enable(priv->reg_xceiver); 308} 309 310static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv) 311{ 312 if (!priv->reg_xceiver) 313 return 0; 314 315 return regulator_disable(priv->reg_xceiver); 316} 317 318static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, 319 u32 reg_esr) 320{ 321 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 322 (reg_esr & FLEXCAN_ESR_ERR_BUS); 323} 324 325static int flexcan_chip_enable(struct flexcan_priv *priv) 326{ 327 struct flexcan_regs __iomem *regs = priv->base; 328 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 329 u32 reg; 330 331 reg = flexcan_read(®s->mcr); 332 reg &= ~FLEXCAN_MCR_MDIS; 333 flexcan_write(reg, ®s->mcr); 334 335 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 336 usleep_range(10, 20); 337 338 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK) 339 return -ETIMEDOUT; 340 341 return 0; 342} 343 344static int flexcan_chip_disable(struct flexcan_priv *priv) 345{ 346 struct flexcan_regs __iomem *regs = priv->base; 347 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 348 u32 reg; 349 350 reg = flexcan_read(®s->mcr); 351 reg |= FLEXCAN_MCR_MDIS; 352 flexcan_write(reg, ®s->mcr); 353 354 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 355 usleep_range(10, 20); 356 357 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 358 return -ETIMEDOUT; 359 360 return 0; 361} 362 363static int flexcan_chip_freeze(struct flexcan_priv *priv) 364{ 365 struct flexcan_regs __iomem *regs = priv->base; 366 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate; 367 u32 reg; 368 369 reg = flexcan_read(®s->mcr); 370 reg |= FLEXCAN_MCR_HALT; 371 flexcan_write(reg, ®s->mcr); 372 373 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 374 usleep_range(100, 200); 375 376 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 377 return -ETIMEDOUT; 378 379 return 0; 380} 381 382static int flexcan_chip_unfreeze(struct flexcan_priv *priv) 383{ 384 struct flexcan_regs __iomem *regs = priv->base; 385 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 386 u32 reg; 387 388 reg = flexcan_read(®s->mcr); 389 reg &= ~FLEXCAN_MCR_HALT; 390 flexcan_write(reg, ®s->mcr); 391 392 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 393 usleep_range(10, 20); 394 395 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK) 396 return -ETIMEDOUT; 397 398 return 0; 399} 400 401static int flexcan_chip_softreset(struct flexcan_priv *priv) 402{ 403 struct flexcan_regs __iomem *regs = priv->base; 404 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 405 406 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 407 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)) 408 usleep_range(10, 20); 409 410 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST) 411 return -ETIMEDOUT; 412 413 return 0; 414} 415 416 417static int __flexcan_get_berr_counter(const struct net_device *dev, 418 struct can_berr_counter *bec) 419{ 420 const struct flexcan_priv *priv = netdev_priv(dev); 421 struct flexcan_regs __iomem *regs = priv->base; 422 u32 reg = flexcan_read(®s->ecr); 423 424 bec->txerr = (reg >> 0) & 0xff; 425 bec->rxerr = (reg >> 8) & 0xff; 426 427 return 0; 428} 429 430static int flexcan_get_berr_counter(const struct net_device *dev, 431 struct can_berr_counter *bec) 432{ 433 const struct flexcan_priv *priv = netdev_priv(dev); 434 int err; 435 436 err = clk_prepare_enable(priv->clk_ipg); 437 if (err) 438 return err; 439 440 err = clk_prepare_enable(priv->clk_per); 441 if (err) 442 goto out_disable_ipg; 443 444 err = __flexcan_get_berr_counter(dev, bec); 445 446 clk_disable_unprepare(priv->clk_per); 447 out_disable_ipg: 448 clk_disable_unprepare(priv->clk_ipg); 449 450 return err; 451} 452 453static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 454{ 455 const struct flexcan_priv *priv = netdev_priv(dev); 456 struct flexcan_regs __iomem *regs = priv->base; 457 struct can_frame *cf = (struct can_frame *)skb->data; 458 u32 can_id; 459 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); 460 461 if (can_dropped_invalid_skb(dev, skb)) 462 return NETDEV_TX_OK; 463 464 netif_stop_queue(dev); 465 466 if (cf->can_id & CAN_EFF_FLAG) { 467 can_id = cf->can_id & CAN_EFF_MASK; 468 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 469 } else { 470 can_id = (cf->can_id & CAN_SFF_MASK) << 18; 471 } 472 473 if (cf->can_id & CAN_RTR_FLAG) 474 ctrl |= FLEXCAN_MB_CNT_RTR; 475 476 if (cf->can_dlc > 0) { 477 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 478 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 479 } 480 if (cf->can_dlc > 3) { 481 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 482 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 483 } 484 485 can_put_echo_skb(skb, dev, 0); 486 487 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 488 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 489 490 return NETDEV_TX_OK; 491} 492 493static void do_bus_err(struct net_device *dev, 494 struct can_frame *cf, u32 reg_esr) 495{ 496 struct flexcan_priv *priv = netdev_priv(dev); 497 int rx_errors = 0, tx_errors = 0; 498 499 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 500 501 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 502 netdev_dbg(dev, "BIT1_ERR irq\n"); 503 cf->data[2] |= CAN_ERR_PROT_BIT1; 504 tx_errors = 1; 505 } 506 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 507 netdev_dbg(dev, "BIT0_ERR irq\n"); 508 cf->data[2] |= CAN_ERR_PROT_BIT0; 509 tx_errors = 1; 510 } 511 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 512 netdev_dbg(dev, "ACK_ERR irq\n"); 513 cf->can_id |= CAN_ERR_ACK; 514 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 515 tx_errors = 1; 516 } 517 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 518 netdev_dbg(dev, "CRC_ERR irq\n"); 519 cf->data[2] |= CAN_ERR_PROT_BIT; 520 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 521 rx_errors = 1; 522 } 523 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 524 netdev_dbg(dev, "FRM_ERR irq\n"); 525 cf->data[2] |= CAN_ERR_PROT_FORM; 526 rx_errors = 1; 527 } 528 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 529 netdev_dbg(dev, "STF_ERR irq\n"); 530 cf->data[2] |= CAN_ERR_PROT_STUFF; 531 rx_errors = 1; 532 } 533 534 priv->can.can_stats.bus_error++; 535 if (rx_errors) 536 dev->stats.rx_errors++; 537 if (tx_errors) 538 dev->stats.tx_errors++; 539} 540 541static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) 542{ 543 struct sk_buff *skb; 544 struct can_frame *cf; 545 546 skb = alloc_can_err_skb(dev, &cf); 547 if (unlikely(!skb)) 548 return 0; 549 550 do_bus_err(dev, cf, reg_esr); 551 netif_receive_skb(skb); 552 553 dev->stats.rx_packets++; 554 dev->stats.rx_bytes += cf->can_dlc; 555 556 return 1; 557} 558 559static void do_state(struct net_device *dev, 560 struct can_frame *cf, enum can_state new_state) 561{ 562 struct flexcan_priv *priv = netdev_priv(dev); 563 struct can_berr_counter bec; 564 565 __flexcan_get_berr_counter(dev, &bec); 566 567 switch (priv->can.state) { 568 case CAN_STATE_ERROR_ACTIVE: 569 /* 570 * from: ERROR_ACTIVE 571 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 572 * => : there was a warning int 573 */ 574 if (new_state >= CAN_STATE_ERROR_WARNING && 575 new_state <= CAN_STATE_BUS_OFF) { 576 netdev_dbg(dev, "Error Warning IRQ\n"); 577 priv->can.can_stats.error_warning++; 578 579 cf->can_id |= CAN_ERR_CRTL; 580 cf->data[1] = (bec.txerr > bec.rxerr) ? 581 CAN_ERR_CRTL_TX_WARNING : 582 CAN_ERR_CRTL_RX_WARNING; 583 } 584 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 585 /* 586 * from: ERROR_ACTIVE, ERROR_WARNING 587 * to : ERROR_PASSIVE, BUS_OFF 588 * => : error passive int 589 */ 590 if (new_state >= CAN_STATE_ERROR_PASSIVE && 591 new_state <= CAN_STATE_BUS_OFF) { 592 netdev_dbg(dev, "Error Passive IRQ\n"); 593 priv->can.can_stats.error_passive++; 594 595 cf->can_id |= CAN_ERR_CRTL; 596 cf->data[1] = (bec.txerr > bec.rxerr) ? 597 CAN_ERR_CRTL_TX_PASSIVE : 598 CAN_ERR_CRTL_RX_PASSIVE; 599 } 600 break; 601 case CAN_STATE_BUS_OFF: 602 netdev_err(dev, "BUG! " 603 "hardware recovered automatically from BUS_OFF\n"); 604 break; 605 default: 606 break; 607 } 608 609 /* process state changes depending on the new state */ 610 switch (new_state) { 611 case CAN_STATE_ERROR_ACTIVE: 612 netdev_dbg(dev, "Error Active\n"); 613 cf->can_id |= CAN_ERR_PROT; 614 cf->data[2] = CAN_ERR_PROT_ACTIVE; 615 break; 616 case CAN_STATE_BUS_OFF: 617 cf->can_id |= CAN_ERR_BUSOFF; 618 can_bus_off(dev); 619 break; 620 default: 621 break; 622 } 623} 624 625static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) 626{ 627 struct flexcan_priv *priv = netdev_priv(dev); 628 struct sk_buff *skb; 629 struct can_frame *cf; 630 enum can_state new_state; 631 int flt; 632 633 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 634 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 635 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | 636 FLEXCAN_ESR_RX_WRN)))) 637 new_state = CAN_STATE_ERROR_ACTIVE; 638 else 639 new_state = CAN_STATE_ERROR_WARNING; 640 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) 641 new_state = CAN_STATE_ERROR_PASSIVE; 642 else 643 new_state = CAN_STATE_BUS_OFF; 644 645 /* state hasn't changed */ 646 if (likely(new_state == priv->can.state)) 647 return 0; 648 649 skb = alloc_can_err_skb(dev, &cf); 650 if (unlikely(!skb)) 651 return 0; 652 653 do_state(dev, cf, new_state); 654 priv->can.state = new_state; 655 netif_receive_skb(skb); 656 657 dev->stats.rx_packets++; 658 dev->stats.rx_bytes += cf->can_dlc; 659 660 return 1; 661} 662 663static void flexcan_read_fifo(const struct net_device *dev, 664 struct can_frame *cf) 665{ 666 const struct flexcan_priv *priv = netdev_priv(dev); 667 struct flexcan_regs __iomem *regs = priv->base; 668 struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; 669 u32 reg_ctrl, reg_id; 670 671 reg_ctrl = flexcan_read(&mb->can_ctrl); 672 reg_id = flexcan_read(&mb->can_id); 673 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 674 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 675 else 676 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; 677 678 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 679 cf->can_id |= CAN_RTR_FLAG; 680 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 681 682 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); 683 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); 684 685 /* mark as read */ 686 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 687 flexcan_read(®s->timer); 688} 689 690static int flexcan_read_frame(struct net_device *dev) 691{ 692 struct net_device_stats *stats = &dev->stats; 693 struct can_frame *cf; 694 struct sk_buff *skb; 695 696 skb = alloc_can_skb(dev, &cf); 697 if (unlikely(!skb)) { 698 stats->rx_dropped++; 699 return 0; 700 } 701 702 flexcan_read_fifo(dev, cf); 703 netif_receive_skb(skb); 704 705 stats->rx_packets++; 706 stats->rx_bytes += cf->can_dlc; 707 708 can_led_event(dev, CAN_LED_EVENT_RX); 709 710 return 1; 711} 712 713static int flexcan_poll(struct napi_struct *napi, int quota) 714{ 715 struct net_device *dev = napi->dev; 716 const struct flexcan_priv *priv = netdev_priv(dev); 717 struct flexcan_regs __iomem *regs = priv->base; 718 u32 reg_iflag1, reg_esr; 719 int work_done = 0; 720 721 /* 722 * The error bits are cleared on read, 723 * use saved value from irq handler. 724 */ 725 reg_esr = flexcan_read(®s->esr) | priv->reg_esr; 726 727 /* handle state changes */ 728 work_done += flexcan_poll_state(dev, reg_esr); 729 730 /* handle RX-FIFO */ 731 reg_iflag1 = flexcan_read(®s->iflag1); 732 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 733 work_done < quota) { 734 work_done += flexcan_read_frame(dev); 735 reg_iflag1 = flexcan_read(®s->iflag1); 736 } 737 738 /* report bus errors */ 739 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) 740 work_done += flexcan_poll_bus_err(dev, reg_esr); 741 742 if (work_done < quota) { 743 napi_complete(napi); 744 /* enable IRQs */ 745 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 746 flexcan_write(priv->reg_ctrl_default, ®s->ctrl); 747 } 748 749 return work_done; 750} 751 752static irqreturn_t flexcan_irq(int irq, void *dev_id) 753{ 754 struct net_device *dev = dev_id; 755 struct net_device_stats *stats = &dev->stats; 756 struct flexcan_priv *priv = netdev_priv(dev); 757 struct flexcan_regs __iomem *regs = priv->base; 758 u32 reg_iflag1, reg_esr; 759 760 reg_iflag1 = flexcan_read(®s->iflag1); 761 reg_esr = flexcan_read(®s->esr); 762 /* ACK all bus error and state change IRQ sources */ 763 if (reg_esr & FLEXCAN_ESR_ALL_INT) 764 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); 765 766 /* 767 * schedule NAPI in case of: 768 * - rx IRQ 769 * - state change IRQ 770 * - bus error IRQ and bus error reporting is activated 771 */ 772 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || 773 (reg_esr & FLEXCAN_ESR_ERR_STATE) || 774 flexcan_has_and_handle_berr(priv, reg_esr)) { 775 /* 776 * The error bits are cleared on read, 777 * save them for later use. 778 */ 779 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 780 flexcan_write(FLEXCAN_IFLAG_DEFAULT & 781 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); 782 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 783 ®s->ctrl); 784 napi_schedule(&priv->napi); 785 } 786 787 /* FIFO overflow */ 788 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 789 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); 790 dev->stats.rx_over_errors++; 791 dev->stats.rx_errors++; 792 } 793 794 /* transmission complete interrupt */ 795 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 796 stats->tx_bytes += can_get_echo_skb(dev, 0); 797 stats->tx_packets++; 798 can_led_event(dev, CAN_LED_EVENT_TX); 799 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); 800 netif_wake_queue(dev); 801 } 802 803 return IRQ_HANDLED; 804} 805 806static void flexcan_set_bittiming(struct net_device *dev) 807{ 808 const struct flexcan_priv *priv = netdev_priv(dev); 809 const struct can_bittiming *bt = &priv->can.bittiming; 810 struct flexcan_regs __iomem *regs = priv->base; 811 u32 reg; 812 813 reg = flexcan_read(®s->ctrl); 814 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 815 FLEXCAN_CTRL_RJW(0x3) | 816 FLEXCAN_CTRL_PSEG1(0x7) | 817 FLEXCAN_CTRL_PSEG2(0x7) | 818 FLEXCAN_CTRL_PROPSEG(0x7) | 819 FLEXCAN_CTRL_LPB | 820 FLEXCAN_CTRL_SMP | 821 FLEXCAN_CTRL_LOM); 822 823 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 824 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 825 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 826 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 827 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 828 829 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 830 reg |= FLEXCAN_CTRL_LPB; 831 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 832 reg |= FLEXCAN_CTRL_LOM; 833 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 834 reg |= FLEXCAN_CTRL_SMP; 835 836 netdev_info(dev, "writing ctrl=0x%08x\n", reg); 837 flexcan_write(reg, ®s->ctrl); 838 839 /* print chip status */ 840 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 841 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 842} 843 844/* 845 * flexcan_chip_start 846 * 847 * this functions is entered with clocks enabled 848 * 849 */ 850static int flexcan_chip_start(struct net_device *dev) 851{ 852 struct flexcan_priv *priv = netdev_priv(dev); 853 struct flexcan_regs __iomem *regs = priv->base; 854 int err; 855 u32 reg_mcr, reg_ctrl, reg_crl2, reg_mecr; 856 857 /* enable module */ 858 err = flexcan_chip_enable(priv); 859 if (err) 860 return err; 861 862 /* soft reset */ 863 err = flexcan_chip_softreset(priv); 864 if (err) 865 goto out_chip_disable; 866 867 flexcan_set_bittiming(dev); 868 869 /* 870 * MCR 871 * 872 * enable freeze 873 * enable fifo 874 * halt now 875 * only supervisor access 876 * enable warning int 877 * choose format C 878 * disable local echo 879 * 880 */ 881 reg_mcr = flexcan_read(®s->mcr); 882 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff); 883 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 884 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 885 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS | 886 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID); 887 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); 888 flexcan_write(reg_mcr, ®s->mcr); 889 890 /* 891 * CTRL 892 * 893 * disable timer sync feature 894 * 895 * disable auto busoff recovery 896 * transmit lowest buffer first 897 * 898 * enable tx and rx warning interrupt 899 * enable bus off interrupt 900 * (== FLEXCAN_CTRL_ERR_STATE) 901 */ 902 reg_ctrl = flexcan_read(®s->ctrl); 903 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 904 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 905 FLEXCAN_CTRL_ERR_STATE; 906 /* 907 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), 908 * on most Flexcan cores, too. Otherwise we don't get 909 * any error warning or passive interrupts. 910 */ 911 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE || 912 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 913 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; 914 915 /* save for later use */ 916 priv->reg_ctrl_default = reg_ctrl; 917 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 918 flexcan_write(reg_ctrl, ®s->ctrl); 919 920 /* Abort any pending TX, mark Mailbox as INACTIVE */ 921 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4), 922 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 923 924 /* acceptance mask/acceptance code (accept everything) */ 925 flexcan_write(0x0, ®s->rxgmask); 926 flexcan_write(0x0, ®s->rx14mask); 927 flexcan_write(0x0, ®s->rx15mask); 928 929 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) 930 flexcan_write(0x0, ®s->rxfgmask); 931 932 /* 933 * On Vybrid, disable memory error detection interrupts 934 * and freeze mode. 935 * This also works around errata e5295 which generates 936 * false positive memory errors and put the device in 937 * freeze mode. 938 */ 939 if (priv->devtype_data->features & FLEXCAN_HAS_MECR_FEATURES) { 940 /* 941 * Follow the protocol as described in "Detection 942 * and Correction of Memory Errors" to write to 943 * MECR register 944 */ 945 reg_crl2 = flexcan_read(®s->crl2); 946 reg_crl2 |= FLEXCAN_CRL2_ECRWRE; 947 flexcan_write(reg_crl2, ®s->crl2); 948 949 reg_mecr = flexcan_read(®s->mecr); 950 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS; 951 flexcan_write(reg_mecr, ®s->mecr); 952 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK | 953 FLEXCAN_MECR_FANCEI_MSK); 954 flexcan_write(reg_mecr, ®s->mecr); 955 } 956 957 err = flexcan_transceiver_enable(priv); 958 if (err) 959 goto out_chip_disable; 960 961 /* synchronize with the can bus */ 962 err = flexcan_chip_unfreeze(priv); 963 if (err) 964 goto out_transceiver_disable; 965 966 priv->can.state = CAN_STATE_ERROR_ACTIVE; 967 968 /* enable FIFO interrupts */ 969 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 970 971 /* print chip status */ 972 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, 973 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 974 975 return 0; 976 977 out_transceiver_disable: 978 flexcan_transceiver_disable(priv); 979 out_chip_disable: 980 flexcan_chip_disable(priv); 981 return err; 982} 983 984/* 985 * flexcan_chip_stop 986 * 987 * this functions is entered with clocks enabled 988 * 989 */ 990static void flexcan_chip_stop(struct net_device *dev) 991{ 992 struct flexcan_priv *priv = netdev_priv(dev); 993 struct flexcan_regs __iomem *regs = priv->base; 994 995 /* freeze + disable module */ 996 flexcan_chip_freeze(priv); 997 flexcan_chip_disable(priv); 998 999 /* Disable all interrupts */ 1000 flexcan_write(0, ®s->imask1); 1001 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 1002 ®s->ctrl); 1003 1004 flexcan_transceiver_disable(priv); 1005 priv->can.state = CAN_STATE_STOPPED; 1006 1007 return; 1008} 1009 1010static int flexcan_open(struct net_device *dev) 1011{ 1012 struct flexcan_priv *priv = netdev_priv(dev); 1013 int err; 1014 1015 err = clk_prepare_enable(priv->clk_ipg); 1016 if (err) 1017 return err; 1018 1019 err = clk_prepare_enable(priv->clk_per); 1020 if (err) 1021 goto out_disable_ipg; 1022 1023 err = open_candev(dev); 1024 if (err) 1025 goto out_disable_per; 1026 1027 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 1028 if (err) 1029 goto out_close; 1030 1031 /* start chip and queuing */ 1032 err = flexcan_chip_start(dev); 1033 if (err) 1034 goto out_free_irq; 1035 1036 can_led_event(dev, CAN_LED_EVENT_OPEN); 1037 1038 napi_enable(&priv->napi); 1039 netif_start_queue(dev); 1040 1041 return 0; 1042 1043 out_free_irq: 1044 free_irq(dev->irq, dev); 1045 out_close: 1046 close_candev(dev); 1047 out_disable_per: 1048 clk_disable_unprepare(priv->clk_per); 1049 out_disable_ipg: 1050 clk_disable_unprepare(priv->clk_ipg); 1051 1052 return err; 1053} 1054 1055static int flexcan_close(struct net_device *dev) 1056{ 1057 struct flexcan_priv *priv = netdev_priv(dev); 1058 1059 netif_stop_queue(dev); 1060 napi_disable(&priv->napi); 1061 flexcan_chip_stop(dev); 1062 1063 free_irq(dev->irq, dev); 1064 clk_disable_unprepare(priv->clk_per); 1065 clk_disable_unprepare(priv->clk_ipg); 1066 1067 close_candev(dev); 1068 1069 can_led_event(dev, CAN_LED_EVENT_STOP); 1070 1071 return 0; 1072} 1073 1074static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 1075{ 1076 int err; 1077 1078 switch (mode) { 1079 case CAN_MODE_START: 1080 err = flexcan_chip_start(dev); 1081 if (err) 1082 return err; 1083 1084 netif_wake_queue(dev); 1085 break; 1086 1087 default: 1088 return -EOPNOTSUPP; 1089 } 1090 1091 return 0; 1092} 1093 1094static const struct net_device_ops flexcan_netdev_ops = { 1095 .ndo_open = flexcan_open, 1096 .ndo_stop = flexcan_close, 1097 .ndo_start_xmit = flexcan_start_xmit, 1098 .ndo_change_mtu = can_change_mtu, 1099}; 1100 1101static int register_flexcandev(struct net_device *dev) 1102{ 1103 struct flexcan_priv *priv = netdev_priv(dev); 1104 struct flexcan_regs __iomem *regs = priv->base; 1105 u32 reg, err; 1106 1107 err = clk_prepare_enable(priv->clk_ipg); 1108 if (err) 1109 return err; 1110 1111 err = clk_prepare_enable(priv->clk_per); 1112 if (err) 1113 goto out_disable_ipg; 1114 1115 /* select "bus clock", chip must be disabled */ 1116 err = flexcan_chip_disable(priv); 1117 if (err) 1118 goto out_disable_per; 1119 reg = flexcan_read(®s->ctrl); 1120 reg |= FLEXCAN_CTRL_CLK_SRC; 1121 flexcan_write(reg, ®s->ctrl); 1122 1123 err = flexcan_chip_enable(priv); 1124 if (err) 1125 goto out_chip_disable; 1126 1127 /* set freeze, halt and activate FIFO, restrict register access */ 1128 reg = flexcan_read(®s->mcr); 1129 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 1130 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 1131 flexcan_write(reg, ®s->mcr); 1132 1133 /* 1134 * Currently we only support newer versions of this core 1135 * featuring a RX FIFO. Older cores found on some Coldfire 1136 * derivates are not yet supported. 1137 */ 1138 reg = flexcan_read(®s->mcr); 1139 if (!(reg & FLEXCAN_MCR_FEN)) { 1140 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); 1141 err = -ENODEV; 1142 goto out_chip_disable; 1143 } 1144 1145 err = register_candev(dev); 1146 1147 /* disable core and turn off clocks */ 1148 out_chip_disable: 1149 flexcan_chip_disable(priv); 1150 out_disable_per: 1151 clk_disable_unprepare(priv->clk_per); 1152 out_disable_ipg: 1153 clk_disable_unprepare(priv->clk_ipg); 1154 1155 return err; 1156} 1157 1158static void unregister_flexcandev(struct net_device *dev) 1159{ 1160 unregister_candev(dev); 1161} 1162 1163static const struct of_device_id flexcan_of_match[] = { 1164 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, 1165 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, 1166 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, 1167 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, }, 1168 { /* sentinel */ }, 1169}; 1170MODULE_DEVICE_TABLE(of, flexcan_of_match); 1171 1172static const struct platform_device_id flexcan_id_table[] = { 1173 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, }, 1174 { /* sentinel */ }, 1175}; 1176MODULE_DEVICE_TABLE(platform, flexcan_id_table); 1177 1178static int flexcan_probe(struct platform_device *pdev) 1179{ 1180 const struct of_device_id *of_id; 1181 const struct flexcan_devtype_data *devtype_data; 1182 struct net_device *dev; 1183 struct flexcan_priv *priv; 1184 struct resource *mem; 1185 struct clk *clk_ipg = NULL, *clk_per = NULL; 1186 void __iomem *base; 1187 int err, irq; 1188 u32 clock_freq = 0; 1189 1190 if (pdev->dev.of_node) 1191 of_property_read_u32(pdev->dev.of_node, 1192 "clock-frequency", &clock_freq); 1193 1194 if (!clock_freq) { 1195 clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1196 if (IS_ERR(clk_ipg)) { 1197 dev_err(&pdev->dev, "no ipg clock defined\n"); 1198 return PTR_ERR(clk_ipg); 1199 } 1200 1201 clk_per = devm_clk_get(&pdev->dev, "per"); 1202 if (IS_ERR(clk_per)) { 1203 dev_err(&pdev->dev, "no per clock defined\n"); 1204 return PTR_ERR(clk_per); 1205 } 1206 clock_freq = clk_get_rate(clk_per); 1207 } 1208 1209 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1210 irq = platform_get_irq(pdev, 0); 1211 if (irq <= 0) 1212 return -ENODEV; 1213 1214 base = devm_ioremap_resource(&pdev->dev, mem); 1215 if (IS_ERR(base)) 1216 return PTR_ERR(base); 1217 1218 of_id = of_match_device(flexcan_of_match, &pdev->dev); 1219 if (of_id) { 1220 devtype_data = of_id->data; 1221 } else if (platform_get_device_id(pdev)->driver_data) { 1222 devtype_data = (struct flexcan_devtype_data *) 1223 platform_get_device_id(pdev)->driver_data; 1224 } else { 1225 return -ENODEV; 1226 } 1227 1228 dev = alloc_candev(sizeof(struct flexcan_priv), 1); 1229 if (!dev) 1230 return -ENOMEM; 1231 1232 dev->netdev_ops = &flexcan_netdev_ops; 1233 dev->irq = irq; 1234 dev->flags |= IFF_ECHO; 1235 1236 priv = netdev_priv(dev); 1237 priv->can.clock.freq = clock_freq; 1238 priv->can.bittiming_const = &flexcan_bittiming_const; 1239 priv->can.do_set_mode = flexcan_set_mode; 1240 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 1241 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1242 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 1243 CAN_CTRLMODE_BERR_REPORTING; 1244 priv->base = base; 1245 priv->dev = dev; 1246 priv->clk_ipg = clk_ipg; 1247 priv->clk_per = clk_per; 1248 priv->pdata = dev_get_platdata(&pdev->dev); 1249 priv->devtype_data = devtype_data; 1250 1251 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); 1252 if (IS_ERR(priv->reg_xceiver)) 1253 priv->reg_xceiver = NULL; 1254 1255 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); 1256 1257 platform_set_drvdata(pdev, dev); 1258 SET_NETDEV_DEV(dev, &pdev->dev); 1259 1260 err = register_flexcandev(dev); 1261 if (err) { 1262 dev_err(&pdev->dev, "registering netdev failed\n"); 1263 goto failed_register; 1264 } 1265 1266 devm_can_led_init(dev); 1267 1268 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1269 priv->base, dev->irq); 1270 1271 return 0; 1272 1273 failed_register: 1274 free_candev(dev); 1275 return err; 1276} 1277 1278static int flexcan_remove(struct platform_device *pdev) 1279{ 1280 struct net_device *dev = platform_get_drvdata(pdev); 1281 struct flexcan_priv *priv = netdev_priv(dev); 1282 1283 unregister_flexcandev(dev); 1284 netif_napi_del(&priv->napi); 1285 free_candev(dev); 1286 1287 return 0; 1288} 1289 1290static int __maybe_unused flexcan_suspend(struct device *device) 1291{ 1292 struct net_device *dev = dev_get_drvdata(device); 1293 struct flexcan_priv *priv = netdev_priv(dev); 1294 int err; 1295 1296 err = flexcan_chip_disable(priv); 1297 if (err) 1298 return err; 1299 1300 if (netif_running(dev)) { 1301 netif_stop_queue(dev); 1302 netif_device_detach(dev); 1303 } 1304 priv->can.state = CAN_STATE_SLEEPING; 1305 1306 return 0; 1307} 1308 1309static int __maybe_unused flexcan_resume(struct device *device) 1310{ 1311 struct net_device *dev = dev_get_drvdata(device); 1312 struct flexcan_priv *priv = netdev_priv(dev); 1313 1314 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1315 if (netif_running(dev)) { 1316 netif_device_attach(dev); 1317 netif_start_queue(dev); 1318 } 1319 return flexcan_chip_enable(priv); 1320} 1321 1322static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume); 1323 1324static struct platform_driver flexcan_driver = { 1325 .driver = { 1326 .name = DRV_NAME, 1327 .owner = THIS_MODULE, 1328 .pm = &flexcan_pm_ops, 1329 .of_match_table = flexcan_of_match, 1330 }, 1331 .probe = flexcan_probe, 1332 .remove = flexcan_remove, 1333 .id_table = flexcan_id_table, 1334}; 1335 1336module_platform_driver(flexcan_driver); 1337 1338MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 1339 "Marc Kleine-Budde <kernel@pengutronix.de>"); 1340MODULE_LICENSE("GPL v2"); 1341MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 1342