flexcan.c revision dda0b3bd1cbb66ee869d589f7d719f703d7c38a1
1/* 2 * flexcan.c - FLEXCAN CAN controller driver 3 * 4 * Copyright (c) 2005-2006 Varma Electronics Oy 5 * Copyright (c) 2009 Sascha Hauer, Pengutronix 6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix 7 * 8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com> 9 * 10 * LICENCE: 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22#include <linux/netdevice.h> 23#include <linux/can.h> 24#include <linux/can/dev.h> 25#include <linux/can/error.h> 26#include <linux/can/platform/flexcan.h> 27#include <linux/clk.h> 28#include <linux/delay.h> 29#include <linux/if_arp.h> 30#include <linux/if_ether.h> 31#include <linux/interrupt.h> 32#include <linux/io.h> 33#include <linux/kernel.h> 34#include <linux/list.h> 35#include <linux/module.h> 36#include <linux/of.h> 37#include <linux/of_device.h> 38#include <linux/platform_device.h> 39#include <linux/pinctrl/consumer.h> 40 41#define DRV_NAME "flexcan" 42 43/* 8 for RX fifo and 2 error handling */ 44#define FLEXCAN_NAPI_WEIGHT (8 + 2) 45 46/* FLEXCAN module configuration register (CANMCR) bits */ 47#define FLEXCAN_MCR_MDIS BIT(31) 48#define FLEXCAN_MCR_FRZ BIT(30) 49#define FLEXCAN_MCR_FEN BIT(29) 50#define FLEXCAN_MCR_HALT BIT(28) 51#define FLEXCAN_MCR_NOT_RDY BIT(27) 52#define FLEXCAN_MCR_WAK_MSK BIT(26) 53#define FLEXCAN_MCR_SOFTRST BIT(25) 54#define FLEXCAN_MCR_FRZ_ACK BIT(24) 55#define FLEXCAN_MCR_SUPV BIT(23) 56#define FLEXCAN_MCR_SLF_WAK BIT(22) 57#define FLEXCAN_MCR_WRN_EN BIT(21) 58#define FLEXCAN_MCR_LPM_ACK BIT(20) 59#define FLEXCAN_MCR_WAK_SRC BIT(19) 60#define FLEXCAN_MCR_DOZE BIT(18) 61#define FLEXCAN_MCR_SRX_DIS BIT(17) 62#define FLEXCAN_MCR_BCC BIT(16) 63#define FLEXCAN_MCR_LPRIO_EN BIT(13) 64#define FLEXCAN_MCR_AEN BIT(12) 65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf) 66#define FLEXCAN_MCR_IDAM_A (0 << 8) 67#define FLEXCAN_MCR_IDAM_B (1 << 8) 68#define FLEXCAN_MCR_IDAM_C (2 << 8) 69#define FLEXCAN_MCR_IDAM_D (3 << 8) 70 71/* FLEXCAN control register (CANCTRL) bits */ 72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 76#define FLEXCAN_CTRL_BOFF_MSK BIT(15) 77#define FLEXCAN_CTRL_ERR_MSK BIT(14) 78#define FLEXCAN_CTRL_CLK_SRC BIT(13) 79#define FLEXCAN_CTRL_LPB BIT(12) 80#define FLEXCAN_CTRL_TWRN_MSK BIT(11) 81#define FLEXCAN_CTRL_RWRN_MSK BIT(10) 82#define FLEXCAN_CTRL_SMP BIT(7) 83#define FLEXCAN_CTRL_BOFF_REC BIT(6) 84#define FLEXCAN_CTRL_TSYN BIT(5) 85#define FLEXCAN_CTRL_LBUF BIT(4) 86#define FLEXCAN_CTRL_LOM BIT(3) 87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 89#define FLEXCAN_CTRL_ERR_STATE \ 90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 91 FLEXCAN_CTRL_BOFF_MSK) 92#define FLEXCAN_CTRL_ERR_ALL \ 93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 94 95/* FLEXCAN error and status register (ESR) bits */ 96#define FLEXCAN_ESR_TWRN_INT BIT(17) 97#define FLEXCAN_ESR_RWRN_INT BIT(16) 98#define FLEXCAN_ESR_BIT1_ERR BIT(15) 99#define FLEXCAN_ESR_BIT0_ERR BIT(14) 100#define FLEXCAN_ESR_ACK_ERR BIT(13) 101#define FLEXCAN_ESR_CRC_ERR BIT(12) 102#define FLEXCAN_ESR_FRM_ERR BIT(11) 103#define FLEXCAN_ESR_STF_ERR BIT(10) 104#define FLEXCAN_ESR_TX_WRN BIT(9) 105#define FLEXCAN_ESR_RX_WRN BIT(8) 106#define FLEXCAN_ESR_IDLE BIT(7) 107#define FLEXCAN_ESR_TXRX BIT(6) 108#define FLEXCAN_EST_FLT_CONF_SHIFT (4) 109#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 110#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 111#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 112#define FLEXCAN_ESR_BOFF_INT BIT(2) 113#define FLEXCAN_ESR_ERR_INT BIT(1) 114#define FLEXCAN_ESR_WAK_INT BIT(0) 115#define FLEXCAN_ESR_ERR_BUS \ 116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 119#define FLEXCAN_ESR_ERR_STATE \ 120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 121#define FLEXCAN_ESR_ERR_ALL \ 122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 123#define FLEXCAN_ESR_ALL_INT \ 124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ 125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) 126 127/* FLEXCAN interrupt flag register (IFLAG) bits */ 128#define FLEXCAN_TX_BUF_ID 8 129#define FLEXCAN_IFLAG_BUF(x) BIT(x) 130#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 131#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 132#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 133#define FLEXCAN_IFLAG_DEFAULT \ 134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ 135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) 136 137/* FLEXCAN message buffers */ 138#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) 139#define FLEXCAN_MB_CNT_SRR BIT(22) 140#define FLEXCAN_MB_CNT_IDE BIT(21) 141#define FLEXCAN_MB_CNT_RTR BIT(20) 142#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 143#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 144 145#define FLEXCAN_MB_CODE_MASK (0xf0ffffff) 146 147/* Structure of the message buffer */ 148struct flexcan_mb { 149 u32 can_ctrl; 150 u32 can_id; 151 u32 data[2]; 152}; 153 154/* Structure of the hardware registers */ 155struct flexcan_regs { 156 u32 mcr; /* 0x00 */ 157 u32 ctrl; /* 0x04 */ 158 u32 timer; /* 0x08 */ 159 u32 _reserved1; /* 0x0c */ 160 u32 rxgmask; /* 0x10 */ 161 u32 rx14mask; /* 0x14 */ 162 u32 rx15mask; /* 0x18 */ 163 u32 ecr; /* 0x1c */ 164 u32 esr; /* 0x20 */ 165 u32 imask2; /* 0x24 */ 166 u32 imask1; /* 0x28 */ 167 u32 iflag2; /* 0x2c */ 168 u32 iflag1; /* 0x30 */ 169 u32 crl2; /* 0x34 */ 170 u32 esr2; /* 0x38 */ 171 u32 imeur; /* 0x3c */ 172 u32 lrfr; /* 0x40 */ 173 u32 crcr; /* 0x44 */ 174 u32 rxfgmask; /* 0x48 */ 175 u32 rxfir; /* 0x4c */ 176 u32 _reserved3[12]; 177 struct flexcan_mb cantxfg[64]; 178}; 179 180struct flexcan_devtype_data { 181 u32 hw_ver; /* hardware controller version */ 182}; 183 184struct flexcan_priv { 185 struct can_priv can; 186 struct net_device *dev; 187 struct napi_struct napi; 188 189 void __iomem *base; 190 u32 reg_esr; 191 u32 reg_ctrl_default; 192 193 struct clk *clk; 194 struct flexcan_platform_data *pdata; 195 const struct flexcan_devtype_data *devtype_data; 196}; 197 198static struct flexcan_devtype_data fsl_p1010_devtype_data = { 199 .hw_ver = 3, 200}; 201 202static struct flexcan_devtype_data fsl_imx6q_devtype_data = { 203 .hw_ver = 10, 204}; 205 206static struct can_bittiming_const flexcan_bittiming_const = { 207 .name = DRV_NAME, 208 .tseg1_min = 4, 209 .tseg1_max = 16, 210 .tseg2_min = 2, 211 .tseg2_max = 8, 212 .sjw_max = 4, 213 .brp_min = 1, 214 .brp_max = 256, 215 .brp_inc = 1, 216}; 217 218/* 219 * Abstract off the read/write for arm versus ppc. 220 */ 221#if defined(__BIG_ENDIAN) 222static inline u32 flexcan_read(void __iomem *addr) 223{ 224 return in_be32(addr); 225} 226 227static inline void flexcan_write(u32 val, void __iomem *addr) 228{ 229 out_be32(addr, val); 230} 231#else 232static inline u32 flexcan_read(void __iomem *addr) 233{ 234 return readl(addr); 235} 236 237static inline void flexcan_write(u32 val, void __iomem *addr) 238{ 239 writel(val, addr); 240} 241#endif 242 243/* 244 * Swtich transceiver on or off 245 */ 246static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on) 247{ 248 if (priv->pdata && priv->pdata->transceiver_switch) 249 priv->pdata->transceiver_switch(on); 250} 251 252static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, 253 u32 reg_esr) 254{ 255 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 256 (reg_esr & FLEXCAN_ESR_ERR_BUS); 257} 258 259static inline void flexcan_chip_enable(struct flexcan_priv *priv) 260{ 261 struct flexcan_regs __iomem *regs = priv->base; 262 u32 reg; 263 264 reg = flexcan_read(®s->mcr); 265 reg &= ~FLEXCAN_MCR_MDIS; 266 flexcan_write(reg, ®s->mcr); 267 268 udelay(10); 269} 270 271static inline void flexcan_chip_disable(struct flexcan_priv *priv) 272{ 273 struct flexcan_regs __iomem *regs = priv->base; 274 u32 reg; 275 276 reg = flexcan_read(®s->mcr); 277 reg |= FLEXCAN_MCR_MDIS; 278 flexcan_write(reg, ®s->mcr); 279} 280 281static int flexcan_get_berr_counter(const struct net_device *dev, 282 struct can_berr_counter *bec) 283{ 284 const struct flexcan_priv *priv = netdev_priv(dev); 285 struct flexcan_regs __iomem *regs = priv->base; 286 u32 reg = flexcan_read(®s->ecr); 287 288 bec->txerr = (reg >> 0) & 0xff; 289 bec->rxerr = (reg >> 8) & 0xff; 290 291 return 0; 292} 293 294static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 295{ 296 const struct flexcan_priv *priv = netdev_priv(dev); 297 struct flexcan_regs __iomem *regs = priv->base; 298 struct can_frame *cf = (struct can_frame *)skb->data; 299 u32 can_id; 300 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); 301 302 if (can_dropped_invalid_skb(dev, skb)) 303 return NETDEV_TX_OK; 304 305 netif_stop_queue(dev); 306 307 if (cf->can_id & CAN_EFF_FLAG) { 308 can_id = cf->can_id & CAN_EFF_MASK; 309 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 310 } else { 311 can_id = (cf->can_id & CAN_SFF_MASK) << 18; 312 } 313 314 if (cf->can_id & CAN_RTR_FLAG) 315 ctrl |= FLEXCAN_MB_CNT_RTR; 316 317 if (cf->can_dlc > 0) { 318 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 319 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 320 } 321 if (cf->can_dlc > 3) { 322 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 323 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 324 } 325 326 can_put_echo_skb(skb, dev, 0); 327 328 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 329 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 330 331 return NETDEV_TX_OK; 332} 333 334static void do_bus_err(struct net_device *dev, 335 struct can_frame *cf, u32 reg_esr) 336{ 337 struct flexcan_priv *priv = netdev_priv(dev); 338 int rx_errors = 0, tx_errors = 0; 339 340 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 341 342 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 343 netdev_dbg(dev, "BIT1_ERR irq\n"); 344 cf->data[2] |= CAN_ERR_PROT_BIT1; 345 tx_errors = 1; 346 } 347 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 348 netdev_dbg(dev, "BIT0_ERR irq\n"); 349 cf->data[2] |= CAN_ERR_PROT_BIT0; 350 tx_errors = 1; 351 } 352 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 353 netdev_dbg(dev, "ACK_ERR irq\n"); 354 cf->can_id |= CAN_ERR_ACK; 355 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 356 tx_errors = 1; 357 } 358 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 359 netdev_dbg(dev, "CRC_ERR irq\n"); 360 cf->data[2] |= CAN_ERR_PROT_BIT; 361 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 362 rx_errors = 1; 363 } 364 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 365 netdev_dbg(dev, "FRM_ERR irq\n"); 366 cf->data[2] |= CAN_ERR_PROT_FORM; 367 rx_errors = 1; 368 } 369 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 370 netdev_dbg(dev, "STF_ERR irq\n"); 371 cf->data[2] |= CAN_ERR_PROT_STUFF; 372 rx_errors = 1; 373 } 374 375 priv->can.can_stats.bus_error++; 376 if (rx_errors) 377 dev->stats.rx_errors++; 378 if (tx_errors) 379 dev->stats.tx_errors++; 380} 381 382static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) 383{ 384 struct sk_buff *skb; 385 struct can_frame *cf; 386 387 skb = alloc_can_err_skb(dev, &cf); 388 if (unlikely(!skb)) 389 return 0; 390 391 do_bus_err(dev, cf, reg_esr); 392 netif_receive_skb(skb); 393 394 dev->stats.rx_packets++; 395 dev->stats.rx_bytes += cf->can_dlc; 396 397 return 1; 398} 399 400static void do_state(struct net_device *dev, 401 struct can_frame *cf, enum can_state new_state) 402{ 403 struct flexcan_priv *priv = netdev_priv(dev); 404 struct can_berr_counter bec; 405 406 flexcan_get_berr_counter(dev, &bec); 407 408 switch (priv->can.state) { 409 case CAN_STATE_ERROR_ACTIVE: 410 /* 411 * from: ERROR_ACTIVE 412 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 413 * => : there was a warning int 414 */ 415 if (new_state >= CAN_STATE_ERROR_WARNING && 416 new_state <= CAN_STATE_BUS_OFF) { 417 netdev_dbg(dev, "Error Warning IRQ\n"); 418 priv->can.can_stats.error_warning++; 419 420 cf->can_id |= CAN_ERR_CRTL; 421 cf->data[1] = (bec.txerr > bec.rxerr) ? 422 CAN_ERR_CRTL_TX_WARNING : 423 CAN_ERR_CRTL_RX_WARNING; 424 } 425 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 426 /* 427 * from: ERROR_ACTIVE, ERROR_WARNING 428 * to : ERROR_PASSIVE, BUS_OFF 429 * => : error passive int 430 */ 431 if (new_state >= CAN_STATE_ERROR_PASSIVE && 432 new_state <= CAN_STATE_BUS_OFF) { 433 netdev_dbg(dev, "Error Passive IRQ\n"); 434 priv->can.can_stats.error_passive++; 435 436 cf->can_id |= CAN_ERR_CRTL; 437 cf->data[1] = (bec.txerr > bec.rxerr) ? 438 CAN_ERR_CRTL_TX_PASSIVE : 439 CAN_ERR_CRTL_RX_PASSIVE; 440 } 441 break; 442 case CAN_STATE_BUS_OFF: 443 netdev_err(dev, "BUG! " 444 "hardware recovered automatically from BUS_OFF\n"); 445 break; 446 default: 447 break; 448 } 449 450 /* process state changes depending on the new state */ 451 switch (new_state) { 452 case CAN_STATE_ERROR_ACTIVE: 453 netdev_dbg(dev, "Error Active\n"); 454 cf->can_id |= CAN_ERR_PROT; 455 cf->data[2] = CAN_ERR_PROT_ACTIVE; 456 break; 457 case CAN_STATE_BUS_OFF: 458 cf->can_id |= CAN_ERR_BUSOFF; 459 can_bus_off(dev); 460 break; 461 default: 462 break; 463 } 464} 465 466static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) 467{ 468 struct flexcan_priv *priv = netdev_priv(dev); 469 struct sk_buff *skb; 470 struct can_frame *cf; 471 enum can_state new_state; 472 int flt; 473 474 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 475 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 476 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | 477 FLEXCAN_ESR_RX_WRN)))) 478 new_state = CAN_STATE_ERROR_ACTIVE; 479 else 480 new_state = CAN_STATE_ERROR_WARNING; 481 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) 482 new_state = CAN_STATE_ERROR_PASSIVE; 483 else 484 new_state = CAN_STATE_BUS_OFF; 485 486 /* state hasn't changed */ 487 if (likely(new_state == priv->can.state)) 488 return 0; 489 490 skb = alloc_can_err_skb(dev, &cf); 491 if (unlikely(!skb)) 492 return 0; 493 494 do_state(dev, cf, new_state); 495 priv->can.state = new_state; 496 netif_receive_skb(skb); 497 498 dev->stats.rx_packets++; 499 dev->stats.rx_bytes += cf->can_dlc; 500 501 return 1; 502} 503 504static void flexcan_read_fifo(const struct net_device *dev, 505 struct can_frame *cf) 506{ 507 const struct flexcan_priv *priv = netdev_priv(dev); 508 struct flexcan_regs __iomem *regs = priv->base; 509 struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; 510 u32 reg_ctrl, reg_id; 511 512 reg_ctrl = flexcan_read(&mb->can_ctrl); 513 reg_id = flexcan_read(&mb->can_id); 514 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 515 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 516 else 517 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; 518 519 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 520 cf->can_id |= CAN_RTR_FLAG; 521 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 522 523 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); 524 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); 525 526 /* mark as read */ 527 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 528 flexcan_read(®s->timer); 529} 530 531static int flexcan_read_frame(struct net_device *dev) 532{ 533 struct net_device_stats *stats = &dev->stats; 534 struct can_frame *cf; 535 struct sk_buff *skb; 536 537 skb = alloc_can_skb(dev, &cf); 538 if (unlikely(!skb)) { 539 stats->rx_dropped++; 540 return 0; 541 } 542 543 flexcan_read_fifo(dev, cf); 544 netif_receive_skb(skb); 545 546 stats->rx_packets++; 547 stats->rx_bytes += cf->can_dlc; 548 549 return 1; 550} 551 552static int flexcan_poll(struct napi_struct *napi, int quota) 553{ 554 struct net_device *dev = napi->dev; 555 const struct flexcan_priv *priv = netdev_priv(dev); 556 struct flexcan_regs __iomem *regs = priv->base; 557 u32 reg_iflag1, reg_esr; 558 int work_done = 0; 559 560 /* 561 * The error bits are cleared on read, 562 * use saved value from irq handler. 563 */ 564 reg_esr = flexcan_read(®s->esr) | priv->reg_esr; 565 566 /* handle state changes */ 567 work_done += flexcan_poll_state(dev, reg_esr); 568 569 /* handle RX-FIFO */ 570 reg_iflag1 = flexcan_read(®s->iflag1); 571 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 572 work_done < quota) { 573 work_done += flexcan_read_frame(dev); 574 reg_iflag1 = flexcan_read(®s->iflag1); 575 } 576 577 /* report bus errors */ 578 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) 579 work_done += flexcan_poll_bus_err(dev, reg_esr); 580 581 if (work_done < quota) { 582 napi_complete(napi); 583 /* enable IRQs */ 584 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 585 flexcan_write(priv->reg_ctrl_default, ®s->ctrl); 586 } 587 588 return work_done; 589} 590 591static irqreturn_t flexcan_irq(int irq, void *dev_id) 592{ 593 struct net_device *dev = dev_id; 594 struct net_device_stats *stats = &dev->stats; 595 struct flexcan_priv *priv = netdev_priv(dev); 596 struct flexcan_regs __iomem *regs = priv->base; 597 u32 reg_iflag1, reg_esr; 598 599 reg_iflag1 = flexcan_read(®s->iflag1); 600 reg_esr = flexcan_read(®s->esr); 601 /* ACK all bus error and state change IRQ sources */ 602 if (reg_esr & FLEXCAN_ESR_ALL_INT) 603 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); 604 605 /* 606 * schedule NAPI in case of: 607 * - rx IRQ 608 * - state change IRQ 609 * - bus error IRQ and bus error reporting is activated 610 */ 611 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || 612 (reg_esr & FLEXCAN_ESR_ERR_STATE) || 613 flexcan_has_and_handle_berr(priv, reg_esr)) { 614 /* 615 * The error bits are cleared on read, 616 * save them for later use. 617 */ 618 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 619 flexcan_write(FLEXCAN_IFLAG_DEFAULT & 620 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); 621 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 622 ®s->ctrl); 623 napi_schedule(&priv->napi); 624 } 625 626 /* FIFO overflow */ 627 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 628 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); 629 dev->stats.rx_over_errors++; 630 dev->stats.rx_errors++; 631 } 632 633 /* transmission complete interrupt */ 634 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 635 stats->tx_bytes += can_get_echo_skb(dev, 0); 636 stats->tx_packets++; 637 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); 638 netif_wake_queue(dev); 639 } 640 641 return IRQ_HANDLED; 642} 643 644static void flexcan_set_bittiming(struct net_device *dev) 645{ 646 const struct flexcan_priv *priv = netdev_priv(dev); 647 const struct can_bittiming *bt = &priv->can.bittiming; 648 struct flexcan_regs __iomem *regs = priv->base; 649 u32 reg; 650 651 reg = flexcan_read(®s->ctrl); 652 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 653 FLEXCAN_CTRL_RJW(0x3) | 654 FLEXCAN_CTRL_PSEG1(0x7) | 655 FLEXCAN_CTRL_PSEG2(0x7) | 656 FLEXCAN_CTRL_PROPSEG(0x7) | 657 FLEXCAN_CTRL_LPB | 658 FLEXCAN_CTRL_SMP | 659 FLEXCAN_CTRL_LOM); 660 661 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 662 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 663 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 664 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 665 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 666 667 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 668 reg |= FLEXCAN_CTRL_LPB; 669 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 670 reg |= FLEXCAN_CTRL_LOM; 671 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 672 reg |= FLEXCAN_CTRL_SMP; 673 674 netdev_info(dev, "writing ctrl=0x%08x\n", reg); 675 flexcan_write(reg, ®s->ctrl); 676 677 /* print chip status */ 678 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 679 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 680} 681 682/* 683 * flexcan_chip_start 684 * 685 * this functions is entered with clocks enabled 686 * 687 */ 688static int flexcan_chip_start(struct net_device *dev) 689{ 690 struct flexcan_priv *priv = netdev_priv(dev); 691 struct flexcan_regs __iomem *regs = priv->base; 692 unsigned int i; 693 int err; 694 u32 reg_mcr, reg_ctrl; 695 696 /* enable module */ 697 flexcan_chip_enable(priv); 698 699 /* soft reset */ 700 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 701 udelay(10); 702 703 reg_mcr = flexcan_read(®s->mcr); 704 if (reg_mcr & FLEXCAN_MCR_SOFTRST) { 705 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n", 706 reg_mcr); 707 err = -ENODEV; 708 goto out; 709 } 710 711 flexcan_set_bittiming(dev); 712 713 /* 714 * MCR 715 * 716 * enable freeze 717 * enable fifo 718 * halt now 719 * only supervisor access 720 * enable warning int 721 * choose format C 722 * disable local echo 723 * 724 */ 725 reg_mcr = flexcan_read(®s->mcr); 726 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 727 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 728 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS; 729 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); 730 flexcan_write(reg_mcr, ®s->mcr); 731 732 /* 733 * CTRL 734 * 735 * disable timer sync feature 736 * 737 * disable auto busoff recovery 738 * transmit lowest buffer first 739 * 740 * enable tx and rx warning interrupt 741 * enable bus off interrupt 742 * (== FLEXCAN_CTRL_ERR_STATE) 743 * 744 * _note_: we enable the "error interrupt" 745 * (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any 746 * warning or bus passive interrupts. 747 */ 748 reg_ctrl = flexcan_read(®s->ctrl); 749 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 750 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 751 FLEXCAN_CTRL_ERR_STATE | FLEXCAN_CTRL_ERR_MSK; 752 753 /* save for later use */ 754 priv->reg_ctrl_default = reg_ctrl; 755 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 756 flexcan_write(reg_ctrl, ®s->ctrl); 757 758 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) { 759 flexcan_write(0, ®s->cantxfg[i].can_ctrl); 760 flexcan_write(0, ®s->cantxfg[i].can_id); 761 flexcan_write(0, ®s->cantxfg[i].data[0]); 762 flexcan_write(0, ®s->cantxfg[i].data[1]); 763 764 /* put MB into rx queue */ 765 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4), 766 ®s->cantxfg[i].can_ctrl); 767 } 768 769 /* acceptance mask/acceptance code (accept everything) */ 770 flexcan_write(0x0, ®s->rxgmask); 771 flexcan_write(0x0, ®s->rx14mask); 772 flexcan_write(0x0, ®s->rx15mask); 773 774 if (priv->devtype_data->hw_ver >= 10) 775 flexcan_write(0x0, ®s->rxfgmask); 776 777 flexcan_transceiver_switch(priv, 1); 778 779 /* synchronize with the can bus */ 780 reg_mcr = flexcan_read(®s->mcr); 781 reg_mcr &= ~FLEXCAN_MCR_HALT; 782 flexcan_write(reg_mcr, ®s->mcr); 783 784 priv->can.state = CAN_STATE_ERROR_ACTIVE; 785 786 /* enable FIFO interrupts */ 787 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 788 789 /* print chip status */ 790 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, 791 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 792 793 return 0; 794 795 out: 796 flexcan_chip_disable(priv); 797 return err; 798} 799 800/* 801 * flexcan_chip_stop 802 * 803 * this functions is entered with clocks enabled 804 * 805 */ 806static void flexcan_chip_stop(struct net_device *dev) 807{ 808 struct flexcan_priv *priv = netdev_priv(dev); 809 struct flexcan_regs __iomem *regs = priv->base; 810 u32 reg; 811 812 /* Disable all interrupts */ 813 flexcan_write(0, ®s->imask1); 814 815 /* Disable + halt module */ 816 reg = flexcan_read(®s->mcr); 817 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT; 818 flexcan_write(reg, ®s->mcr); 819 820 flexcan_transceiver_switch(priv, 0); 821 priv->can.state = CAN_STATE_STOPPED; 822 823 return; 824} 825 826static int flexcan_open(struct net_device *dev) 827{ 828 struct flexcan_priv *priv = netdev_priv(dev); 829 int err; 830 831 clk_prepare_enable(priv->clk); 832 833 err = open_candev(dev); 834 if (err) 835 goto out; 836 837 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 838 if (err) 839 goto out_close; 840 841 /* start chip and queuing */ 842 err = flexcan_chip_start(dev); 843 if (err) 844 goto out_close; 845 napi_enable(&priv->napi); 846 netif_start_queue(dev); 847 848 return 0; 849 850 out_close: 851 close_candev(dev); 852 out: 853 clk_disable_unprepare(priv->clk); 854 855 return err; 856} 857 858static int flexcan_close(struct net_device *dev) 859{ 860 struct flexcan_priv *priv = netdev_priv(dev); 861 862 netif_stop_queue(dev); 863 napi_disable(&priv->napi); 864 flexcan_chip_stop(dev); 865 866 free_irq(dev->irq, dev); 867 clk_disable_unprepare(priv->clk); 868 869 close_candev(dev); 870 871 return 0; 872} 873 874static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 875{ 876 int err; 877 878 switch (mode) { 879 case CAN_MODE_START: 880 err = flexcan_chip_start(dev); 881 if (err) 882 return err; 883 884 netif_wake_queue(dev); 885 break; 886 887 default: 888 return -EOPNOTSUPP; 889 } 890 891 return 0; 892} 893 894static const struct net_device_ops flexcan_netdev_ops = { 895 .ndo_open = flexcan_open, 896 .ndo_stop = flexcan_close, 897 .ndo_start_xmit = flexcan_start_xmit, 898}; 899 900static int __devinit register_flexcandev(struct net_device *dev) 901{ 902 struct flexcan_priv *priv = netdev_priv(dev); 903 struct flexcan_regs __iomem *regs = priv->base; 904 u32 reg, err; 905 906 clk_prepare_enable(priv->clk); 907 908 /* select "bus clock", chip must be disabled */ 909 flexcan_chip_disable(priv); 910 reg = flexcan_read(®s->ctrl); 911 reg |= FLEXCAN_CTRL_CLK_SRC; 912 flexcan_write(reg, ®s->ctrl); 913 914 flexcan_chip_enable(priv); 915 916 /* set freeze, halt and activate FIFO, restrict register access */ 917 reg = flexcan_read(®s->mcr); 918 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 919 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 920 flexcan_write(reg, ®s->mcr); 921 922 /* 923 * Currently we only support newer versions of this core 924 * featuring a RX FIFO. Older cores found on some Coldfire 925 * derivates are not yet supported. 926 */ 927 reg = flexcan_read(®s->mcr); 928 if (!(reg & FLEXCAN_MCR_FEN)) { 929 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); 930 err = -ENODEV; 931 goto out; 932 } 933 934 err = register_candev(dev); 935 936 out: 937 /* disable core and turn off clocks */ 938 flexcan_chip_disable(priv); 939 clk_disable_unprepare(priv->clk); 940 941 return err; 942} 943 944static void __devexit unregister_flexcandev(struct net_device *dev) 945{ 946 unregister_candev(dev); 947} 948 949static const struct of_device_id flexcan_of_match[] = { 950 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, 951 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, 952 { /* sentinel */ }, 953}; 954 955static const struct platform_device_id flexcan_id_table[] = { 956 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, }, 957 { /* sentinel */ }, 958}; 959 960static int __devinit flexcan_probe(struct platform_device *pdev) 961{ 962 const struct of_device_id *of_id; 963 const struct flexcan_devtype_data *devtype_data; 964 struct net_device *dev; 965 struct flexcan_priv *priv; 966 struct resource *mem; 967 struct clk *clk = NULL; 968 struct pinctrl *pinctrl; 969 void __iomem *base; 970 resource_size_t mem_size; 971 int err, irq; 972 u32 clock_freq = 0; 973 974 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 975 if (IS_ERR(pinctrl)) 976 return PTR_ERR(pinctrl); 977 978 if (pdev->dev.of_node) 979 of_property_read_u32(pdev->dev.of_node, 980 "clock-frequency", &clock_freq); 981 982 if (!clock_freq) { 983 clk = clk_get(&pdev->dev, NULL); 984 if (IS_ERR(clk)) { 985 dev_err(&pdev->dev, "no clock defined\n"); 986 err = PTR_ERR(clk); 987 goto failed_clock; 988 } 989 clock_freq = clk_get_rate(clk); 990 } 991 992 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 993 irq = platform_get_irq(pdev, 0); 994 if (!mem || irq <= 0) { 995 err = -ENODEV; 996 goto failed_get; 997 } 998 999 mem_size = resource_size(mem); 1000 if (!request_mem_region(mem->start, mem_size, pdev->name)) { 1001 err = -EBUSY; 1002 goto failed_get; 1003 } 1004 1005 base = ioremap(mem->start, mem_size); 1006 if (!base) { 1007 err = -ENOMEM; 1008 goto failed_map; 1009 } 1010 1011 dev = alloc_candev(sizeof(struct flexcan_priv), 1); 1012 if (!dev) { 1013 err = -ENOMEM; 1014 goto failed_alloc; 1015 } 1016 1017 of_id = of_match_device(flexcan_of_match, &pdev->dev); 1018 if (of_id) { 1019 devtype_data = of_id->data; 1020 } else if (pdev->id_entry->driver_data) { 1021 devtype_data = (struct flexcan_devtype_data *) 1022 pdev->id_entry->driver_data; 1023 } else { 1024 err = -ENODEV; 1025 goto failed_devtype; 1026 } 1027 1028 dev->netdev_ops = &flexcan_netdev_ops; 1029 dev->irq = irq; 1030 dev->flags |= IFF_ECHO; 1031 1032 priv = netdev_priv(dev); 1033 priv->can.clock.freq = clock_freq; 1034 priv->can.bittiming_const = &flexcan_bittiming_const; 1035 priv->can.do_set_mode = flexcan_set_mode; 1036 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 1037 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1038 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 1039 CAN_CTRLMODE_BERR_REPORTING; 1040 priv->base = base; 1041 priv->dev = dev; 1042 priv->clk = clk; 1043 priv->pdata = pdev->dev.platform_data; 1044 priv->devtype_data = devtype_data; 1045 1046 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); 1047 1048 dev_set_drvdata(&pdev->dev, dev); 1049 SET_NETDEV_DEV(dev, &pdev->dev); 1050 1051 err = register_flexcandev(dev); 1052 if (err) { 1053 dev_err(&pdev->dev, "registering netdev failed\n"); 1054 goto failed_register; 1055 } 1056 1057 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1058 priv->base, dev->irq); 1059 1060 return 0; 1061 1062 failed_register: 1063 failed_devtype: 1064 free_candev(dev); 1065 failed_alloc: 1066 iounmap(base); 1067 failed_map: 1068 release_mem_region(mem->start, mem_size); 1069 failed_get: 1070 if (clk) 1071 clk_put(clk); 1072 failed_clock: 1073 return err; 1074} 1075 1076static int __devexit flexcan_remove(struct platform_device *pdev) 1077{ 1078 struct net_device *dev = platform_get_drvdata(pdev); 1079 struct flexcan_priv *priv = netdev_priv(dev); 1080 struct resource *mem; 1081 1082 unregister_flexcandev(dev); 1083 platform_set_drvdata(pdev, NULL); 1084 iounmap(priv->base); 1085 1086 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1087 release_mem_region(mem->start, resource_size(mem)); 1088 1089 if (priv->clk) 1090 clk_put(priv->clk); 1091 1092 free_candev(dev); 1093 1094 return 0; 1095} 1096 1097#ifdef CONFIG_PM 1098static int flexcan_suspend(struct platform_device *pdev, pm_message_t state) 1099{ 1100 struct net_device *dev = platform_get_drvdata(pdev); 1101 struct flexcan_priv *priv = netdev_priv(dev); 1102 1103 flexcan_chip_disable(priv); 1104 1105 if (netif_running(dev)) { 1106 netif_stop_queue(dev); 1107 netif_device_detach(dev); 1108 } 1109 priv->can.state = CAN_STATE_SLEEPING; 1110 1111 return 0; 1112} 1113 1114static int flexcan_resume(struct platform_device *pdev) 1115{ 1116 struct net_device *dev = platform_get_drvdata(pdev); 1117 struct flexcan_priv *priv = netdev_priv(dev); 1118 1119 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1120 if (netif_running(dev)) { 1121 netif_device_attach(dev); 1122 netif_start_queue(dev); 1123 } 1124 flexcan_chip_enable(priv); 1125 1126 return 0; 1127} 1128#else 1129#define flexcan_suspend NULL 1130#define flexcan_resume NULL 1131#endif 1132 1133static struct platform_driver flexcan_driver = { 1134 .driver = { 1135 .name = DRV_NAME, 1136 .owner = THIS_MODULE, 1137 .of_match_table = flexcan_of_match, 1138 }, 1139 .probe = flexcan_probe, 1140 .remove = __devexit_p(flexcan_remove), 1141 .suspend = flexcan_suspend, 1142 .resume = flexcan_resume, 1143 .id_table = flexcan_id_table, 1144}; 1145 1146module_platform_driver(flexcan_driver); 1147 1148MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 1149 "Marc Kleine-Budde <kernel@pengutronix.de>"); 1150MODULE_LICENSE("GPL v2"); 1151MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 1152