flexcan.c revision ec56acfef2af184ca485ffeba16adbd56c110c94
1/* 2 * flexcan.c - FLEXCAN CAN controller driver 3 * 4 * Copyright (c) 2005-2006 Varma Electronics Oy 5 * Copyright (c) 2009 Sascha Hauer, Pengutronix 6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix 7 * 8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com> 9 * 10 * LICENCE: 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22#include <linux/netdevice.h> 23#include <linux/can.h> 24#include <linux/can/dev.h> 25#include <linux/can/error.h> 26#include <linux/can/led.h> 27#include <linux/clk.h> 28#include <linux/delay.h> 29#include <linux/if_arp.h> 30#include <linux/if_ether.h> 31#include <linux/interrupt.h> 32#include <linux/io.h> 33#include <linux/kernel.h> 34#include <linux/list.h> 35#include <linux/module.h> 36#include <linux/of.h> 37#include <linux/of_device.h> 38#include <linux/platform_device.h> 39#include <linux/regulator/consumer.h> 40 41#define DRV_NAME "flexcan" 42 43/* 8 for RX fifo and 2 error handling */ 44#define FLEXCAN_NAPI_WEIGHT (8 + 2) 45 46/* FLEXCAN module configuration register (CANMCR) bits */ 47#define FLEXCAN_MCR_MDIS BIT(31) 48#define FLEXCAN_MCR_FRZ BIT(30) 49#define FLEXCAN_MCR_FEN BIT(29) 50#define FLEXCAN_MCR_HALT BIT(28) 51#define FLEXCAN_MCR_NOT_RDY BIT(27) 52#define FLEXCAN_MCR_WAK_MSK BIT(26) 53#define FLEXCAN_MCR_SOFTRST BIT(25) 54#define FLEXCAN_MCR_FRZ_ACK BIT(24) 55#define FLEXCAN_MCR_SUPV BIT(23) 56#define FLEXCAN_MCR_SLF_WAK BIT(22) 57#define FLEXCAN_MCR_WRN_EN BIT(21) 58#define FLEXCAN_MCR_LPM_ACK BIT(20) 59#define FLEXCAN_MCR_WAK_SRC BIT(19) 60#define FLEXCAN_MCR_DOZE BIT(18) 61#define FLEXCAN_MCR_SRX_DIS BIT(17) 62#define FLEXCAN_MCR_BCC BIT(16) 63#define FLEXCAN_MCR_LPRIO_EN BIT(13) 64#define FLEXCAN_MCR_AEN BIT(12) 65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f) 66#define FLEXCAN_MCR_IDAM_A (0 << 8) 67#define FLEXCAN_MCR_IDAM_B (1 << 8) 68#define FLEXCAN_MCR_IDAM_C (2 << 8) 69#define FLEXCAN_MCR_IDAM_D (3 << 8) 70 71/* FLEXCAN control register (CANCTRL) bits */ 72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 76#define FLEXCAN_CTRL_BOFF_MSK BIT(15) 77#define FLEXCAN_CTRL_ERR_MSK BIT(14) 78#define FLEXCAN_CTRL_CLK_SRC BIT(13) 79#define FLEXCAN_CTRL_LPB BIT(12) 80#define FLEXCAN_CTRL_TWRN_MSK BIT(11) 81#define FLEXCAN_CTRL_RWRN_MSK BIT(10) 82#define FLEXCAN_CTRL_SMP BIT(7) 83#define FLEXCAN_CTRL_BOFF_REC BIT(6) 84#define FLEXCAN_CTRL_TSYN BIT(5) 85#define FLEXCAN_CTRL_LBUF BIT(4) 86#define FLEXCAN_CTRL_LOM BIT(3) 87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 89#define FLEXCAN_CTRL_ERR_STATE \ 90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 91 FLEXCAN_CTRL_BOFF_MSK) 92#define FLEXCAN_CTRL_ERR_ALL \ 93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 94 95/* FLEXCAN error and status register (ESR) bits */ 96#define FLEXCAN_ESR_TWRN_INT BIT(17) 97#define FLEXCAN_ESR_RWRN_INT BIT(16) 98#define FLEXCAN_ESR_BIT1_ERR BIT(15) 99#define FLEXCAN_ESR_BIT0_ERR BIT(14) 100#define FLEXCAN_ESR_ACK_ERR BIT(13) 101#define FLEXCAN_ESR_CRC_ERR BIT(12) 102#define FLEXCAN_ESR_FRM_ERR BIT(11) 103#define FLEXCAN_ESR_STF_ERR BIT(10) 104#define FLEXCAN_ESR_TX_WRN BIT(9) 105#define FLEXCAN_ESR_RX_WRN BIT(8) 106#define FLEXCAN_ESR_IDLE BIT(7) 107#define FLEXCAN_ESR_TXRX BIT(6) 108#define FLEXCAN_EST_FLT_CONF_SHIFT (4) 109#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 110#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 111#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 112#define FLEXCAN_ESR_BOFF_INT BIT(2) 113#define FLEXCAN_ESR_ERR_INT BIT(1) 114#define FLEXCAN_ESR_WAK_INT BIT(0) 115#define FLEXCAN_ESR_ERR_BUS \ 116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 119#define FLEXCAN_ESR_ERR_STATE \ 120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 121#define FLEXCAN_ESR_ERR_ALL \ 122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 123#define FLEXCAN_ESR_ALL_INT \ 124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ 125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) 126 127/* FLEXCAN interrupt flag register (IFLAG) bits */ 128#define FLEXCAN_TX_BUF_ID 8 129#define FLEXCAN_IFLAG_BUF(x) BIT(x) 130#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 131#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 132#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 133#define FLEXCAN_IFLAG_DEFAULT \ 134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ 135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) 136 137/* FLEXCAN message buffers */ 138#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) 139#define FLEXCAN_MB_CNT_SRR BIT(22) 140#define FLEXCAN_MB_CNT_IDE BIT(21) 141#define FLEXCAN_MB_CNT_RTR BIT(20) 142#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 143#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 144 145#define FLEXCAN_MB_CODE_MASK (0xf0ffffff) 146 147#define FLEXCAN_TIMEOUT_US (50) 148 149/* 150 * FLEXCAN hardware feature flags 151 * 152 * Below is some version info we got: 153 * SOC Version IP-Version Glitch- [TR]WRN_INT 154 * Filter? connected? 155 * MX25 FlexCAN2 03.00.00.00 no no 156 * MX28 FlexCAN2 03.00.04.00 yes yes 157 * MX35 FlexCAN2 03.00.00.00 no no 158 * MX53 FlexCAN2 03.00.00.00 yes no 159 * MX6s FlexCAN3 10.00.12.00 yes yes 160 * 161 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected. 162 */ 163#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */ 164#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */ 165 166/* Structure of the message buffer */ 167struct flexcan_mb { 168 u32 can_ctrl; 169 u32 can_id; 170 u32 data[2]; 171}; 172 173/* Structure of the hardware registers */ 174struct flexcan_regs { 175 u32 mcr; /* 0x00 */ 176 u32 ctrl; /* 0x04 */ 177 u32 timer; /* 0x08 */ 178 u32 _reserved1; /* 0x0c */ 179 u32 rxgmask; /* 0x10 */ 180 u32 rx14mask; /* 0x14 */ 181 u32 rx15mask; /* 0x18 */ 182 u32 ecr; /* 0x1c */ 183 u32 esr; /* 0x20 */ 184 u32 imask2; /* 0x24 */ 185 u32 imask1; /* 0x28 */ 186 u32 iflag2; /* 0x2c */ 187 u32 iflag1; /* 0x30 */ 188 u32 crl2; /* 0x34 */ 189 u32 esr2; /* 0x38 */ 190 u32 imeur; /* 0x3c */ 191 u32 lrfr; /* 0x40 */ 192 u32 crcr; /* 0x44 */ 193 u32 rxfgmask; /* 0x48 */ 194 u32 rxfir; /* 0x4c */ 195 u32 _reserved3[12]; 196 struct flexcan_mb cantxfg[64]; 197}; 198 199struct flexcan_devtype_data { 200 u32 features; /* hardware controller features */ 201}; 202 203struct flexcan_priv { 204 struct can_priv can; 205 struct net_device *dev; 206 struct napi_struct napi; 207 208 void __iomem *base; 209 u32 reg_esr; 210 u32 reg_ctrl_default; 211 212 struct clk *clk_ipg; 213 struct clk *clk_per; 214 struct flexcan_platform_data *pdata; 215 const struct flexcan_devtype_data *devtype_data; 216 struct regulator *reg_xceiver; 217}; 218 219static struct flexcan_devtype_data fsl_p1010_devtype_data = { 220 .features = FLEXCAN_HAS_BROKEN_ERR_STATE, 221}; 222static struct flexcan_devtype_data fsl_imx28_devtype_data; 223static struct flexcan_devtype_data fsl_imx6q_devtype_data = { 224 .features = FLEXCAN_HAS_V10_FEATURES, 225}; 226 227static const struct can_bittiming_const flexcan_bittiming_const = { 228 .name = DRV_NAME, 229 .tseg1_min = 4, 230 .tseg1_max = 16, 231 .tseg2_min = 2, 232 .tseg2_max = 8, 233 .sjw_max = 4, 234 .brp_min = 1, 235 .brp_max = 256, 236 .brp_inc = 1, 237}; 238 239/* 240 * Abstract off the read/write for arm versus ppc. This 241 * assumes that PPC uses big-endian registers and everything 242 * else uses little-endian registers, independent of CPU 243 * endianess. 244 */ 245#if defined(CONFIG_PPC) 246static inline u32 flexcan_read(void __iomem *addr) 247{ 248 return in_be32(addr); 249} 250 251static inline void flexcan_write(u32 val, void __iomem *addr) 252{ 253 out_be32(addr, val); 254} 255#else 256static inline u32 flexcan_read(void __iomem *addr) 257{ 258 return readl(addr); 259} 260 261static inline void flexcan_write(u32 val, void __iomem *addr) 262{ 263 writel(val, addr); 264} 265#endif 266 267static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv) 268{ 269 if (!priv->reg_xceiver) 270 return 0; 271 272 return regulator_enable(priv->reg_xceiver); 273} 274 275static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv) 276{ 277 if (!priv->reg_xceiver) 278 return 0; 279 280 return regulator_disable(priv->reg_xceiver); 281} 282 283static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, 284 u32 reg_esr) 285{ 286 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 287 (reg_esr & FLEXCAN_ESR_ERR_BUS); 288} 289 290static int flexcan_chip_enable(struct flexcan_priv *priv) 291{ 292 struct flexcan_regs __iomem *regs = priv->base; 293 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 294 u32 reg; 295 296 reg = flexcan_read(®s->mcr); 297 reg &= ~FLEXCAN_MCR_MDIS; 298 flexcan_write(reg, ®s->mcr); 299 300 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 301 usleep_range(10, 20); 302 303 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK) 304 return -ETIMEDOUT; 305 306 return 0; 307} 308 309static int flexcan_chip_disable(struct flexcan_priv *priv) 310{ 311 struct flexcan_regs __iomem *regs = priv->base; 312 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 313 u32 reg; 314 315 reg = flexcan_read(®s->mcr); 316 reg |= FLEXCAN_MCR_MDIS; 317 flexcan_write(reg, ®s->mcr); 318 319 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 320 usleep_range(10, 20); 321 322 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 323 return -ETIMEDOUT; 324 325 return 0; 326} 327 328static int flexcan_chip_freeze(struct flexcan_priv *priv) 329{ 330 struct flexcan_regs __iomem *regs = priv->base; 331 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate; 332 u32 reg; 333 334 reg = flexcan_read(®s->mcr); 335 reg |= FLEXCAN_MCR_HALT; 336 flexcan_write(reg, ®s->mcr); 337 338 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 339 usleep_range(100, 200); 340 341 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 342 return -ETIMEDOUT; 343 344 return 0; 345} 346 347static int flexcan_chip_unfreeze(struct flexcan_priv *priv) 348{ 349 struct flexcan_regs __iomem *regs = priv->base; 350 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 351 u32 reg; 352 353 reg = flexcan_read(®s->mcr); 354 reg &= ~FLEXCAN_MCR_HALT; 355 flexcan_write(reg, ®s->mcr); 356 357 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 358 usleep_range(10, 20); 359 360 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK) 361 return -ETIMEDOUT; 362 363 return 0; 364} 365 366static int flexcan_chip_softreset(struct flexcan_priv *priv) 367{ 368 struct flexcan_regs __iomem *regs = priv->base; 369 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 370 371 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 372 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)) 373 usleep_range(10, 20); 374 375 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST) 376 return -ETIMEDOUT; 377 378 return 0; 379} 380 381 382static int __flexcan_get_berr_counter(const struct net_device *dev, 383 struct can_berr_counter *bec) 384{ 385 const struct flexcan_priv *priv = netdev_priv(dev); 386 struct flexcan_regs __iomem *regs = priv->base; 387 u32 reg = flexcan_read(®s->ecr); 388 389 bec->txerr = (reg >> 0) & 0xff; 390 bec->rxerr = (reg >> 8) & 0xff; 391 392 return 0; 393} 394 395static int flexcan_get_berr_counter(const struct net_device *dev, 396 struct can_berr_counter *bec) 397{ 398 const struct flexcan_priv *priv = netdev_priv(dev); 399 int err; 400 401 err = clk_prepare_enable(priv->clk_ipg); 402 if (err) 403 return err; 404 405 err = clk_prepare_enable(priv->clk_per); 406 if (err) 407 goto out_disable_ipg; 408 409 err = __flexcan_get_berr_counter(dev, bec); 410 411 clk_disable_unprepare(priv->clk_per); 412 out_disable_ipg: 413 clk_disable_unprepare(priv->clk_ipg); 414 415 return err; 416} 417 418static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 419{ 420 const struct flexcan_priv *priv = netdev_priv(dev); 421 struct flexcan_regs __iomem *regs = priv->base; 422 struct can_frame *cf = (struct can_frame *)skb->data; 423 u32 can_id; 424 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); 425 426 if (can_dropped_invalid_skb(dev, skb)) 427 return NETDEV_TX_OK; 428 429 netif_stop_queue(dev); 430 431 if (cf->can_id & CAN_EFF_FLAG) { 432 can_id = cf->can_id & CAN_EFF_MASK; 433 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 434 } else { 435 can_id = (cf->can_id & CAN_SFF_MASK) << 18; 436 } 437 438 if (cf->can_id & CAN_RTR_FLAG) 439 ctrl |= FLEXCAN_MB_CNT_RTR; 440 441 if (cf->can_dlc > 0) { 442 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 443 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 444 } 445 if (cf->can_dlc > 3) { 446 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 447 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 448 } 449 450 can_put_echo_skb(skb, dev, 0); 451 452 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 453 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 454 455 return NETDEV_TX_OK; 456} 457 458static void do_bus_err(struct net_device *dev, 459 struct can_frame *cf, u32 reg_esr) 460{ 461 struct flexcan_priv *priv = netdev_priv(dev); 462 int rx_errors = 0, tx_errors = 0; 463 464 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 465 466 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 467 netdev_dbg(dev, "BIT1_ERR irq\n"); 468 cf->data[2] |= CAN_ERR_PROT_BIT1; 469 tx_errors = 1; 470 } 471 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 472 netdev_dbg(dev, "BIT0_ERR irq\n"); 473 cf->data[2] |= CAN_ERR_PROT_BIT0; 474 tx_errors = 1; 475 } 476 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 477 netdev_dbg(dev, "ACK_ERR irq\n"); 478 cf->can_id |= CAN_ERR_ACK; 479 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 480 tx_errors = 1; 481 } 482 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 483 netdev_dbg(dev, "CRC_ERR irq\n"); 484 cf->data[2] |= CAN_ERR_PROT_BIT; 485 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 486 rx_errors = 1; 487 } 488 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 489 netdev_dbg(dev, "FRM_ERR irq\n"); 490 cf->data[2] |= CAN_ERR_PROT_FORM; 491 rx_errors = 1; 492 } 493 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 494 netdev_dbg(dev, "STF_ERR irq\n"); 495 cf->data[2] |= CAN_ERR_PROT_STUFF; 496 rx_errors = 1; 497 } 498 499 priv->can.can_stats.bus_error++; 500 if (rx_errors) 501 dev->stats.rx_errors++; 502 if (tx_errors) 503 dev->stats.tx_errors++; 504} 505 506static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) 507{ 508 struct sk_buff *skb; 509 struct can_frame *cf; 510 511 skb = alloc_can_err_skb(dev, &cf); 512 if (unlikely(!skb)) 513 return 0; 514 515 do_bus_err(dev, cf, reg_esr); 516 netif_receive_skb(skb); 517 518 dev->stats.rx_packets++; 519 dev->stats.rx_bytes += cf->can_dlc; 520 521 return 1; 522} 523 524static void do_state(struct net_device *dev, 525 struct can_frame *cf, enum can_state new_state) 526{ 527 struct flexcan_priv *priv = netdev_priv(dev); 528 struct can_berr_counter bec; 529 530 __flexcan_get_berr_counter(dev, &bec); 531 532 switch (priv->can.state) { 533 case CAN_STATE_ERROR_ACTIVE: 534 /* 535 * from: ERROR_ACTIVE 536 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 537 * => : there was a warning int 538 */ 539 if (new_state >= CAN_STATE_ERROR_WARNING && 540 new_state <= CAN_STATE_BUS_OFF) { 541 netdev_dbg(dev, "Error Warning IRQ\n"); 542 priv->can.can_stats.error_warning++; 543 544 cf->can_id |= CAN_ERR_CRTL; 545 cf->data[1] = (bec.txerr > bec.rxerr) ? 546 CAN_ERR_CRTL_TX_WARNING : 547 CAN_ERR_CRTL_RX_WARNING; 548 } 549 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 550 /* 551 * from: ERROR_ACTIVE, ERROR_WARNING 552 * to : ERROR_PASSIVE, BUS_OFF 553 * => : error passive int 554 */ 555 if (new_state >= CAN_STATE_ERROR_PASSIVE && 556 new_state <= CAN_STATE_BUS_OFF) { 557 netdev_dbg(dev, "Error Passive IRQ\n"); 558 priv->can.can_stats.error_passive++; 559 560 cf->can_id |= CAN_ERR_CRTL; 561 cf->data[1] = (bec.txerr > bec.rxerr) ? 562 CAN_ERR_CRTL_TX_PASSIVE : 563 CAN_ERR_CRTL_RX_PASSIVE; 564 } 565 break; 566 case CAN_STATE_BUS_OFF: 567 netdev_err(dev, "BUG! " 568 "hardware recovered automatically from BUS_OFF\n"); 569 break; 570 default: 571 break; 572 } 573 574 /* process state changes depending on the new state */ 575 switch (new_state) { 576 case CAN_STATE_ERROR_ACTIVE: 577 netdev_dbg(dev, "Error Active\n"); 578 cf->can_id |= CAN_ERR_PROT; 579 cf->data[2] = CAN_ERR_PROT_ACTIVE; 580 break; 581 case CAN_STATE_BUS_OFF: 582 cf->can_id |= CAN_ERR_BUSOFF; 583 can_bus_off(dev); 584 break; 585 default: 586 break; 587 } 588} 589 590static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) 591{ 592 struct flexcan_priv *priv = netdev_priv(dev); 593 struct sk_buff *skb; 594 struct can_frame *cf; 595 enum can_state new_state; 596 int flt; 597 598 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 599 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 600 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | 601 FLEXCAN_ESR_RX_WRN)))) 602 new_state = CAN_STATE_ERROR_ACTIVE; 603 else 604 new_state = CAN_STATE_ERROR_WARNING; 605 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) 606 new_state = CAN_STATE_ERROR_PASSIVE; 607 else 608 new_state = CAN_STATE_BUS_OFF; 609 610 /* state hasn't changed */ 611 if (likely(new_state == priv->can.state)) 612 return 0; 613 614 skb = alloc_can_err_skb(dev, &cf); 615 if (unlikely(!skb)) 616 return 0; 617 618 do_state(dev, cf, new_state); 619 priv->can.state = new_state; 620 netif_receive_skb(skb); 621 622 dev->stats.rx_packets++; 623 dev->stats.rx_bytes += cf->can_dlc; 624 625 return 1; 626} 627 628static void flexcan_read_fifo(const struct net_device *dev, 629 struct can_frame *cf) 630{ 631 const struct flexcan_priv *priv = netdev_priv(dev); 632 struct flexcan_regs __iomem *regs = priv->base; 633 struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; 634 u32 reg_ctrl, reg_id; 635 636 reg_ctrl = flexcan_read(&mb->can_ctrl); 637 reg_id = flexcan_read(&mb->can_id); 638 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 639 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 640 else 641 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; 642 643 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 644 cf->can_id |= CAN_RTR_FLAG; 645 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 646 647 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); 648 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); 649 650 /* mark as read */ 651 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 652 flexcan_read(®s->timer); 653} 654 655static int flexcan_read_frame(struct net_device *dev) 656{ 657 struct net_device_stats *stats = &dev->stats; 658 struct can_frame *cf; 659 struct sk_buff *skb; 660 661 skb = alloc_can_skb(dev, &cf); 662 if (unlikely(!skb)) { 663 stats->rx_dropped++; 664 return 0; 665 } 666 667 flexcan_read_fifo(dev, cf); 668 netif_receive_skb(skb); 669 670 stats->rx_packets++; 671 stats->rx_bytes += cf->can_dlc; 672 673 can_led_event(dev, CAN_LED_EVENT_RX); 674 675 return 1; 676} 677 678static int flexcan_poll(struct napi_struct *napi, int quota) 679{ 680 struct net_device *dev = napi->dev; 681 const struct flexcan_priv *priv = netdev_priv(dev); 682 struct flexcan_regs __iomem *regs = priv->base; 683 u32 reg_iflag1, reg_esr; 684 int work_done = 0; 685 686 /* 687 * The error bits are cleared on read, 688 * use saved value from irq handler. 689 */ 690 reg_esr = flexcan_read(®s->esr) | priv->reg_esr; 691 692 /* handle state changes */ 693 work_done += flexcan_poll_state(dev, reg_esr); 694 695 /* handle RX-FIFO */ 696 reg_iflag1 = flexcan_read(®s->iflag1); 697 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 698 work_done < quota) { 699 work_done += flexcan_read_frame(dev); 700 reg_iflag1 = flexcan_read(®s->iflag1); 701 } 702 703 /* report bus errors */ 704 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) 705 work_done += flexcan_poll_bus_err(dev, reg_esr); 706 707 if (work_done < quota) { 708 napi_complete(napi); 709 /* enable IRQs */ 710 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 711 flexcan_write(priv->reg_ctrl_default, ®s->ctrl); 712 } 713 714 return work_done; 715} 716 717static irqreturn_t flexcan_irq(int irq, void *dev_id) 718{ 719 struct net_device *dev = dev_id; 720 struct net_device_stats *stats = &dev->stats; 721 struct flexcan_priv *priv = netdev_priv(dev); 722 struct flexcan_regs __iomem *regs = priv->base; 723 u32 reg_iflag1, reg_esr; 724 725 reg_iflag1 = flexcan_read(®s->iflag1); 726 reg_esr = flexcan_read(®s->esr); 727 /* ACK all bus error and state change IRQ sources */ 728 if (reg_esr & FLEXCAN_ESR_ALL_INT) 729 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); 730 731 /* 732 * schedule NAPI in case of: 733 * - rx IRQ 734 * - state change IRQ 735 * - bus error IRQ and bus error reporting is activated 736 */ 737 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || 738 (reg_esr & FLEXCAN_ESR_ERR_STATE) || 739 flexcan_has_and_handle_berr(priv, reg_esr)) { 740 /* 741 * The error bits are cleared on read, 742 * save them for later use. 743 */ 744 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 745 flexcan_write(FLEXCAN_IFLAG_DEFAULT & 746 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); 747 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 748 ®s->ctrl); 749 napi_schedule(&priv->napi); 750 } 751 752 /* FIFO overflow */ 753 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 754 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); 755 dev->stats.rx_over_errors++; 756 dev->stats.rx_errors++; 757 } 758 759 /* transmission complete interrupt */ 760 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 761 stats->tx_bytes += can_get_echo_skb(dev, 0); 762 stats->tx_packets++; 763 can_led_event(dev, CAN_LED_EVENT_TX); 764 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); 765 netif_wake_queue(dev); 766 } 767 768 return IRQ_HANDLED; 769} 770 771static void flexcan_set_bittiming(struct net_device *dev) 772{ 773 const struct flexcan_priv *priv = netdev_priv(dev); 774 const struct can_bittiming *bt = &priv->can.bittiming; 775 struct flexcan_regs __iomem *regs = priv->base; 776 u32 reg; 777 778 reg = flexcan_read(®s->ctrl); 779 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 780 FLEXCAN_CTRL_RJW(0x3) | 781 FLEXCAN_CTRL_PSEG1(0x7) | 782 FLEXCAN_CTRL_PSEG2(0x7) | 783 FLEXCAN_CTRL_PROPSEG(0x7) | 784 FLEXCAN_CTRL_LPB | 785 FLEXCAN_CTRL_SMP | 786 FLEXCAN_CTRL_LOM); 787 788 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 789 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 790 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 791 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 792 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 793 794 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 795 reg |= FLEXCAN_CTRL_LPB; 796 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 797 reg |= FLEXCAN_CTRL_LOM; 798 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 799 reg |= FLEXCAN_CTRL_SMP; 800 801 netdev_info(dev, "writing ctrl=0x%08x\n", reg); 802 flexcan_write(reg, ®s->ctrl); 803 804 /* print chip status */ 805 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 806 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 807} 808 809/* 810 * flexcan_chip_start 811 * 812 * this functions is entered with clocks enabled 813 * 814 */ 815static int flexcan_chip_start(struct net_device *dev) 816{ 817 struct flexcan_priv *priv = netdev_priv(dev); 818 struct flexcan_regs __iomem *regs = priv->base; 819 int err; 820 u32 reg_mcr, reg_ctrl; 821 822 /* enable module */ 823 err = flexcan_chip_enable(priv); 824 if (err) 825 return err; 826 827 /* soft reset */ 828 err = flexcan_chip_softreset(priv); 829 if (err) 830 goto out_chip_disable; 831 832 flexcan_set_bittiming(dev); 833 834 /* 835 * MCR 836 * 837 * enable freeze 838 * enable fifo 839 * halt now 840 * only supervisor access 841 * enable warning int 842 * choose format C 843 * disable local echo 844 * 845 */ 846 reg_mcr = flexcan_read(®s->mcr); 847 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff); 848 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 849 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 850 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS | 851 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID); 852 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); 853 flexcan_write(reg_mcr, ®s->mcr); 854 855 /* 856 * CTRL 857 * 858 * disable timer sync feature 859 * 860 * disable auto busoff recovery 861 * transmit lowest buffer first 862 * 863 * enable tx and rx warning interrupt 864 * enable bus off interrupt 865 * (== FLEXCAN_CTRL_ERR_STATE) 866 */ 867 reg_ctrl = flexcan_read(®s->ctrl); 868 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 869 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 870 FLEXCAN_CTRL_ERR_STATE; 871 /* 872 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), 873 * on most Flexcan cores, too. Otherwise we don't get 874 * any error warning or passive interrupts. 875 */ 876 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE || 877 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 878 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; 879 880 /* save for later use */ 881 priv->reg_ctrl_default = reg_ctrl; 882 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 883 flexcan_write(reg_ctrl, ®s->ctrl); 884 885 /* Abort any pending TX, mark Mailbox as INACTIVE */ 886 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4), 887 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 888 889 /* acceptance mask/acceptance code (accept everything) */ 890 flexcan_write(0x0, ®s->rxgmask); 891 flexcan_write(0x0, ®s->rx14mask); 892 flexcan_write(0x0, ®s->rx15mask); 893 894 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) 895 flexcan_write(0x0, ®s->rxfgmask); 896 897 err = flexcan_transceiver_enable(priv); 898 if (err) 899 goto out_chip_disable; 900 901 /* synchronize with the can bus */ 902 err = flexcan_chip_unfreeze(priv); 903 if (err) 904 goto out_transceiver_disable; 905 906 priv->can.state = CAN_STATE_ERROR_ACTIVE; 907 908 /* enable FIFO interrupts */ 909 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 910 911 /* print chip status */ 912 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, 913 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 914 915 return 0; 916 917 out_transceiver_disable: 918 flexcan_transceiver_disable(priv); 919 out_chip_disable: 920 flexcan_chip_disable(priv); 921 return err; 922} 923 924/* 925 * flexcan_chip_stop 926 * 927 * this functions is entered with clocks enabled 928 * 929 */ 930static void flexcan_chip_stop(struct net_device *dev) 931{ 932 struct flexcan_priv *priv = netdev_priv(dev); 933 struct flexcan_regs __iomem *regs = priv->base; 934 935 /* freeze + disable module */ 936 flexcan_chip_freeze(priv); 937 flexcan_chip_disable(priv); 938 939 /* Disable all interrupts */ 940 flexcan_write(0, ®s->imask1); 941 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 942 ®s->ctrl); 943 944 flexcan_transceiver_disable(priv); 945 priv->can.state = CAN_STATE_STOPPED; 946 947 return; 948} 949 950static int flexcan_open(struct net_device *dev) 951{ 952 struct flexcan_priv *priv = netdev_priv(dev); 953 int err; 954 955 err = clk_prepare_enable(priv->clk_ipg); 956 if (err) 957 return err; 958 959 err = clk_prepare_enable(priv->clk_per); 960 if (err) 961 goto out_disable_ipg; 962 963 err = open_candev(dev); 964 if (err) 965 goto out_disable_per; 966 967 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 968 if (err) 969 goto out_close; 970 971 /* start chip and queuing */ 972 err = flexcan_chip_start(dev); 973 if (err) 974 goto out_free_irq; 975 976 can_led_event(dev, CAN_LED_EVENT_OPEN); 977 978 napi_enable(&priv->napi); 979 netif_start_queue(dev); 980 981 return 0; 982 983 out_free_irq: 984 free_irq(dev->irq, dev); 985 out_close: 986 close_candev(dev); 987 out_disable_per: 988 clk_disable_unprepare(priv->clk_per); 989 out_disable_ipg: 990 clk_disable_unprepare(priv->clk_ipg); 991 992 return err; 993} 994 995static int flexcan_close(struct net_device *dev) 996{ 997 struct flexcan_priv *priv = netdev_priv(dev); 998 999 netif_stop_queue(dev); 1000 napi_disable(&priv->napi); 1001 flexcan_chip_stop(dev); 1002 1003 free_irq(dev->irq, dev); 1004 clk_disable_unprepare(priv->clk_per); 1005 clk_disable_unprepare(priv->clk_ipg); 1006 1007 close_candev(dev); 1008 1009 can_led_event(dev, CAN_LED_EVENT_STOP); 1010 1011 return 0; 1012} 1013 1014static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 1015{ 1016 int err; 1017 1018 switch (mode) { 1019 case CAN_MODE_START: 1020 err = flexcan_chip_start(dev); 1021 if (err) 1022 return err; 1023 1024 netif_wake_queue(dev); 1025 break; 1026 1027 default: 1028 return -EOPNOTSUPP; 1029 } 1030 1031 return 0; 1032} 1033 1034static const struct net_device_ops flexcan_netdev_ops = { 1035 .ndo_open = flexcan_open, 1036 .ndo_stop = flexcan_close, 1037 .ndo_start_xmit = flexcan_start_xmit, 1038 .ndo_change_mtu = can_change_mtu, 1039}; 1040 1041static int register_flexcandev(struct net_device *dev) 1042{ 1043 struct flexcan_priv *priv = netdev_priv(dev); 1044 struct flexcan_regs __iomem *regs = priv->base; 1045 u32 reg, err; 1046 1047 err = clk_prepare_enable(priv->clk_ipg); 1048 if (err) 1049 return err; 1050 1051 err = clk_prepare_enable(priv->clk_per); 1052 if (err) 1053 goto out_disable_ipg; 1054 1055 /* select "bus clock", chip must be disabled */ 1056 err = flexcan_chip_disable(priv); 1057 if (err) 1058 goto out_disable_per; 1059 reg = flexcan_read(®s->ctrl); 1060 reg |= FLEXCAN_CTRL_CLK_SRC; 1061 flexcan_write(reg, ®s->ctrl); 1062 1063 err = flexcan_chip_enable(priv); 1064 if (err) 1065 goto out_chip_disable; 1066 1067 /* set freeze, halt and activate FIFO, restrict register access */ 1068 reg = flexcan_read(®s->mcr); 1069 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 1070 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 1071 flexcan_write(reg, ®s->mcr); 1072 1073 /* 1074 * Currently we only support newer versions of this core 1075 * featuring a RX FIFO. Older cores found on some Coldfire 1076 * derivates are not yet supported. 1077 */ 1078 reg = flexcan_read(®s->mcr); 1079 if (!(reg & FLEXCAN_MCR_FEN)) { 1080 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); 1081 err = -ENODEV; 1082 goto out_chip_disable; 1083 } 1084 1085 err = register_candev(dev); 1086 1087 /* disable core and turn off clocks */ 1088 out_chip_disable: 1089 flexcan_chip_disable(priv); 1090 out_disable_per: 1091 clk_disable_unprepare(priv->clk_per); 1092 out_disable_ipg: 1093 clk_disable_unprepare(priv->clk_ipg); 1094 1095 return err; 1096} 1097 1098static void unregister_flexcandev(struct net_device *dev) 1099{ 1100 unregister_candev(dev); 1101} 1102 1103static const struct of_device_id flexcan_of_match[] = { 1104 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, 1105 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, 1106 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, 1107 { /* sentinel */ }, 1108}; 1109MODULE_DEVICE_TABLE(of, flexcan_of_match); 1110 1111static const struct platform_device_id flexcan_id_table[] = { 1112 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, }, 1113 { /* sentinel */ }, 1114}; 1115MODULE_DEVICE_TABLE(platform, flexcan_id_table); 1116 1117static int flexcan_probe(struct platform_device *pdev) 1118{ 1119 const struct of_device_id *of_id; 1120 const struct flexcan_devtype_data *devtype_data; 1121 struct net_device *dev; 1122 struct flexcan_priv *priv; 1123 struct resource *mem; 1124 struct clk *clk_ipg = NULL, *clk_per = NULL; 1125 void __iomem *base; 1126 int err, irq; 1127 u32 clock_freq = 0; 1128 1129 if (pdev->dev.of_node) 1130 of_property_read_u32(pdev->dev.of_node, 1131 "clock-frequency", &clock_freq); 1132 1133 if (!clock_freq) { 1134 clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1135 if (IS_ERR(clk_ipg)) { 1136 dev_err(&pdev->dev, "no ipg clock defined\n"); 1137 return PTR_ERR(clk_ipg); 1138 } 1139 1140 clk_per = devm_clk_get(&pdev->dev, "per"); 1141 if (IS_ERR(clk_per)) { 1142 dev_err(&pdev->dev, "no per clock defined\n"); 1143 return PTR_ERR(clk_per); 1144 } 1145 clock_freq = clk_get_rate(clk_per); 1146 } 1147 1148 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1149 irq = platform_get_irq(pdev, 0); 1150 if (irq <= 0) 1151 return -ENODEV; 1152 1153 base = devm_ioremap_resource(&pdev->dev, mem); 1154 if (IS_ERR(base)) 1155 return PTR_ERR(base); 1156 1157 of_id = of_match_device(flexcan_of_match, &pdev->dev); 1158 if (of_id) { 1159 devtype_data = of_id->data; 1160 } else if (platform_get_device_id(pdev)->driver_data) { 1161 devtype_data = (struct flexcan_devtype_data *) 1162 platform_get_device_id(pdev)->driver_data; 1163 } else { 1164 return -ENODEV; 1165 } 1166 1167 dev = alloc_candev(sizeof(struct flexcan_priv), 1); 1168 if (!dev) 1169 return -ENOMEM; 1170 1171 dev->netdev_ops = &flexcan_netdev_ops; 1172 dev->irq = irq; 1173 dev->flags |= IFF_ECHO; 1174 1175 priv = netdev_priv(dev); 1176 priv->can.clock.freq = clock_freq; 1177 priv->can.bittiming_const = &flexcan_bittiming_const; 1178 priv->can.do_set_mode = flexcan_set_mode; 1179 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 1180 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1181 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 1182 CAN_CTRLMODE_BERR_REPORTING; 1183 priv->base = base; 1184 priv->dev = dev; 1185 priv->clk_ipg = clk_ipg; 1186 priv->clk_per = clk_per; 1187 priv->pdata = dev_get_platdata(&pdev->dev); 1188 priv->devtype_data = devtype_data; 1189 1190 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); 1191 if (IS_ERR(priv->reg_xceiver)) 1192 priv->reg_xceiver = NULL; 1193 1194 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); 1195 1196 platform_set_drvdata(pdev, dev); 1197 SET_NETDEV_DEV(dev, &pdev->dev); 1198 1199 err = register_flexcandev(dev); 1200 if (err) { 1201 dev_err(&pdev->dev, "registering netdev failed\n"); 1202 goto failed_register; 1203 } 1204 1205 devm_can_led_init(dev); 1206 1207 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1208 priv->base, dev->irq); 1209 1210 return 0; 1211 1212 failed_register: 1213 free_candev(dev); 1214 return err; 1215} 1216 1217static int flexcan_remove(struct platform_device *pdev) 1218{ 1219 struct net_device *dev = platform_get_drvdata(pdev); 1220 struct flexcan_priv *priv = netdev_priv(dev); 1221 1222 unregister_flexcandev(dev); 1223 netif_napi_del(&priv->napi); 1224 free_candev(dev); 1225 1226 return 0; 1227} 1228 1229static int __maybe_unused flexcan_suspend(struct device *device) 1230{ 1231 struct net_device *dev = dev_get_drvdata(device); 1232 struct flexcan_priv *priv = netdev_priv(dev); 1233 int err; 1234 1235 err = flexcan_chip_disable(priv); 1236 if (err) 1237 return err; 1238 1239 if (netif_running(dev)) { 1240 netif_stop_queue(dev); 1241 netif_device_detach(dev); 1242 } 1243 priv->can.state = CAN_STATE_SLEEPING; 1244 1245 return 0; 1246} 1247 1248static int __maybe_unused flexcan_resume(struct device *device) 1249{ 1250 struct net_device *dev = dev_get_drvdata(device); 1251 struct flexcan_priv *priv = netdev_priv(dev); 1252 1253 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1254 if (netif_running(dev)) { 1255 netif_device_attach(dev); 1256 netif_start_queue(dev); 1257 } 1258 return flexcan_chip_enable(priv); 1259} 1260 1261static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume); 1262 1263static struct platform_driver flexcan_driver = { 1264 .driver = { 1265 .name = DRV_NAME, 1266 .owner = THIS_MODULE, 1267 .pm = &flexcan_pm_ops, 1268 .of_match_table = flexcan_of_match, 1269 }, 1270 .probe = flexcan_probe, 1271 .remove = flexcan_remove, 1272 .id_table = flexcan_id_table, 1273}; 1274 1275module_platform_driver(flexcan_driver); 1276 1277MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 1278 "Marc Kleine-Budde <kernel@pengutronix.de>"); 1279MODULE_LICENSE("GPL v2"); 1280MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 1281