flexcan.c revision f003698e23f6f56a791774f14d0ac35d04872490
1/* 2 * flexcan.c - FLEXCAN CAN controller driver 3 * 4 * Copyright (c) 2005-2006 Varma Electronics Oy 5 * Copyright (c) 2009 Sascha Hauer, Pengutronix 6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix 7 * 8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com> 9 * 10 * LICENCE: 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22#include <linux/netdevice.h> 23#include <linux/can.h> 24#include <linux/can/dev.h> 25#include <linux/can/error.h> 26#include <linux/can/led.h> 27#include <linux/clk.h> 28#include <linux/delay.h> 29#include <linux/if_arp.h> 30#include <linux/if_ether.h> 31#include <linux/interrupt.h> 32#include <linux/io.h> 33#include <linux/kernel.h> 34#include <linux/list.h> 35#include <linux/module.h> 36#include <linux/of.h> 37#include <linux/of_device.h> 38#include <linux/platform_device.h> 39#include <linux/regulator/consumer.h> 40 41#define DRV_NAME "flexcan" 42 43/* 8 for RX fifo and 2 error handling */ 44#define FLEXCAN_NAPI_WEIGHT (8 + 2) 45 46/* FLEXCAN module configuration register (CANMCR) bits */ 47#define FLEXCAN_MCR_MDIS BIT(31) 48#define FLEXCAN_MCR_FRZ BIT(30) 49#define FLEXCAN_MCR_FEN BIT(29) 50#define FLEXCAN_MCR_HALT BIT(28) 51#define FLEXCAN_MCR_NOT_RDY BIT(27) 52#define FLEXCAN_MCR_WAK_MSK BIT(26) 53#define FLEXCAN_MCR_SOFTRST BIT(25) 54#define FLEXCAN_MCR_FRZ_ACK BIT(24) 55#define FLEXCAN_MCR_SUPV BIT(23) 56#define FLEXCAN_MCR_SLF_WAK BIT(22) 57#define FLEXCAN_MCR_WRN_EN BIT(21) 58#define FLEXCAN_MCR_LPM_ACK BIT(20) 59#define FLEXCAN_MCR_WAK_SRC BIT(19) 60#define FLEXCAN_MCR_DOZE BIT(18) 61#define FLEXCAN_MCR_SRX_DIS BIT(17) 62#define FLEXCAN_MCR_BCC BIT(16) 63#define FLEXCAN_MCR_LPRIO_EN BIT(13) 64#define FLEXCAN_MCR_AEN BIT(12) 65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f) 66#define FLEXCAN_MCR_IDAM_A (0 << 8) 67#define FLEXCAN_MCR_IDAM_B (1 << 8) 68#define FLEXCAN_MCR_IDAM_C (2 << 8) 69#define FLEXCAN_MCR_IDAM_D (3 << 8) 70 71/* FLEXCAN control register (CANCTRL) bits */ 72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 76#define FLEXCAN_CTRL_BOFF_MSK BIT(15) 77#define FLEXCAN_CTRL_ERR_MSK BIT(14) 78#define FLEXCAN_CTRL_CLK_SRC BIT(13) 79#define FLEXCAN_CTRL_LPB BIT(12) 80#define FLEXCAN_CTRL_TWRN_MSK BIT(11) 81#define FLEXCAN_CTRL_RWRN_MSK BIT(10) 82#define FLEXCAN_CTRL_SMP BIT(7) 83#define FLEXCAN_CTRL_BOFF_REC BIT(6) 84#define FLEXCAN_CTRL_TSYN BIT(5) 85#define FLEXCAN_CTRL_LBUF BIT(4) 86#define FLEXCAN_CTRL_LOM BIT(3) 87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 89#define FLEXCAN_CTRL_ERR_STATE \ 90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 91 FLEXCAN_CTRL_BOFF_MSK) 92#define FLEXCAN_CTRL_ERR_ALL \ 93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 94 95/* FLEXCAN error and status register (ESR) bits */ 96#define FLEXCAN_ESR_TWRN_INT BIT(17) 97#define FLEXCAN_ESR_RWRN_INT BIT(16) 98#define FLEXCAN_ESR_BIT1_ERR BIT(15) 99#define FLEXCAN_ESR_BIT0_ERR BIT(14) 100#define FLEXCAN_ESR_ACK_ERR BIT(13) 101#define FLEXCAN_ESR_CRC_ERR BIT(12) 102#define FLEXCAN_ESR_FRM_ERR BIT(11) 103#define FLEXCAN_ESR_STF_ERR BIT(10) 104#define FLEXCAN_ESR_TX_WRN BIT(9) 105#define FLEXCAN_ESR_RX_WRN BIT(8) 106#define FLEXCAN_ESR_IDLE BIT(7) 107#define FLEXCAN_ESR_TXRX BIT(6) 108#define FLEXCAN_EST_FLT_CONF_SHIFT (4) 109#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 110#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 111#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 112#define FLEXCAN_ESR_BOFF_INT BIT(2) 113#define FLEXCAN_ESR_ERR_INT BIT(1) 114#define FLEXCAN_ESR_WAK_INT BIT(0) 115#define FLEXCAN_ESR_ERR_BUS \ 116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 119#define FLEXCAN_ESR_ERR_STATE \ 120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 121#define FLEXCAN_ESR_ERR_ALL \ 122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 123#define FLEXCAN_ESR_ALL_INT \ 124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ 125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) 126 127/* FLEXCAN interrupt flag register (IFLAG) bits */ 128#define FLEXCAN_TX_BUF_ID 8 129#define FLEXCAN_IFLAG_BUF(x) BIT(x) 130#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 131#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 132#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 133#define FLEXCAN_IFLAG_DEFAULT \ 134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ 135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) 136 137/* FLEXCAN message buffers */ 138#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) 139#define FLEXCAN_MB_CNT_SRR BIT(22) 140#define FLEXCAN_MB_CNT_IDE BIT(21) 141#define FLEXCAN_MB_CNT_RTR BIT(20) 142#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 143#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 144 145#define FLEXCAN_MB_CODE_MASK (0xf0ffffff) 146 147#define FLEXCAN_TIMEOUT_US (50) 148 149/* 150 * FLEXCAN hardware feature flags 151 * 152 * Below is some version info we got: 153 * SOC Version IP-Version Glitch- [TR]WRN_INT 154 * Filter? connected? 155 * MX25 FlexCAN2 03.00.00.00 no no 156 * MX28 FlexCAN2 03.00.04.00 yes yes 157 * MX35 FlexCAN2 03.00.00.00 no no 158 * MX53 FlexCAN2 03.00.00.00 yes no 159 * MX6s FlexCAN3 10.00.12.00 yes yes 160 * 161 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected. 162 */ 163#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */ 164#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */ 165 166/* Structure of the message buffer */ 167struct flexcan_mb { 168 u32 can_ctrl; 169 u32 can_id; 170 u32 data[2]; 171}; 172 173/* Structure of the hardware registers */ 174struct flexcan_regs { 175 u32 mcr; /* 0x00 */ 176 u32 ctrl; /* 0x04 */ 177 u32 timer; /* 0x08 */ 178 u32 _reserved1; /* 0x0c */ 179 u32 rxgmask; /* 0x10 */ 180 u32 rx14mask; /* 0x14 */ 181 u32 rx15mask; /* 0x18 */ 182 u32 ecr; /* 0x1c */ 183 u32 esr; /* 0x20 */ 184 u32 imask2; /* 0x24 */ 185 u32 imask1; /* 0x28 */ 186 u32 iflag2; /* 0x2c */ 187 u32 iflag1; /* 0x30 */ 188 u32 crl2; /* 0x34 */ 189 u32 esr2; /* 0x38 */ 190 u32 imeur; /* 0x3c */ 191 u32 lrfr; /* 0x40 */ 192 u32 crcr; /* 0x44 */ 193 u32 rxfgmask; /* 0x48 */ 194 u32 rxfir; /* 0x4c */ 195 u32 _reserved3[12]; 196 struct flexcan_mb cantxfg[64]; 197}; 198 199struct flexcan_devtype_data { 200 u32 features; /* hardware controller features */ 201}; 202 203struct flexcan_priv { 204 struct can_priv can; 205 struct net_device *dev; 206 struct napi_struct napi; 207 208 void __iomem *base; 209 u32 reg_esr; 210 u32 reg_ctrl_default; 211 212 struct clk *clk_ipg; 213 struct clk *clk_per; 214 struct flexcan_platform_data *pdata; 215 const struct flexcan_devtype_data *devtype_data; 216 struct regulator *reg_xceiver; 217}; 218 219static struct flexcan_devtype_data fsl_p1010_devtype_data = { 220 .features = FLEXCAN_HAS_BROKEN_ERR_STATE, 221}; 222static struct flexcan_devtype_data fsl_imx28_devtype_data; 223static struct flexcan_devtype_data fsl_imx6q_devtype_data = { 224 .features = FLEXCAN_HAS_V10_FEATURES, 225}; 226 227static const struct can_bittiming_const flexcan_bittiming_const = { 228 .name = DRV_NAME, 229 .tseg1_min = 4, 230 .tseg1_max = 16, 231 .tseg2_min = 2, 232 .tseg2_max = 8, 233 .sjw_max = 4, 234 .brp_min = 1, 235 .brp_max = 256, 236 .brp_inc = 1, 237}; 238 239/* 240 * Abstract off the read/write for arm versus ppc. This 241 * assumes that PPC uses big-endian registers and everything 242 * else uses little-endian registers, independent of CPU 243 * endianess. 244 */ 245#if defined(CONFIG_PPC) 246static inline u32 flexcan_read(void __iomem *addr) 247{ 248 return in_be32(addr); 249} 250 251static inline void flexcan_write(u32 val, void __iomem *addr) 252{ 253 out_be32(addr, val); 254} 255#else 256static inline u32 flexcan_read(void __iomem *addr) 257{ 258 return readl(addr); 259} 260 261static inline void flexcan_write(u32 val, void __iomem *addr) 262{ 263 writel(val, addr); 264} 265#endif 266 267static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv) 268{ 269 if (!priv->reg_xceiver) 270 return 0; 271 272 return regulator_enable(priv->reg_xceiver); 273} 274 275static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv) 276{ 277 if (!priv->reg_xceiver) 278 return 0; 279 280 return regulator_disable(priv->reg_xceiver); 281} 282 283static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, 284 u32 reg_esr) 285{ 286 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 287 (reg_esr & FLEXCAN_ESR_ERR_BUS); 288} 289 290static int flexcan_chip_enable(struct flexcan_priv *priv) 291{ 292 struct flexcan_regs __iomem *regs = priv->base; 293 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 294 u32 reg; 295 296 reg = flexcan_read(®s->mcr); 297 reg &= ~FLEXCAN_MCR_MDIS; 298 flexcan_write(reg, ®s->mcr); 299 300 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 301 usleep_range(10, 20); 302 303 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK) 304 return -ETIMEDOUT; 305 306 return 0; 307} 308 309static int flexcan_chip_disable(struct flexcan_priv *priv) 310{ 311 struct flexcan_regs __iomem *regs = priv->base; 312 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 313 u32 reg; 314 315 reg = flexcan_read(®s->mcr); 316 reg |= FLEXCAN_MCR_MDIS; 317 flexcan_write(reg, ®s->mcr); 318 319 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 320 usleep_range(10, 20); 321 322 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 323 return -ETIMEDOUT; 324 325 return 0; 326} 327 328static int flexcan_get_berr_counter(const struct net_device *dev, 329 struct can_berr_counter *bec) 330{ 331 const struct flexcan_priv *priv = netdev_priv(dev); 332 struct flexcan_regs __iomem *regs = priv->base; 333 u32 reg = flexcan_read(®s->ecr); 334 335 bec->txerr = (reg >> 0) & 0xff; 336 bec->rxerr = (reg >> 8) & 0xff; 337 338 return 0; 339} 340 341static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 342{ 343 const struct flexcan_priv *priv = netdev_priv(dev); 344 struct flexcan_regs __iomem *regs = priv->base; 345 struct can_frame *cf = (struct can_frame *)skb->data; 346 u32 can_id; 347 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); 348 349 if (can_dropped_invalid_skb(dev, skb)) 350 return NETDEV_TX_OK; 351 352 netif_stop_queue(dev); 353 354 if (cf->can_id & CAN_EFF_FLAG) { 355 can_id = cf->can_id & CAN_EFF_MASK; 356 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 357 } else { 358 can_id = (cf->can_id & CAN_SFF_MASK) << 18; 359 } 360 361 if (cf->can_id & CAN_RTR_FLAG) 362 ctrl |= FLEXCAN_MB_CNT_RTR; 363 364 if (cf->can_dlc > 0) { 365 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 366 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 367 } 368 if (cf->can_dlc > 3) { 369 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 370 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 371 } 372 373 can_put_echo_skb(skb, dev, 0); 374 375 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 376 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 377 378 return NETDEV_TX_OK; 379} 380 381static void do_bus_err(struct net_device *dev, 382 struct can_frame *cf, u32 reg_esr) 383{ 384 struct flexcan_priv *priv = netdev_priv(dev); 385 int rx_errors = 0, tx_errors = 0; 386 387 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 388 389 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 390 netdev_dbg(dev, "BIT1_ERR irq\n"); 391 cf->data[2] |= CAN_ERR_PROT_BIT1; 392 tx_errors = 1; 393 } 394 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 395 netdev_dbg(dev, "BIT0_ERR irq\n"); 396 cf->data[2] |= CAN_ERR_PROT_BIT0; 397 tx_errors = 1; 398 } 399 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 400 netdev_dbg(dev, "ACK_ERR irq\n"); 401 cf->can_id |= CAN_ERR_ACK; 402 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 403 tx_errors = 1; 404 } 405 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 406 netdev_dbg(dev, "CRC_ERR irq\n"); 407 cf->data[2] |= CAN_ERR_PROT_BIT; 408 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 409 rx_errors = 1; 410 } 411 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 412 netdev_dbg(dev, "FRM_ERR irq\n"); 413 cf->data[2] |= CAN_ERR_PROT_FORM; 414 rx_errors = 1; 415 } 416 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 417 netdev_dbg(dev, "STF_ERR irq\n"); 418 cf->data[2] |= CAN_ERR_PROT_STUFF; 419 rx_errors = 1; 420 } 421 422 priv->can.can_stats.bus_error++; 423 if (rx_errors) 424 dev->stats.rx_errors++; 425 if (tx_errors) 426 dev->stats.tx_errors++; 427} 428 429static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) 430{ 431 struct sk_buff *skb; 432 struct can_frame *cf; 433 434 skb = alloc_can_err_skb(dev, &cf); 435 if (unlikely(!skb)) 436 return 0; 437 438 do_bus_err(dev, cf, reg_esr); 439 netif_receive_skb(skb); 440 441 dev->stats.rx_packets++; 442 dev->stats.rx_bytes += cf->can_dlc; 443 444 return 1; 445} 446 447static void do_state(struct net_device *dev, 448 struct can_frame *cf, enum can_state new_state) 449{ 450 struct flexcan_priv *priv = netdev_priv(dev); 451 struct can_berr_counter bec; 452 453 flexcan_get_berr_counter(dev, &bec); 454 455 switch (priv->can.state) { 456 case CAN_STATE_ERROR_ACTIVE: 457 /* 458 * from: ERROR_ACTIVE 459 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 460 * => : there was a warning int 461 */ 462 if (new_state >= CAN_STATE_ERROR_WARNING && 463 new_state <= CAN_STATE_BUS_OFF) { 464 netdev_dbg(dev, "Error Warning IRQ\n"); 465 priv->can.can_stats.error_warning++; 466 467 cf->can_id |= CAN_ERR_CRTL; 468 cf->data[1] = (bec.txerr > bec.rxerr) ? 469 CAN_ERR_CRTL_TX_WARNING : 470 CAN_ERR_CRTL_RX_WARNING; 471 } 472 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 473 /* 474 * from: ERROR_ACTIVE, ERROR_WARNING 475 * to : ERROR_PASSIVE, BUS_OFF 476 * => : error passive int 477 */ 478 if (new_state >= CAN_STATE_ERROR_PASSIVE && 479 new_state <= CAN_STATE_BUS_OFF) { 480 netdev_dbg(dev, "Error Passive IRQ\n"); 481 priv->can.can_stats.error_passive++; 482 483 cf->can_id |= CAN_ERR_CRTL; 484 cf->data[1] = (bec.txerr > bec.rxerr) ? 485 CAN_ERR_CRTL_TX_PASSIVE : 486 CAN_ERR_CRTL_RX_PASSIVE; 487 } 488 break; 489 case CAN_STATE_BUS_OFF: 490 netdev_err(dev, "BUG! " 491 "hardware recovered automatically from BUS_OFF\n"); 492 break; 493 default: 494 break; 495 } 496 497 /* process state changes depending on the new state */ 498 switch (new_state) { 499 case CAN_STATE_ERROR_ACTIVE: 500 netdev_dbg(dev, "Error Active\n"); 501 cf->can_id |= CAN_ERR_PROT; 502 cf->data[2] = CAN_ERR_PROT_ACTIVE; 503 break; 504 case CAN_STATE_BUS_OFF: 505 cf->can_id |= CAN_ERR_BUSOFF; 506 can_bus_off(dev); 507 break; 508 default: 509 break; 510 } 511} 512 513static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) 514{ 515 struct flexcan_priv *priv = netdev_priv(dev); 516 struct sk_buff *skb; 517 struct can_frame *cf; 518 enum can_state new_state; 519 int flt; 520 521 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 522 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 523 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | 524 FLEXCAN_ESR_RX_WRN)))) 525 new_state = CAN_STATE_ERROR_ACTIVE; 526 else 527 new_state = CAN_STATE_ERROR_WARNING; 528 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) 529 new_state = CAN_STATE_ERROR_PASSIVE; 530 else 531 new_state = CAN_STATE_BUS_OFF; 532 533 /* state hasn't changed */ 534 if (likely(new_state == priv->can.state)) 535 return 0; 536 537 skb = alloc_can_err_skb(dev, &cf); 538 if (unlikely(!skb)) 539 return 0; 540 541 do_state(dev, cf, new_state); 542 priv->can.state = new_state; 543 netif_receive_skb(skb); 544 545 dev->stats.rx_packets++; 546 dev->stats.rx_bytes += cf->can_dlc; 547 548 return 1; 549} 550 551static void flexcan_read_fifo(const struct net_device *dev, 552 struct can_frame *cf) 553{ 554 const struct flexcan_priv *priv = netdev_priv(dev); 555 struct flexcan_regs __iomem *regs = priv->base; 556 struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; 557 u32 reg_ctrl, reg_id; 558 559 reg_ctrl = flexcan_read(&mb->can_ctrl); 560 reg_id = flexcan_read(&mb->can_id); 561 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 562 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 563 else 564 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; 565 566 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 567 cf->can_id |= CAN_RTR_FLAG; 568 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 569 570 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); 571 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); 572 573 /* mark as read */ 574 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 575 flexcan_read(®s->timer); 576} 577 578static int flexcan_read_frame(struct net_device *dev) 579{ 580 struct net_device_stats *stats = &dev->stats; 581 struct can_frame *cf; 582 struct sk_buff *skb; 583 584 skb = alloc_can_skb(dev, &cf); 585 if (unlikely(!skb)) { 586 stats->rx_dropped++; 587 return 0; 588 } 589 590 flexcan_read_fifo(dev, cf); 591 netif_receive_skb(skb); 592 593 stats->rx_packets++; 594 stats->rx_bytes += cf->can_dlc; 595 596 can_led_event(dev, CAN_LED_EVENT_RX); 597 598 return 1; 599} 600 601static int flexcan_poll(struct napi_struct *napi, int quota) 602{ 603 struct net_device *dev = napi->dev; 604 const struct flexcan_priv *priv = netdev_priv(dev); 605 struct flexcan_regs __iomem *regs = priv->base; 606 u32 reg_iflag1, reg_esr; 607 int work_done = 0; 608 609 /* 610 * The error bits are cleared on read, 611 * use saved value from irq handler. 612 */ 613 reg_esr = flexcan_read(®s->esr) | priv->reg_esr; 614 615 /* handle state changes */ 616 work_done += flexcan_poll_state(dev, reg_esr); 617 618 /* handle RX-FIFO */ 619 reg_iflag1 = flexcan_read(®s->iflag1); 620 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 621 work_done < quota) { 622 work_done += flexcan_read_frame(dev); 623 reg_iflag1 = flexcan_read(®s->iflag1); 624 } 625 626 /* report bus errors */ 627 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) 628 work_done += flexcan_poll_bus_err(dev, reg_esr); 629 630 if (work_done < quota) { 631 napi_complete(napi); 632 /* enable IRQs */ 633 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 634 flexcan_write(priv->reg_ctrl_default, ®s->ctrl); 635 } 636 637 return work_done; 638} 639 640static irqreturn_t flexcan_irq(int irq, void *dev_id) 641{ 642 struct net_device *dev = dev_id; 643 struct net_device_stats *stats = &dev->stats; 644 struct flexcan_priv *priv = netdev_priv(dev); 645 struct flexcan_regs __iomem *regs = priv->base; 646 u32 reg_iflag1, reg_esr; 647 648 reg_iflag1 = flexcan_read(®s->iflag1); 649 reg_esr = flexcan_read(®s->esr); 650 /* ACK all bus error and state change IRQ sources */ 651 if (reg_esr & FLEXCAN_ESR_ALL_INT) 652 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); 653 654 /* 655 * schedule NAPI in case of: 656 * - rx IRQ 657 * - state change IRQ 658 * - bus error IRQ and bus error reporting is activated 659 */ 660 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || 661 (reg_esr & FLEXCAN_ESR_ERR_STATE) || 662 flexcan_has_and_handle_berr(priv, reg_esr)) { 663 /* 664 * The error bits are cleared on read, 665 * save them for later use. 666 */ 667 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 668 flexcan_write(FLEXCAN_IFLAG_DEFAULT & 669 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); 670 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 671 ®s->ctrl); 672 napi_schedule(&priv->napi); 673 } 674 675 /* FIFO overflow */ 676 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 677 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); 678 dev->stats.rx_over_errors++; 679 dev->stats.rx_errors++; 680 } 681 682 /* transmission complete interrupt */ 683 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 684 stats->tx_bytes += can_get_echo_skb(dev, 0); 685 stats->tx_packets++; 686 can_led_event(dev, CAN_LED_EVENT_TX); 687 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); 688 netif_wake_queue(dev); 689 } 690 691 return IRQ_HANDLED; 692} 693 694static void flexcan_set_bittiming(struct net_device *dev) 695{ 696 const struct flexcan_priv *priv = netdev_priv(dev); 697 const struct can_bittiming *bt = &priv->can.bittiming; 698 struct flexcan_regs __iomem *regs = priv->base; 699 u32 reg; 700 701 reg = flexcan_read(®s->ctrl); 702 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 703 FLEXCAN_CTRL_RJW(0x3) | 704 FLEXCAN_CTRL_PSEG1(0x7) | 705 FLEXCAN_CTRL_PSEG2(0x7) | 706 FLEXCAN_CTRL_PROPSEG(0x7) | 707 FLEXCAN_CTRL_LPB | 708 FLEXCAN_CTRL_SMP | 709 FLEXCAN_CTRL_LOM); 710 711 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 712 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 713 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 714 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 715 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 716 717 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 718 reg |= FLEXCAN_CTRL_LPB; 719 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 720 reg |= FLEXCAN_CTRL_LOM; 721 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 722 reg |= FLEXCAN_CTRL_SMP; 723 724 netdev_info(dev, "writing ctrl=0x%08x\n", reg); 725 flexcan_write(reg, ®s->ctrl); 726 727 /* print chip status */ 728 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 729 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 730} 731 732/* 733 * flexcan_chip_start 734 * 735 * this functions is entered with clocks enabled 736 * 737 */ 738static int flexcan_chip_start(struct net_device *dev) 739{ 740 struct flexcan_priv *priv = netdev_priv(dev); 741 struct flexcan_regs __iomem *regs = priv->base; 742 int err; 743 u32 reg_mcr, reg_ctrl; 744 745 /* enable module */ 746 err = flexcan_chip_enable(priv); 747 if (err) 748 return err; 749 750 /* soft reset */ 751 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 752 udelay(10); 753 754 reg_mcr = flexcan_read(®s->mcr); 755 if (reg_mcr & FLEXCAN_MCR_SOFTRST) { 756 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n", 757 reg_mcr); 758 err = -ENODEV; 759 goto out; 760 } 761 762 flexcan_set_bittiming(dev); 763 764 /* 765 * MCR 766 * 767 * enable freeze 768 * enable fifo 769 * halt now 770 * only supervisor access 771 * enable warning int 772 * choose format C 773 * disable local echo 774 * 775 */ 776 reg_mcr = flexcan_read(®s->mcr); 777 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff); 778 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 779 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 780 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS | 781 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID); 782 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); 783 flexcan_write(reg_mcr, ®s->mcr); 784 785 /* 786 * CTRL 787 * 788 * disable timer sync feature 789 * 790 * disable auto busoff recovery 791 * transmit lowest buffer first 792 * 793 * enable tx and rx warning interrupt 794 * enable bus off interrupt 795 * (== FLEXCAN_CTRL_ERR_STATE) 796 */ 797 reg_ctrl = flexcan_read(®s->ctrl); 798 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 799 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 800 FLEXCAN_CTRL_ERR_STATE; 801 /* 802 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), 803 * on most Flexcan cores, too. Otherwise we don't get 804 * any error warning or passive interrupts. 805 */ 806 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE || 807 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 808 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; 809 810 /* save for later use */ 811 priv->reg_ctrl_default = reg_ctrl; 812 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 813 flexcan_write(reg_ctrl, ®s->ctrl); 814 815 /* Abort any pending TX, mark Mailbox as INACTIVE */ 816 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4), 817 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 818 819 /* acceptance mask/acceptance code (accept everything) */ 820 flexcan_write(0x0, ®s->rxgmask); 821 flexcan_write(0x0, ®s->rx14mask); 822 flexcan_write(0x0, ®s->rx15mask); 823 824 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) 825 flexcan_write(0x0, ®s->rxfgmask); 826 827 err = flexcan_transceiver_enable(priv); 828 if (err) 829 goto out; 830 831 /* synchronize with the can bus */ 832 reg_mcr = flexcan_read(®s->mcr); 833 reg_mcr &= ~FLEXCAN_MCR_HALT; 834 flexcan_write(reg_mcr, ®s->mcr); 835 836 priv->can.state = CAN_STATE_ERROR_ACTIVE; 837 838 /* enable FIFO interrupts */ 839 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 840 841 /* print chip status */ 842 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, 843 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 844 845 return 0; 846 847 out: 848 flexcan_chip_disable(priv); 849 return err; 850} 851 852/* 853 * flexcan_chip_stop 854 * 855 * this functions is entered with clocks enabled 856 * 857 */ 858static void flexcan_chip_stop(struct net_device *dev) 859{ 860 struct flexcan_priv *priv = netdev_priv(dev); 861 struct flexcan_regs __iomem *regs = priv->base; 862 u32 reg; 863 864 /* Disable + halt module */ 865 reg = flexcan_read(®s->mcr); 866 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT; 867 flexcan_write(reg, ®s->mcr); 868 869 /* Disable all interrupts */ 870 flexcan_write(0, ®s->imask1); 871 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 872 ®s->ctrl); 873 874 flexcan_transceiver_disable(priv); 875 priv->can.state = CAN_STATE_STOPPED; 876 877 return; 878} 879 880static int flexcan_open(struct net_device *dev) 881{ 882 struct flexcan_priv *priv = netdev_priv(dev); 883 int err; 884 885 err = clk_prepare_enable(priv->clk_ipg); 886 if (err) 887 return err; 888 889 err = clk_prepare_enable(priv->clk_per); 890 if (err) 891 goto out_disable_ipg; 892 893 err = open_candev(dev); 894 if (err) 895 goto out_disable_per; 896 897 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 898 if (err) 899 goto out_close; 900 901 /* start chip and queuing */ 902 err = flexcan_chip_start(dev); 903 if (err) 904 goto out_free_irq; 905 906 can_led_event(dev, CAN_LED_EVENT_OPEN); 907 908 napi_enable(&priv->napi); 909 netif_start_queue(dev); 910 911 return 0; 912 913 out_free_irq: 914 free_irq(dev->irq, dev); 915 out_close: 916 close_candev(dev); 917 out_disable_per: 918 clk_disable_unprepare(priv->clk_per); 919 out_disable_ipg: 920 clk_disable_unprepare(priv->clk_ipg); 921 922 return err; 923} 924 925static int flexcan_close(struct net_device *dev) 926{ 927 struct flexcan_priv *priv = netdev_priv(dev); 928 929 netif_stop_queue(dev); 930 napi_disable(&priv->napi); 931 flexcan_chip_stop(dev); 932 933 free_irq(dev->irq, dev); 934 clk_disable_unprepare(priv->clk_per); 935 clk_disable_unprepare(priv->clk_ipg); 936 937 close_candev(dev); 938 939 can_led_event(dev, CAN_LED_EVENT_STOP); 940 941 return 0; 942} 943 944static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 945{ 946 int err; 947 948 switch (mode) { 949 case CAN_MODE_START: 950 err = flexcan_chip_start(dev); 951 if (err) 952 return err; 953 954 netif_wake_queue(dev); 955 break; 956 957 default: 958 return -EOPNOTSUPP; 959 } 960 961 return 0; 962} 963 964static const struct net_device_ops flexcan_netdev_ops = { 965 .ndo_open = flexcan_open, 966 .ndo_stop = flexcan_close, 967 .ndo_start_xmit = flexcan_start_xmit, 968}; 969 970static int register_flexcandev(struct net_device *dev) 971{ 972 struct flexcan_priv *priv = netdev_priv(dev); 973 struct flexcan_regs __iomem *regs = priv->base; 974 u32 reg, err; 975 976 err = clk_prepare_enable(priv->clk_ipg); 977 if (err) 978 return err; 979 980 err = clk_prepare_enable(priv->clk_per); 981 if (err) 982 goto out_disable_ipg; 983 984 /* select "bus clock", chip must be disabled */ 985 err = flexcan_chip_disable(priv); 986 if (err) 987 goto out_disable_per; 988 reg = flexcan_read(®s->ctrl); 989 reg |= FLEXCAN_CTRL_CLK_SRC; 990 flexcan_write(reg, ®s->ctrl); 991 992 err = flexcan_chip_enable(priv); 993 if (err) 994 goto out_chip_disable; 995 996 /* set freeze, halt and activate FIFO, restrict register access */ 997 reg = flexcan_read(®s->mcr); 998 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 999 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 1000 flexcan_write(reg, ®s->mcr); 1001 1002 /* 1003 * Currently we only support newer versions of this core 1004 * featuring a RX FIFO. Older cores found on some Coldfire 1005 * derivates are not yet supported. 1006 */ 1007 reg = flexcan_read(®s->mcr); 1008 if (!(reg & FLEXCAN_MCR_FEN)) { 1009 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); 1010 err = -ENODEV; 1011 goto out_chip_disable; 1012 } 1013 1014 err = register_candev(dev); 1015 1016 /* disable core and turn off clocks */ 1017 out_chip_disable: 1018 flexcan_chip_disable(priv); 1019 out_disable_per: 1020 clk_disable_unprepare(priv->clk_per); 1021 out_disable_ipg: 1022 clk_disable_unprepare(priv->clk_ipg); 1023 1024 return err; 1025} 1026 1027static void unregister_flexcandev(struct net_device *dev) 1028{ 1029 unregister_candev(dev); 1030} 1031 1032static const struct of_device_id flexcan_of_match[] = { 1033 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, 1034 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, 1035 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, 1036 { /* sentinel */ }, 1037}; 1038MODULE_DEVICE_TABLE(of, flexcan_of_match); 1039 1040static const struct platform_device_id flexcan_id_table[] = { 1041 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, }, 1042 { /* sentinel */ }, 1043}; 1044MODULE_DEVICE_TABLE(platform, flexcan_id_table); 1045 1046static int flexcan_probe(struct platform_device *pdev) 1047{ 1048 const struct of_device_id *of_id; 1049 const struct flexcan_devtype_data *devtype_data; 1050 struct net_device *dev; 1051 struct flexcan_priv *priv; 1052 struct resource *mem; 1053 struct clk *clk_ipg = NULL, *clk_per = NULL; 1054 void __iomem *base; 1055 int err, irq; 1056 u32 clock_freq = 0; 1057 1058 if (pdev->dev.of_node) 1059 of_property_read_u32(pdev->dev.of_node, 1060 "clock-frequency", &clock_freq); 1061 1062 if (!clock_freq) { 1063 clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1064 if (IS_ERR(clk_ipg)) { 1065 dev_err(&pdev->dev, "no ipg clock defined\n"); 1066 return PTR_ERR(clk_ipg); 1067 } 1068 1069 clk_per = devm_clk_get(&pdev->dev, "per"); 1070 if (IS_ERR(clk_per)) { 1071 dev_err(&pdev->dev, "no per clock defined\n"); 1072 return PTR_ERR(clk_per); 1073 } 1074 clock_freq = clk_get_rate(clk_per); 1075 } 1076 1077 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1078 irq = platform_get_irq(pdev, 0); 1079 if (irq <= 0) 1080 return -ENODEV; 1081 1082 base = devm_ioremap_resource(&pdev->dev, mem); 1083 if (IS_ERR(base)) 1084 return PTR_ERR(base); 1085 1086 of_id = of_match_device(flexcan_of_match, &pdev->dev); 1087 if (of_id) { 1088 devtype_data = of_id->data; 1089 } else if (pdev->id_entry->driver_data) { 1090 devtype_data = (struct flexcan_devtype_data *) 1091 pdev->id_entry->driver_data; 1092 } else { 1093 return -ENODEV; 1094 } 1095 1096 dev = alloc_candev(sizeof(struct flexcan_priv), 1); 1097 if (!dev) 1098 return -ENOMEM; 1099 1100 dev->netdev_ops = &flexcan_netdev_ops; 1101 dev->irq = irq; 1102 dev->flags |= IFF_ECHO; 1103 1104 priv = netdev_priv(dev); 1105 priv->can.clock.freq = clock_freq; 1106 priv->can.bittiming_const = &flexcan_bittiming_const; 1107 priv->can.do_set_mode = flexcan_set_mode; 1108 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 1109 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1110 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 1111 CAN_CTRLMODE_BERR_REPORTING; 1112 priv->base = base; 1113 priv->dev = dev; 1114 priv->clk_ipg = clk_ipg; 1115 priv->clk_per = clk_per; 1116 priv->pdata = dev_get_platdata(&pdev->dev); 1117 priv->devtype_data = devtype_data; 1118 1119 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); 1120 if (IS_ERR(priv->reg_xceiver)) 1121 priv->reg_xceiver = NULL; 1122 1123 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); 1124 1125 platform_set_drvdata(pdev, dev); 1126 SET_NETDEV_DEV(dev, &pdev->dev); 1127 1128 err = register_flexcandev(dev); 1129 if (err) { 1130 dev_err(&pdev->dev, "registering netdev failed\n"); 1131 goto failed_register; 1132 } 1133 1134 devm_can_led_init(dev); 1135 1136 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1137 priv->base, dev->irq); 1138 1139 return 0; 1140 1141 failed_register: 1142 free_candev(dev); 1143 return err; 1144} 1145 1146static int flexcan_remove(struct platform_device *pdev) 1147{ 1148 struct net_device *dev = platform_get_drvdata(pdev); 1149 1150 unregister_flexcandev(dev); 1151 1152 free_candev(dev); 1153 1154 return 0; 1155} 1156 1157#ifdef CONFIG_PM_SLEEP 1158static int flexcan_suspend(struct device *device) 1159{ 1160 struct net_device *dev = dev_get_drvdata(device); 1161 struct flexcan_priv *priv = netdev_priv(dev); 1162 int err; 1163 1164 err = flexcan_chip_disable(priv); 1165 if (err) 1166 return err; 1167 1168 if (netif_running(dev)) { 1169 netif_stop_queue(dev); 1170 netif_device_detach(dev); 1171 } 1172 priv->can.state = CAN_STATE_SLEEPING; 1173 1174 return 0; 1175} 1176 1177static int flexcan_resume(struct device *device) 1178{ 1179 struct net_device *dev = dev_get_drvdata(device); 1180 struct flexcan_priv *priv = netdev_priv(dev); 1181 1182 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1183 if (netif_running(dev)) { 1184 netif_device_attach(dev); 1185 netif_start_queue(dev); 1186 } 1187 return flexcan_chip_enable(priv); 1188} 1189#endif /* CONFIG_PM_SLEEP */ 1190 1191static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume); 1192 1193static struct platform_driver flexcan_driver = { 1194 .driver = { 1195 .name = DRV_NAME, 1196 .owner = THIS_MODULE, 1197 .pm = &flexcan_pm_ops, 1198 .of_match_table = flexcan_of_match, 1199 }, 1200 .probe = flexcan_probe, 1201 .remove = flexcan_remove, 1202 .id_table = flexcan_id_table, 1203}; 1204 1205module_platform_driver(flexcan_driver); 1206 1207MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 1208 "Marc Kleine-Budde <kernel@pengutronix.de>"); 1209MODULE_LICENSE("GPL v2"); 1210MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 1211