flexcan.c revision fc05b884a31dbf259cc73cc856e634ec3acbebb6
1/* 2 * flexcan.c - FLEXCAN CAN controller driver 3 * 4 * Copyright (c) 2005-2006 Varma Electronics Oy 5 * Copyright (c) 2009 Sascha Hauer, Pengutronix 6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix 7 * 8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com> 9 * 10 * LICENCE: 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation version 2. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 */ 21 22#include <linux/netdevice.h> 23#include <linux/can.h> 24#include <linux/can/dev.h> 25#include <linux/can/error.h> 26#include <linux/can/led.h> 27#include <linux/clk.h> 28#include <linux/delay.h> 29#include <linux/if_arp.h> 30#include <linux/if_ether.h> 31#include <linux/interrupt.h> 32#include <linux/io.h> 33#include <linux/kernel.h> 34#include <linux/list.h> 35#include <linux/module.h> 36#include <linux/of.h> 37#include <linux/of_device.h> 38#include <linux/platform_device.h> 39#include <linux/regulator/consumer.h> 40 41#define DRV_NAME "flexcan" 42 43/* 8 for RX fifo and 2 error handling */ 44#define FLEXCAN_NAPI_WEIGHT (8 + 2) 45 46/* FLEXCAN module configuration register (CANMCR) bits */ 47#define FLEXCAN_MCR_MDIS BIT(31) 48#define FLEXCAN_MCR_FRZ BIT(30) 49#define FLEXCAN_MCR_FEN BIT(29) 50#define FLEXCAN_MCR_HALT BIT(28) 51#define FLEXCAN_MCR_NOT_RDY BIT(27) 52#define FLEXCAN_MCR_WAK_MSK BIT(26) 53#define FLEXCAN_MCR_SOFTRST BIT(25) 54#define FLEXCAN_MCR_FRZ_ACK BIT(24) 55#define FLEXCAN_MCR_SUPV BIT(23) 56#define FLEXCAN_MCR_SLF_WAK BIT(22) 57#define FLEXCAN_MCR_WRN_EN BIT(21) 58#define FLEXCAN_MCR_LPM_ACK BIT(20) 59#define FLEXCAN_MCR_WAK_SRC BIT(19) 60#define FLEXCAN_MCR_DOZE BIT(18) 61#define FLEXCAN_MCR_SRX_DIS BIT(17) 62#define FLEXCAN_MCR_BCC BIT(16) 63#define FLEXCAN_MCR_LPRIO_EN BIT(13) 64#define FLEXCAN_MCR_AEN BIT(12) 65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f) 66#define FLEXCAN_MCR_IDAM_A (0 << 8) 67#define FLEXCAN_MCR_IDAM_B (1 << 8) 68#define FLEXCAN_MCR_IDAM_C (2 << 8) 69#define FLEXCAN_MCR_IDAM_D (3 << 8) 70 71/* FLEXCAN control register (CANCTRL) bits */ 72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 76#define FLEXCAN_CTRL_BOFF_MSK BIT(15) 77#define FLEXCAN_CTRL_ERR_MSK BIT(14) 78#define FLEXCAN_CTRL_CLK_SRC BIT(13) 79#define FLEXCAN_CTRL_LPB BIT(12) 80#define FLEXCAN_CTRL_TWRN_MSK BIT(11) 81#define FLEXCAN_CTRL_RWRN_MSK BIT(10) 82#define FLEXCAN_CTRL_SMP BIT(7) 83#define FLEXCAN_CTRL_BOFF_REC BIT(6) 84#define FLEXCAN_CTRL_TSYN BIT(5) 85#define FLEXCAN_CTRL_LBUF BIT(4) 86#define FLEXCAN_CTRL_LOM BIT(3) 87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 89#define FLEXCAN_CTRL_ERR_STATE \ 90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 91 FLEXCAN_CTRL_BOFF_MSK) 92#define FLEXCAN_CTRL_ERR_ALL \ 93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 94 95/* FLEXCAN error and status register (ESR) bits */ 96#define FLEXCAN_ESR_TWRN_INT BIT(17) 97#define FLEXCAN_ESR_RWRN_INT BIT(16) 98#define FLEXCAN_ESR_BIT1_ERR BIT(15) 99#define FLEXCAN_ESR_BIT0_ERR BIT(14) 100#define FLEXCAN_ESR_ACK_ERR BIT(13) 101#define FLEXCAN_ESR_CRC_ERR BIT(12) 102#define FLEXCAN_ESR_FRM_ERR BIT(11) 103#define FLEXCAN_ESR_STF_ERR BIT(10) 104#define FLEXCAN_ESR_TX_WRN BIT(9) 105#define FLEXCAN_ESR_RX_WRN BIT(8) 106#define FLEXCAN_ESR_IDLE BIT(7) 107#define FLEXCAN_ESR_TXRX BIT(6) 108#define FLEXCAN_EST_FLT_CONF_SHIFT (4) 109#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 110#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 111#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 112#define FLEXCAN_ESR_BOFF_INT BIT(2) 113#define FLEXCAN_ESR_ERR_INT BIT(1) 114#define FLEXCAN_ESR_WAK_INT BIT(0) 115#define FLEXCAN_ESR_ERR_BUS \ 116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 119#define FLEXCAN_ESR_ERR_STATE \ 120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 121#define FLEXCAN_ESR_ERR_ALL \ 122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 123#define FLEXCAN_ESR_ALL_INT \ 124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ 125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) 126 127/* FLEXCAN interrupt flag register (IFLAG) bits */ 128#define FLEXCAN_TX_BUF_ID 8 129#define FLEXCAN_IFLAG_BUF(x) BIT(x) 130#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 131#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 132#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 133#define FLEXCAN_IFLAG_DEFAULT \ 134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ 135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) 136 137/* FLEXCAN message buffers */ 138#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) 139#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24) 140#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24) 141#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24) 142#define FLEXCAN_MB_CODE_RX_OVERRRUN (0x6 << 24) 143#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24) 144 145#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24) 146#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24) 147#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24) 148#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24) 149 150#define FLEXCAN_MB_CNT_SRR BIT(22) 151#define FLEXCAN_MB_CNT_IDE BIT(21) 152#define FLEXCAN_MB_CNT_RTR BIT(20) 153#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 154#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 155 156#define FLEXCAN_MB_CODE_MASK (0xf0ffffff) 157 158#define FLEXCAN_TIMEOUT_US (50) 159 160/* 161 * FLEXCAN hardware feature flags 162 * 163 * Below is some version info we got: 164 * SOC Version IP-Version Glitch- [TR]WRN_INT 165 * Filter? connected? 166 * MX25 FlexCAN2 03.00.00.00 no no 167 * MX28 FlexCAN2 03.00.04.00 yes yes 168 * MX35 FlexCAN2 03.00.00.00 no no 169 * MX53 FlexCAN2 03.00.00.00 yes no 170 * MX6s FlexCAN3 10.00.12.00 yes yes 171 * 172 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected. 173 */ 174#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */ 175#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */ 176 177/* Structure of the message buffer */ 178struct flexcan_mb { 179 u32 can_ctrl; 180 u32 can_id; 181 u32 data[2]; 182}; 183 184/* Structure of the hardware registers */ 185struct flexcan_regs { 186 u32 mcr; /* 0x00 */ 187 u32 ctrl; /* 0x04 */ 188 u32 timer; /* 0x08 */ 189 u32 _reserved1; /* 0x0c */ 190 u32 rxgmask; /* 0x10 */ 191 u32 rx14mask; /* 0x14 */ 192 u32 rx15mask; /* 0x18 */ 193 u32 ecr; /* 0x1c */ 194 u32 esr; /* 0x20 */ 195 u32 imask2; /* 0x24 */ 196 u32 imask1; /* 0x28 */ 197 u32 iflag2; /* 0x2c */ 198 u32 iflag1; /* 0x30 */ 199 u32 crl2; /* 0x34 */ 200 u32 esr2; /* 0x38 */ 201 u32 imeur; /* 0x3c */ 202 u32 lrfr; /* 0x40 */ 203 u32 crcr; /* 0x44 */ 204 u32 rxfgmask; /* 0x48 */ 205 u32 rxfir; /* 0x4c */ 206 u32 _reserved3[12]; 207 struct flexcan_mb cantxfg[64]; 208}; 209 210struct flexcan_devtype_data { 211 u32 features; /* hardware controller features */ 212}; 213 214struct flexcan_priv { 215 struct can_priv can; 216 struct net_device *dev; 217 struct napi_struct napi; 218 219 void __iomem *base; 220 u32 reg_esr; 221 u32 reg_ctrl_default; 222 223 struct clk *clk_ipg; 224 struct clk *clk_per; 225 struct flexcan_platform_data *pdata; 226 const struct flexcan_devtype_data *devtype_data; 227 struct regulator *reg_xceiver; 228}; 229 230static struct flexcan_devtype_data fsl_p1010_devtype_data = { 231 .features = FLEXCAN_HAS_BROKEN_ERR_STATE, 232}; 233static struct flexcan_devtype_data fsl_imx28_devtype_data; 234static struct flexcan_devtype_data fsl_imx6q_devtype_data = { 235 .features = FLEXCAN_HAS_V10_FEATURES, 236}; 237 238static const struct can_bittiming_const flexcan_bittiming_const = { 239 .name = DRV_NAME, 240 .tseg1_min = 4, 241 .tseg1_max = 16, 242 .tseg2_min = 2, 243 .tseg2_max = 8, 244 .sjw_max = 4, 245 .brp_min = 1, 246 .brp_max = 256, 247 .brp_inc = 1, 248}; 249 250/* 251 * Abstract off the read/write for arm versus ppc. This 252 * assumes that PPC uses big-endian registers and everything 253 * else uses little-endian registers, independent of CPU 254 * endianess. 255 */ 256#if defined(CONFIG_PPC) 257static inline u32 flexcan_read(void __iomem *addr) 258{ 259 return in_be32(addr); 260} 261 262static inline void flexcan_write(u32 val, void __iomem *addr) 263{ 264 out_be32(addr, val); 265} 266#else 267static inline u32 flexcan_read(void __iomem *addr) 268{ 269 return readl(addr); 270} 271 272static inline void flexcan_write(u32 val, void __iomem *addr) 273{ 274 writel(val, addr); 275} 276#endif 277 278static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv) 279{ 280 if (!priv->reg_xceiver) 281 return 0; 282 283 return regulator_enable(priv->reg_xceiver); 284} 285 286static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv) 287{ 288 if (!priv->reg_xceiver) 289 return 0; 290 291 return regulator_disable(priv->reg_xceiver); 292} 293 294static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, 295 u32 reg_esr) 296{ 297 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 298 (reg_esr & FLEXCAN_ESR_ERR_BUS); 299} 300 301static int flexcan_chip_enable(struct flexcan_priv *priv) 302{ 303 struct flexcan_regs __iomem *regs = priv->base; 304 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 305 u32 reg; 306 307 reg = flexcan_read(®s->mcr); 308 reg &= ~FLEXCAN_MCR_MDIS; 309 flexcan_write(reg, ®s->mcr); 310 311 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 312 udelay(10); 313 314 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK) 315 return -ETIMEDOUT; 316 317 return 0; 318} 319 320static int flexcan_chip_disable(struct flexcan_priv *priv) 321{ 322 struct flexcan_regs __iomem *regs = priv->base; 323 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 324 u32 reg; 325 326 reg = flexcan_read(®s->mcr); 327 reg |= FLEXCAN_MCR_MDIS; 328 flexcan_write(reg, ®s->mcr); 329 330 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 331 udelay(10); 332 333 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 334 return -ETIMEDOUT; 335 336 return 0; 337} 338 339static int flexcan_chip_freeze(struct flexcan_priv *priv) 340{ 341 struct flexcan_regs __iomem *regs = priv->base; 342 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate; 343 u32 reg; 344 345 reg = flexcan_read(®s->mcr); 346 reg |= FLEXCAN_MCR_HALT; 347 flexcan_write(reg, ®s->mcr); 348 349 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 350 udelay(100); 351 352 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 353 return -ETIMEDOUT; 354 355 return 0; 356} 357 358static int flexcan_chip_unfreeze(struct flexcan_priv *priv) 359{ 360 struct flexcan_regs __iomem *regs = priv->base; 361 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 362 u32 reg; 363 364 reg = flexcan_read(®s->mcr); 365 reg &= ~FLEXCAN_MCR_HALT; 366 flexcan_write(reg, ®s->mcr); 367 368 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 369 udelay(10); 370 371 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK) 372 return -ETIMEDOUT; 373 374 return 0; 375} 376 377static int flexcan_chip_softreset(struct flexcan_priv *priv) 378{ 379 struct flexcan_regs __iomem *regs = priv->base; 380 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 381 382 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 383 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)) 384 udelay(10); 385 386 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST) 387 return -ETIMEDOUT; 388 389 return 0; 390} 391 392static int flexcan_get_berr_counter(const struct net_device *dev, 393 struct can_berr_counter *bec) 394{ 395 const struct flexcan_priv *priv = netdev_priv(dev); 396 struct flexcan_regs __iomem *regs = priv->base; 397 u32 reg = flexcan_read(®s->ecr); 398 399 bec->txerr = (reg >> 0) & 0xff; 400 bec->rxerr = (reg >> 8) & 0xff; 401 402 return 0; 403} 404 405static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 406{ 407 const struct flexcan_priv *priv = netdev_priv(dev); 408 struct flexcan_regs __iomem *regs = priv->base; 409 struct can_frame *cf = (struct can_frame *)skb->data; 410 u32 can_id; 411 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); 412 413 if (can_dropped_invalid_skb(dev, skb)) 414 return NETDEV_TX_OK; 415 416 netif_stop_queue(dev); 417 418 if (cf->can_id & CAN_EFF_FLAG) { 419 can_id = cf->can_id & CAN_EFF_MASK; 420 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 421 } else { 422 can_id = (cf->can_id & CAN_SFF_MASK) << 18; 423 } 424 425 if (cf->can_id & CAN_RTR_FLAG) 426 ctrl |= FLEXCAN_MB_CNT_RTR; 427 428 if (cf->can_dlc > 0) { 429 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 430 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 431 } 432 if (cf->can_dlc > 3) { 433 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 434 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 435 } 436 437 can_put_echo_skb(skb, dev, 0); 438 439 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 440 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 441 442 return NETDEV_TX_OK; 443} 444 445static void do_bus_err(struct net_device *dev, 446 struct can_frame *cf, u32 reg_esr) 447{ 448 struct flexcan_priv *priv = netdev_priv(dev); 449 int rx_errors = 0, tx_errors = 0; 450 451 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 452 453 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 454 netdev_dbg(dev, "BIT1_ERR irq\n"); 455 cf->data[2] |= CAN_ERR_PROT_BIT1; 456 tx_errors = 1; 457 } 458 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 459 netdev_dbg(dev, "BIT0_ERR irq\n"); 460 cf->data[2] |= CAN_ERR_PROT_BIT0; 461 tx_errors = 1; 462 } 463 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 464 netdev_dbg(dev, "ACK_ERR irq\n"); 465 cf->can_id |= CAN_ERR_ACK; 466 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 467 tx_errors = 1; 468 } 469 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 470 netdev_dbg(dev, "CRC_ERR irq\n"); 471 cf->data[2] |= CAN_ERR_PROT_BIT; 472 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 473 rx_errors = 1; 474 } 475 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 476 netdev_dbg(dev, "FRM_ERR irq\n"); 477 cf->data[2] |= CAN_ERR_PROT_FORM; 478 rx_errors = 1; 479 } 480 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 481 netdev_dbg(dev, "STF_ERR irq\n"); 482 cf->data[2] |= CAN_ERR_PROT_STUFF; 483 rx_errors = 1; 484 } 485 486 priv->can.can_stats.bus_error++; 487 if (rx_errors) 488 dev->stats.rx_errors++; 489 if (tx_errors) 490 dev->stats.tx_errors++; 491} 492 493static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) 494{ 495 struct sk_buff *skb; 496 struct can_frame *cf; 497 498 skb = alloc_can_err_skb(dev, &cf); 499 if (unlikely(!skb)) 500 return 0; 501 502 do_bus_err(dev, cf, reg_esr); 503 netif_receive_skb(skb); 504 505 dev->stats.rx_packets++; 506 dev->stats.rx_bytes += cf->can_dlc; 507 508 return 1; 509} 510 511static void do_state(struct net_device *dev, 512 struct can_frame *cf, enum can_state new_state) 513{ 514 struct flexcan_priv *priv = netdev_priv(dev); 515 struct can_berr_counter bec; 516 517 flexcan_get_berr_counter(dev, &bec); 518 519 switch (priv->can.state) { 520 case CAN_STATE_ERROR_ACTIVE: 521 /* 522 * from: ERROR_ACTIVE 523 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 524 * => : there was a warning int 525 */ 526 if (new_state >= CAN_STATE_ERROR_WARNING && 527 new_state <= CAN_STATE_BUS_OFF) { 528 netdev_dbg(dev, "Error Warning IRQ\n"); 529 priv->can.can_stats.error_warning++; 530 531 cf->can_id |= CAN_ERR_CRTL; 532 cf->data[1] = (bec.txerr > bec.rxerr) ? 533 CAN_ERR_CRTL_TX_WARNING : 534 CAN_ERR_CRTL_RX_WARNING; 535 } 536 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 537 /* 538 * from: ERROR_ACTIVE, ERROR_WARNING 539 * to : ERROR_PASSIVE, BUS_OFF 540 * => : error passive int 541 */ 542 if (new_state >= CAN_STATE_ERROR_PASSIVE && 543 new_state <= CAN_STATE_BUS_OFF) { 544 netdev_dbg(dev, "Error Passive IRQ\n"); 545 priv->can.can_stats.error_passive++; 546 547 cf->can_id |= CAN_ERR_CRTL; 548 cf->data[1] = (bec.txerr > bec.rxerr) ? 549 CAN_ERR_CRTL_TX_PASSIVE : 550 CAN_ERR_CRTL_RX_PASSIVE; 551 } 552 break; 553 case CAN_STATE_BUS_OFF: 554 netdev_err(dev, "BUG! " 555 "hardware recovered automatically from BUS_OFF\n"); 556 break; 557 default: 558 break; 559 } 560 561 /* process state changes depending on the new state */ 562 switch (new_state) { 563 case CAN_STATE_ERROR_WARNING: 564 netdev_dbg(dev, "Error Warning\n"); 565 cf->can_id |= CAN_ERR_CRTL; 566 cf->data[1] = (bec.txerr > bec.rxerr) ? 567 CAN_ERR_CRTL_TX_WARNING : 568 CAN_ERR_CRTL_RX_WARNING; 569 break; 570 case CAN_STATE_ERROR_ACTIVE: 571 netdev_dbg(dev, "Error Active\n"); 572 cf->can_id |= CAN_ERR_PROT; 573 cf->data[2] = CAN_ERR_PROT_ACTIVE; 574 break; 575 case CAN_STATE_BUS_OFF: 576 cf->can_id |= CAN_ERR_BUSOFF; 577 can_bus_off(dev); 578 break; 579 default: 580 break; 581 } 582} 583 584static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) 585{ 586 struct flexcan_priv *priv = netdev_priv(dev); 587 struct sk_buff *skb; 588 struct can_frame *cf; 589 enum can_state new_state; 590 int flt; 591 592 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 593 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 594 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | 595 FLEXCAN_ESR_RX_WRN)))) 596 new_state = CAN_STATE_ERROR_ACTIVE; 597 else 598 new_state = CAN_STATE_ERROR_WARNING; 599 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) 600 new_state = CAN_STATE_ERROR_PASSIVE; 601 else 602 new_state = CAN_STATE_BUS_OFF; 603 604 /* state hasn't changed */ 605 if (likely(new_state == priv->can.state)) 606 return 0; 607 608 skb = alloc_can_err_skb(dev, &cf); 609 if (unlikely(!skb)) 610 return 0; 611 612 do_state(dev, cf, new_state); 613 priv->can.state = new_state; 614 netif_receive_skb(skb); 615 616 dev->stats.rx_packets++; 617 dev->stats.rx_bytes += cf->can_dlc; 618 619 return 1; 620} 621 622static void flexcan_read_fifo(const struct net_device *dev, 623 struct can_frame *cf) 624{ 625 const struct flexcan_priv *priv = netdev_priv(dev); 626 struct flexcan_regs __iomem *regs = priv->base; 627 struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; 628 u32 reg_ctrl, reg_id; 629 630 reg_ctrl = flexcan_read(&mb->can_ctrl); 631 reg_id = flexcan_read(&mb->can_id); 632 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 633 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 634 else 635 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; 636 637 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 638 cf->can_id |= CAN_RTR_FLAG; 639 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 640 641 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); 642 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); 643 644 /* mark as read */ 645 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 646 flexcan_read(®s->timer); 647} 648 649static int flexcan_read_frame(struct net_device *dev) 650{ 651 struct net_device_stats *stats = &dev->stats; 652 struct can_frame *cf; 653 struct sk_buff *skb; 654 655 skb = alloc_can_skb(dev, &cf); 656 if (unlikely(!skb)) { 657 stats->rx_dropped++; 658 return 0; 659 } 660 661 flexcan_read_fifo(dev, cf); 662 netif_receive_skb(skb); 663 664 stats->rx_packets++; 665 stats->rx_bytes += cf->can_dlc; 666 667 can_led_event(dev, CAN_LED_EVENT_RX); 668 669 return 1; 670} 671 672static int flexcan_poll(struct napi_struct *napi, int quota) 673{ 674 struct net_device *dev = napi->dev; 675 const struct flexcan_priv *priv = netdev_priv(dev); 676 struct flexcan_regs __iomem *regs = priv->base; 677 u32 reg_iflag1, reg_esr; 678 int work_done = 0; 679 680 /* 681 * The error bits are cleared on read, 682 * use saved value from irq handler. 683 */ 684 reg_esr = flexcan_read(®s->esr) | priv->reg_esr; 685 686 /* handle state changes */ 687 work_done += flexcan_poll_state(dev, reg_esr); 688 689 /* handle RX-FIFO */ 690 reg_iflag1 = flexcan_read(®s->iflag1); 691 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 692 work_done < quota) { 693 work_done += flexcan_read_frame(dev); 694 reg_iflag1 = flexcan_read(®s->iflag1); 695 } 696 697 /* report bus errors */ 698 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) 699 work_done += flexcan_poll_bus_err(dev, reg_esr); 700 701 if (work_done < quota) { 702 napi_complete(napi); 703 /* enable IRQs */ 704 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 705 flexcan_write(priv->reg_ctrl_default, ®s->ctrl); 706 } 707 708 return work_done; 709} 710 711static irqreturn_t flexcan_irq(int irq, void *dev_id) 712{ 713 struct net_device *dev = dev_id; 714 struct net_device_stats *stats = &dev->stats; 715 struct flexcan_priv *priv = netdev_priv(dev); 716 struct flexcan_regs __iomem *regs = priv->base; 717 u32 reg_iflag1, reg_esr; 718 719 reg_iflag1 = flexcan_read(®s->iflag1); 720 reg_esr = flexcan_read(®s->esr); 721 /* ACK all bus error and state change IRQ sources */ 722 if (reg_esr & FLEXCAN_ESR_ALL_INT) 723 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); 724 725 /* 726 * schedule NAPI in case of: 727 * - rx IRQ 728 * - state change IRQ 729 * - bus error IRQ and bus error reporting is activated 730 */ 731 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || 732 (reg_esr & FLEXCAN_ESR_ERR_STATE) || 733 flexcan_has_and_handle_berr(priv, reg_esr)) { 734 /* 735 * The error bits are cleared on read, 736 * save them for later use. 737 */ 738 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 739 flexcan_write(FLEXCAN_IFLAG_DEFAULT & 740 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); 741 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 742 ®s->ctrl); 743 napi_schedule(&priv->napi); 744 } 745 746 /* FIFO overflow */ 747 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 748 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); 749 dev->stats.rx_over_errors++; 750 dev->stats.rx_errors++; 751 } 752 753 /* transmission complete interrupt */ 754 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 755 stats->tx_bytes += can_get_echo_skb(dev, 0); 756 stats->tx_packets++; 757 can_led_event(dev, CAN_LED_EVENT_TX); 758 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); 759 netif_wake_queue(dev); 760 } 761 762 return IRQ_HANDLED; 763} 764 765static void flexcan_set_bittiming(struct net_device *dev) 766{ 767 const struct flexcan_priv *priv = netdev_priv(dev); 768 const struct can_bittiming *bt = &priv->can.bittiming; 769 struct flexcan_regs __iomem *regs = priv->base; 770 u32 reg; 771 772 reg = flexcan_read(®s->ctrl); 773 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 774 FLEXCAN_CTRL_RJW(0x3) | 775 FLEXCAN_CTRL_PSEG1(0x7) | 776 FLEXCAN_CTRL_PSEG2(0x7) | 777 FLEXCAN_CTRL_PROPSEG(0x7) | 778 FLEXCAN_CTRL_LPB | 779 FLEXCAN_CTRL_SMP | 780 FLEXCAN_CTRL_LOM); 781 782 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 783 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 784 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 785 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 786 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 787 788 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 789 reg |= FLEXCAN_CTRL_LPB; 790 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 791 reg |= FLEXCAN_CTRL_LOM; 792 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 793 reg |= FLEXCAN_CTRL_SMP; 794 795 netdev_info(dev, "writing ctrl=0x%08x\n", reg); 796 flexcan_write(reg, ®s->ctrl); 797 798 /* print chip status */ 799 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 800 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 801} 802 803/* 804 * flexcan_chip_start 805 * 806 * this functions is entered with clocks enabled 807 * 808 */ 809static int flexcan_chip_start(struct net_device *dev) 810{ 811 struct flexcan_priv *priv = netdev_priv(dev); 812 struct flexcan_regs __iomem *regs = priv->base; 813 int err; 814 u32 reg_mcr, reg_ctrl; 815 int i; 816 817 /* enable module */ 818 err = flexcan_chip_enable(priv); 819 if (err) 820 return err; 821 822 /* soft reset */ 823 err = flexcan_chip_softreset(priv); 824 if (err) 825 goto out_chip_disable; 826 827 flexcan_set_bittiming(dev); 828 829 /* 830 * MCR 831 * 832 * enable freeze 833 * enable fifo 834 * halt now 835 * only supervisor access 836 * enable warning int 837 * choose format C 838 * disable local echo 839 * 840 */ 841 reg_mcr = flexcan_read(®s->mcr); 842 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff); 843 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 844 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 845 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS | 846 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID); 847 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); 848 flexcan_write(reg_mcr, ®s->mcr); 849 850 /* 851 * CTRL 852 * 853 * disable timer sync feature 854 * 855 * disable auto busoff recovery 856 * transmit lowest buffer first 857 * 858 * enable tx and rx warning interrupt 859 * enable bus off interrupt 860 * (== FLEXCAN_CTRL_ERR_STATE) 861 */ 862 reg_ctrl = flexcan_read(®s->ctrl); 863 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 864 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 865 FLEXCAN_CTRL_ERR_STATE; 866 /* 867 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), 868 * on most Flexcan cores, too. Otherwise we don't get 869 * any error warning or passive interrupts. 870 */ 871 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE || 872 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 873 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; 874 else 875 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK; 876 877 /* save for later use */ 878 priv->reg_ctrl_default = reg_ctrl; 879 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 880 flexcan_write(reg_ctrl, ®s->ctrl); 881 882 /* clear and invalidate all mailboxes first */ 883 for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) { 884 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE, 885 ®s->cantxfg[i].can_ctrl); 886 } 887 888 /* mark TX mailbox as INACTIVE */ 889 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, 890 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 891 892 /* acceptance mask/acceptance code (accept everything) */ 893 flexcan_write(0x0, ®s->rxgmask); 894 flexcan_write(0x0, ®s->rx14mask); 895 flexcan_write(0x0, ®s->rx15mask); 896 897 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) 898 flexcan_write(0x0, ®s->rxfgmask); 899 900 err = flexcan_transceiver_enable(priv); 901 if (err) 902 goto out_chip_disable; 903 904 /* synchronize with the can bus */ 905 err = flexcan_chip_unfreeze(priv); 906 if (err) 907 goto out_transceiver_disable; 908 909 priv->can.state = CAN_STATE_ERROR_ACTIVE; 910 911 /* enable FIFO interrupts */ 912 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); 913 914 /* print chip status */ 915 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, 916 flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); 917 918 return 0; 919 920 out_transceiver_disable: 921 flexcan_transceiver_disable(priv); 922 out_chip_disable: 923 flexcan_chip_disable(priv); 924 return err; 925} 926 927/* 928 * flexcan_chip_stop 929 * 930 * this functions is entered with clocks enabled 931 * 932 */ 933static void flexcan_chip_stop(struct net_device *dev) 934{ 935 struct flexcan_priv *priv = netdev_priv(dev); 936 struct flexcan_regs __iomem *regs = priv->base; 937 938 /* freeze + disable module */ 939 flexcan_chip_freeze(priv); 940 flexcan_chip_disable(priv); 941 942 /* Disable all interrupts */ 943 flexcan_write(0, ®s->imask1); 944 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 945 ®s->ctrl); 946 947 flexcan_transceiver_disable(priv); 948 priv->can.state = CAN_STATE_STOPPED; 949 950 return; 951} 952 953static int flexcan_open(struct net_device *dev) 954{ 955 struct flexcan_priv *priv = netdev_priv(dev); 956 int err; 957 958 err = clk_prepare_enable(priv->clk_ipg); 959 if (err) 960 return err; 961 962 err = clk_prepare_enable(priv->clk_per); 963 if (err) 964 goto out_disable_ipg; 965 966 err = open_candev(dev); 967 if (err) 968 goto out_disable_per; 969 970 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 971 if (err) 972 goto out_close; 973 974 /* start chip and queuing */ 975 err = flexcan_chip_start(dev); 976 if (err) 977 goto out_free_irq; 978 979 can_led_event(dev, CAN_LED_EVENT_OPEN); 980 981 napi_enable(&priv->napi); 982 netif_start_queue(dev); 983 984 return 0; 985 986 out_free_irq: 987 free_irq(dev->irq, dev); 988 out_close: 989 close_candev(dev); 990 out_disable_per: 991 clk_disable_unprepare(priv->clk_per); 992 out_disable_ipg: 993 clk_disable_unprepare(priv->clk_ipg); 994 995 return err; 996} 997 998static int flexcan_close(struct net_device *dev) 999{ 1000 struct flexcan_priv *priv = netdev_priv(dev); 1001 1002 netif_stop_queue(dev); 1003 napi_disable(&priv->napi); 1004 flexcan_chip_stop(dev); 1005 1006 free_irq(dev->irq, dev); 1007 clk_disable_unprepare(priv->clk_per); 1008 clk_disable_unprepare(priv->clk_ipg); 1009 1010 close_candev(dev); 1011 1012 can_led_event(dev, CAN_LED_EVENT_STOP); 1013 1014 return 0; 1015} 1016 1017static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 1018{ 1019 int err; 1020 1021 switch (mode) { 1022 case CAN_MODE_START: 1023 err = flexcan_chip_start(dev); 1024 if (err) 1025 return err; 1026 1027 netif_wake_queue(dev); 1028 break; 1029 1030 default: 1031 return -EOPNOTSUPP; 1032 } 1033 1034 return 0; 1035} 1036 1037static const struct net_device_ops flexcan_netdev_ops = { 1038 .ndo_open = flexcan_open, 1039 .ndo_stop = flexcan_close, 1040 .ndo_start_xmit = flexcan_start_xmit, 1041 .ndo_change_mtu = can_change_mtu, 1042}; 1043 1044static int register_flexcandev(struct net_device *dev) 1045{ 1046 struct flexcan_priv *priv = netdev_priv(dev); 1047 struct flexcan_regs __iomem *regs = priv->base; 1048 u32 reg, err; 1049 1050 err = clk_prepare_enable(priv->clk_ipg); 1051 if (err) 1052 return err; 1053 1054 err = clk_prepare_enable(priv->clk_per); 1055 if (err) 1056 goto out_disable_ipg; 1057 1058 /* select "bus clock", chip must be disabled */ 1059 err = flexcan_chip_disable(priv); 1060 if (err) 1061 goto out_disable_per; 1062 reg = flexcan_read(®s->ctrl); 1063 reg |= FLEXCAN_CTRL_CLK_SRC; 1064 flexcan_write(reg, ®s->ctrl); 1065 1066 err = flexcan_chip_enable(priv); 1067 if (err) 1068 goto out_chip_disable; 1069 1070 /* set freeze, halt and activate FIFO, restrict register access */ 1071 reg = flexcan_read(®s->mcr); 1072 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 1073 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 1074 flexcan_write(reg, ®s->mcr); 1075 1076 /* 1077 * Currently we only support newer versions of this core 1078 * featuring a RX FIFO. Older cores found on some Coldfire 1079 * derivates are not yet supported. 1080 */ 1081 reg = flexcan_read(®s->mcr); 1082 if (!(reg & FLEXCAN_MCR_FEN)) { 1083 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); 1084 err = -ENODEV; 1085 goto out_chip_disable; 1086 } 1087 1088 err = register_candev(dev); 1089 1090 /* disable core and turn off clocks */ 1091 out_chip_disable: 1092 flexcan_chip_disable(priv); 1093 out_disable_per: 1094 clk_disable_unprepare(priv->clk_per); 1095 out_disable_ipg: 1096 clk_disable_unprepare(priv->clk_ipg); 1097 1098 return err; 1099} 1100 1101static void unregister_flexcandev(struct net_device *dev) 1102{ 1103 unregister_candev(dev); 1104} 1105 1106static const struct of_device_id flexcan_of_match[] = { 1107 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, 1108 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, 1109 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, 1110 { /* sentinel */ }, 1111}; 1112MODULE_DEVICE_TABLE(of, flexcan_of_match); 1113 1114static const struct platform_device_id flexcan_id_table[] = { 1115 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, }, 1116 { /* sentinel */ }, 1117}; 1118MODULE_DEVICE_TABLE(platform, flexcan_id_table); 1119 1120static int flexcan_probe(struct platform_device *pdev) 1121{ 1122 const struct of_device_id *of_id; 1123 const struct flexcan_devtype_data *devtype_data; 1124 struct net_device *dev; 1125 struct flexcan_priv *priv; 1126 struct resource *mem; 1127 struct clk *clk_ipg = NULL, *clk_per = NULL; 1128 void __iomem *base; 1129 int err, irq; 1130 u32 clock_freq = 0; 1131 1132 if (pdev->dev.of_node) 1133 of_property_read_u32(pdev->dev.of_node, 1134 "clock-frequency", &clock_freq); 1135 1136 if (!clock_freq) { 1137 clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1138 if (IS_ERR(clk_ipg)) { 1139 dev_err(&pdev->dev, "no ipg clock defined\n"); 1140 return PTR_ERR(clk_ipg); 1141 } 1142 1143 clk_per = devm_clk_get(&pdev->dev, "per"); 1144 if (IS_ERR(clk_per)) { 1145 dev_err(&pdev->dev, "no per clock defined\n"); 1146 return PTR_ERR(clk_per); 1147 } 1148 clock_freq = clk_get_rate(clk_per); 1149 } 1150 1151 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1152 irq = platform_get_irq(pdev, 0); 1153 if (irq <= 0) 1154 return -ENODEV; 1155 1156 base = devm_ioremap_resource(&pdev->dev, mem); 1157 if (IS_ERR(base)) 1158 return PTR_ERR(base); 1159 1160 of_id = of_match_device(flexcan_of_match, &pdev->dev); 1161 if (of_id) { 1162 devtype_data = of_id->data; 1163 } else if (platform_get_device_id(pdev)->driver_data) { 1164 devtype_data = (struct flexcan_devtype_data *) 1165 platform_get_device_id(pdev)->driver_data; 1166 } else { 1167 return -ENODEV; 1168 } 1169 1170 dev = alloc_candev(sizeof(struct flexcan_priv), 1); 1171 if (!dev) 1172 return -ENOMEM; 1173 1174 dev->netdev_ops = &flexcan_netdev_ops; 1175 dev->irq = irq; 1176 dev->flags |= IFF_ECHO; 1177 1178 priv = netdev_priv(dev); 1179 priv->can.clock.freq = clock_freq; 1180 priv->can.bittiming_const = &flexcan_bittiming_const; 1181 priv->can.do_set_mode = flexcan_set_mode; 1182 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 1183 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1184 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 1185 CAN_CTRLMODE_BERR_REPORTING; 1186 priv->base = base; 1187 priv->dev = dev; 1188 priv->clk_ipg = clk_ipg; 1189 priv->clk_per = clk_per; 1190 priv->pdata = dev_get_platdata(&pdev->dev); 1191 priv->devtype_data = devtype_data; 1192 1193 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); 1194 if (IS_ERR(priv->reg_xceiver)) 1195 priv->reg_xceiver = NULL; 1196 1197 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); 1198 1199 platform_set_drvdata(pdev, dev); 1200 SET_NETDEV_DEV(dev, &pdev->dev); 1201 1202 err = register_flexcandev(dev); 1203 if (err) { 1204 dev_err(&pdev->dev, "registering netdev failed\n"); 1205 goto failed_register; 1206 } 1207 1208 devm_can_led_init(dev); 1209 1210 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1211 priv->base, dev->irq); 1212 1213 return 0; 1214 1215 failed_register: 1216 free_candev(dev); 1217 return err; 1218} 1219 1220static int flexcan_remove(struct platform_device *pdev) 1221{ 1222 struct net_device *dev = platform_get_drvdata(pdev); 1223 struct flexcan_priv *priv = netdev_priv(dev); 1224 1225 unregister_flexcandev(dev); 1226 netif_napi_del(&priv->napi); 1227 free_candev(dev); 1228 1229 return 0; 1230} 1231 1232static int __maybe_unused flexcan_suspend(struct device *device) 1233{ 1234 struct net_device *dev = dev_get_drvdata(device); 1235 struct flexcan_priv *priv = netdev_priv(dev); 1236 int err; 1237 1238 err = flexcan_chip_disable(priv); 1239 if (err) 1240 return err; 1241 1242 if (netif_running(dev)) { 1243 netif_stop_queue(dev); 1244 netif_device_detach(dev); 1245 } 1246 priv->can.state = CAN_STATE_SLEEPING; 1247 1248 return 0; 1249} 1250 1251static int __maybe_unused flexcan_resume(struct device *device) 1252{ 1253 struct net_device *dev = dev_get_drvdata(device); 1254 struct flexcan_priv *priv = netdev_priv(dev); 1255 1256 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1257 if (netif_running(dev)) { 1258 netif_device_attach(dev); 1259 netif_start_queue(dev); 1260 } 1261 return flexcan_chip_enable(priv); 1262} 1263 1264static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume); 1265 1266static struct platform_driver flexcan_driver = { 1267 .driver = { 1268 .name = DRV_NAME, 1269 .owner = THIS_MODULE, 1270 .pm = &flexcan_pm_ops, 1271 .of_match_table = flexcan_of_match, 1272 }, 1273 .probe = flexcan_probe, 1274 .remove = flexcan_remove, 1275 .id_table = flexcan_id_table, 1276}; 1277 1278module_platform_driver(flexcan_driver); 1279 1280MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 1281 "Marc Kleine-Budde <kernel@pengutronix.de>"); 1282MODULE_LICENSE("GPL v2"); 1283MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 1284