mpc5xxx_can.c revision 05780d9808f72dc28a5c3602e11a7c53aef972ad 
1/*
2 * CAN bus driver for the Freescale MPC5xxx embedded CPU.
3 *
4 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
5 *                         Varma Electronics Oy
6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
7 * Copyright (C) 2009 Wolfram Sang, Pengutronix <w.sang@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the version 2 of the GNU General Public License
11 * as published by the Free Software Foundation
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/platform_device.h>
26#include <linux/netdevice.h>
27#include <linux/can/dev.h>
28#include <linux/of_platform.h>
29#include <sysdev/fsl_soc.h>
30#include <linux/clk.h>
31#include <linux/io.h>
32#include <asm/mpc52xx.h>
33
34#include "mscan.h"
35
36#define DRV_NAME "mpc5xxx_can"
37
38struct mpc5xxx_can_data {
39	unsigned int type;
40	u32 (*get_clock)(struct platform_device *ofdev, const char *clock_name,
41			 int *mscan_clksrc);
42	void (*put_clock)(struct platform_device *ofdev);
43};
44
45#ifdef CONFIG_PPC_MPC52xx
46static struct of_device_id mpc52xx_cdm_ids[] = {
47	{ .compatible = "fsl,mpc5200-cdm", },
48	{}
49};
50
51static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
52				 const char *clock_name, int *mscan_clksrc)
53{
54	unsigned int pvr;
55	struct mpc52xx_cdm  __iomem *cdm;
56	struct device_node *np_cdm;
57	unsigned int freq;
58	u32 val;
59
60	pvr = mfspr(SPRN_PVR);
61
62	/*
63	 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock
64	 * (IP_CLK) can be selected as MSCAN clock source. According to
65	 * the MPC5200 user's manual, the oscillator clock is the better
66	 * choice as it has less jitter. For this reason, it is selected
67	 * by default. Unfortunately, it can not be selected for the old
68	 * MPC5200 Rev. A chips due to a hardware bug (check errata).
69	 */
70	if (clock_name && strcmp(clock_name, "ip") == 0)
71		*mscan_clksrc = MSCAN_CLKSRC_BUS;
72	else
73		*mscan_clksrc = MSCAN_CLKSRC_XTAL;
74
75	freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
76	if (!freq)
77		return 0;
78
79	if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011)
80		return freq;
81
82	/* Determine SYS_XTAL_IN frequency from the clock domain settings */
83	np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids);
84	if (!np_cdm) {
85		dev_err(&ofdev->dev, "can't get clock node!\n");
86		return 0;
87	}
88	cdm = of_iomap(np_cdm, 0);
89
90	if (in_8(&cdm->ipb_clk_sel) & 0x1)
91		freq *= 2;
92	val = in_be32(&cdm->rstcfg);
93
94	freq *= (val & (1 << 5)) ? 8 : 4;
95	freq /= (val & (1 << 6)) ? 12 : 16;
96
97	of_node_put(np_cdm);
98	iounmap(cdm);
99
100	return freq;
101}
102#else /* !CONFIG_PPC_MPC52xx */
103static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
104				 const char *clock_name, int *mscan_clksrc)
105{
106	return 0;
107}
108#endif /* CONFIG_PPC_MPC52xx */
109
110#ifdef CONFIG_PPC_MPC512x
111struct mpc512x_clockctl {
112	u32 spmr;		/* System PLL Mode Reg */
113	u32 sccr[2];		/* System Clk Ctrl Reg 1 & 2 */
114	u32 scfr1;		/* System Clk Freq Reg 1 */
115	u32 scfr2;		/* System Clk Freq Reg 2 */
116	u32 reserved;
117	u32 bcr;		/* Bread Crumb Reg */
118	u32 pccr[12];		/* PSC Clk Ctrl Reg 0-11 */
119	u32 spccr;		/* SPDIF Clk Ctrl Reg */
120	u32 cccr;		/* CFM Clk Ctrl Reg */
121	u32 dccr;		/* DIU Clk Cnfg Reg */
122	u32 mccr[4];		/* MSCAN Clk Ctrl Reg 1-3 */
123};
124
125static struct of_device_id mpc512x_clock_ids[] = {
126	{ .compatible = "fsl,mpc5121-clock", },
127	{}
128};
129
130static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
131				 const char *clock_name, int *mscan_clksrc)
132{
133	struct mpc512x_clockctl __iomem *clockctl;
134	struct device_node *np_clock;
135	struct clk *sys_clk, *ref_clk;
136	int plen, clockidx, clocksrc = -1;
137	u32 sys_freq, val, clockdiv = 1, freq = 0;
138	const u32 *pval;
139
140	np_clock = of_find_matching_node(NULL, mpc512x_clock_ids);
141	if (!np_clock) {
142		dev_err(&ofdev->dev, "couldn't find clock node\n");
143		return 0;
144	}
145	clockctl = of_iomap(np_clock, 0);
146	if (!clockctl) {
147		dev_err(&ofdev->dev, "couldn't map clock registers\n");
148		goto exit_put;
149	}
150
151	/* Determine the MSCAN device index from the peripheral's
152	 * physical address. Register address offsets against the
153	 * IMMR base are:  0x1300, 0x1380, 0x2300, 0x2380
154	 */
155	pval = of_get_property(ofdev->dev.of_node, "reg", &plen);
156	BUG_ON(!pval || plen < sizeof(*pval));
157	clockidx = (*pval & 0x80) ? 1 : 0;
158	if (*pval & 0x2000)
159		clockidx += 2;
160
161	/*
162	 * Clock source and divider selection: 3 different clock sources
163	 * can be selected: "ip", "ref" or "sys". For the latter two, a
164	 * clock divider can be defined as well. If the clock source is
165	 * not specified by the device tree, we first try to find an
166	 * optimal CAN source clock based on the system clock. If that
167	 * is not posslible, the reference clock will be used.
168	 */
169	if (clock_name && !strcmp(clock_name, "ip")) {
170		*mscan_clksrc = MSCAN_CLKSRC_IPS;
171		freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
172	} else {
173		*mscan_clksrc = MSCAN_CLKSRC_BUS;
174
175		pval = of_get_property(ofdev->dev.of_node,
176				       "fsl,mscan-clock-divider", &plen);
177		if (pval && plen == sizeof(*pval))
178			clockdiv = *pval;
179		if (!clockdiv)
180			clockdiv = 1;
181
182		if (!clock_name || !strcmp(clock_name, "sys")) {
183			sys_clk = devm_clk_get(&ofdev->dev, "sys_clk");
184			if (IS_ERR(sys_clk)) {
185				dev_err(&ofdev->dev, "couldn't get sys_clk\n");
186				goto exit_unmap;
187			}
188			/* Get and round up/down sys clock rate */
189			sys_freq = 1000000 *
190				((clk_get_rate(sys_clk) + 499999) / 1000000);
191
192			if (!clock_name) {
193				/* A multiple of 16 MHz would be optimal */
194				if ((sys_freq % 16000000) == 0) {
195					clocksrc = 0;
196					clockdiv = sys_freq / 16000000;
197					freq = sys_freq / clockdiv;
198				}
199			} else {
200				clocksrc = 0;
201				freq = sys_freq / clockdiv;
202			}
203		}
204
205		if (clocksrc < 0) {
206			ref_clk = devm_clk_get(&ofdev->dev, "ref_clk");
207			if (IS_ERR(ref_clk)) {
208				dev_err(&ofdev->dev, "couldn't get ref_clk\n");
209				goto exit_unmap;
210			}
211			clocksrc = 1;
212			freq = clk_get_rate(ref_clk) / clockdiv;
213		}
214	}
215
216	/* Disable clock */
217	out_be32(&clockctl->mccr[clockidx], 0x0);
218	if (clocksrc >= 0) {
219		/* Set source and divider */
220		val = (clocksrc << 14) | ((clockdiv - 1) << 17);
221		out_be32(&clockctl->mccr[clockidx], val);
222		/* Enable clock */
223		out_be32(&clockctl->mccr[clockidx], val | 0x10000);
224	}
225
226	/* Enable MSCAN clock domain */
227	val = in_be32(&clockctl->sccr[1]);
228	if (!(val & (1 << 25)))
229		out_be32(&clockctl->sccr[1], val | (1 << 25));
230
231	dev_dbg(&ofdev->dev, "using '%s' with frequency divider %d\n",
232		*mscan_clksrc == MSCAN_CLKSRC_IPS ? "ips_clk" :
233		clocksrc == 1 ? "ref_clk" : "sys_clk", clockdiv);
234
235exit_unmap:
236	iounmap(clockctl);
237exit_put:
238	of_node_put(np_clock);
239	return freq;
240}
241#else /* !CONFIG_PPC_MPC512x */
242static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
243				 const char *clock_name, int *mscan_clksrc)
244{
245	return 0;
246}
247#endif /* CONFIG_PPC_MPC512x */
248
249static const struct of_device_id mpc5xxx_can_table[];
250static int mpc5xxx_can_probe(struct platform_device *ofdev)
251{
252	const struct of_device_id *match;
253	const struct mpc5xxx_can_data *data;
254	struct device_node *np = ofdev->dev.of_node;
255	struct net_device *dev;
256	struct mscan_priv *priv;
257	void __iomem *base;
258	const char *clock_name = NULL;
259	int irq, mscan_clksrc = 0;
260	int err = -ENOMEM;
261
262	match = of_match_device(mpc5xxx_can_table, &ofdev->dev);
263	if (!match)
264		return -EINVAL;
265	data = match->data;
266
267	base = of_iomap(np, 0);
268	if (!base) {
269		dev_err(&ofdev->dev, "couldn't ioremap\n");
270		return err;
271	}
272
273	irq = irq_of_parse_and_map(np, 0);
274	if (!irq) {
275		dev_err(&ofdev->dev, "no irq found\n");
276		err = -ENODEV;
277		goto exit_unmap_mem;
278	}
279
280	dev = alloc_mscandev();
281	if (!dev)
282		goto exit_dispose_irq;
283	platform_set_drvdata(ofdev, dev);
284	SET_NETDEV_DEV(dev, &ofdev->dev);
285
286	priv = netdev_priv(dev);
287	priv->reg_base = base;
288	dev->irq = irq;
289
290	clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL);
291
292	BUG_ON(!data);
293	priv->type = data->type;
294	priv->can.clock.freq = data->get_clock(ofdev, clock_name,
295					       &mscan_clksrc);
296	if (!priv->can.clock.freq) {
297		dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n");
298		goto exit_free_mscan;
299	}
300
301	err = register_mscandev(dev, mscan_clksrc);
302	if (err) {
303		dev_err(&ofdev->dev, "registering %s failed (err=%d)\n",
304			DRV_NAME, err);
305		goto exit_free_mscan;
306	}
307
308	dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n",
309		 priv->reg_base, dev->irq, priv->can.clock.freq);
310
311	return 0;
312
313exit_free_mscan:
314	free_candev(dev);
315exit_dispose_irq:
316	irq_dispose_mapping(irq);
317exit_unmap_mem:
318	iounmap(base);
319
320	return err;
321}
322
323static int mpc5xxx_can_remove(struct platform_device *ofdev)
324{
325	const struct of_device_id *match;
326	const struct mpc5xxx_can_data *data;
327	struct net_device *dev = platform_get_drvdata(ofdev);
328	struct mscan_priv *priv = netdev_priv(dev);
329
330	match = of_match_device(mpc5xxx_can_table, &ofdev->dev);
331	data = match ? match->data : NULL;
332
333	unregister_mscandev(dev);
334	if (data && data->put_clock)
335		data->put_clock(ofdev);
336	iounmap(priv->reg_base);
337	irq_dispose_mapping(dev->irq);
338	free_candev(dev);
339
340	return 0;
341}
342
343#ifdef CONFIG_PM
344static struct mscan_regs saved_regs;
345static int mpc5xxx_can_suspend(struct platform_device *ofdev, pm_message_t state)
346{
347	struct net_device *dev = platform_get_drvdata(ofdev);
348	struct mscan_priv *priv = netdev_priv(dev);
349	struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
350
351	_memcpy_fromio(&saved_regs, regs, sizeof(*regs));
352
353	return 0;
354}
355
356static int mpc5xxx_can_resume(struct platform_device *ofdev)
357{
358	struct net_device *dev = platform_get_drvdata(ofdev);
359	struct mscan_priv *priv = netdev_priv(dev);
360	struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
361
362	regs->canctl0 |= MSCAN_INITRQ;
363	while (!(regs->canctl1 & MSCAN_INITAK))
364		udelay(10);
365
366	regs->canctl1 = saved_regs.canctl1;
367	regs->canbtr0 = saved_regs.canbtr0;
368	regs->canbtr1 = saved_regs.canbtr1;
369	regs->canidac = saved_regs.canidac;
370
371	/* restore masks, buffers etc. */
372	_memcpy_toio(&regs->canidar1_0, (void *)&saved_regs.canidar1_0,
373		     sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0));
374
375	regs->canctl0 &= ~MSCAN_INITRQ;
376	regs->cantbsel = saved_regs.cantbsel;
377	regs->canrier = saved_regs.canrier;
378	regs->cantier = saved_regs.cantier;
379	regs->canctl0 = saved_regs.canctl0;
380
381	return 0;
382}
383#endif
384
385static const struct mpc5xxx_can_data mpc5200_can_data = {
386	.type = MSCAN_TYPE_MPC5200,
387	.get_clock = mpc52xx_can_get_clock,
388};
389
390static const struct mpc5xxx_can_data mpc5121_can_data = {
391	.type = MSCAN_TYPE_MPC5121,
392	.get_clock = mpc512x_can_get_clock,
393};
394
395static const struct of_device_id mpc5xxx_can_table[] = {
396	{ .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, },
397	/* Note that only MPC5121 Rev. 2 (and later) is supported */
398	{ .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, },
399	{},
400};
401MODULE_DEVICE_TABLE(of, mpc5xxx_can_table);
402
403static struct platform_driver mpc5xxx_can_driver = {
404	.driver = {
405		.name = "mpc5xxx_can",
406		.owner = THIS_MODULE,
407		.of_match_table = mpc5xxx_can_table,
408	},
409	.probe = mpc5xxx_can_probe,
410	.remove = mpc5xxx_can_remove,
411#ifdef CONFIG_PM
412	.suspend = mpc5xxx_can_suspend,
413	.resume = mpc5xxx_can_resume,
414#endif
415};
416
417module_platform_driver(mpc5xxx_can_driver);
418
419MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
420MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver");
421MODULE_LICENSE("GPL v2");
422