mpc5xxx_can.c revision 5ac22504f928db34a3a75ab67bf1eef82b91ef0b
1/* 2 * CAN bus driver for the Freescale MPC5xxx embedded CPU. 3 * 4 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>, 5 * Varma Electronics Oy 6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com> 7 * Copyright (C) 2009 Wolfram Sang, Pengutronix <w.sang@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23#include <linux/kernel.h> 24#include <linux/module.h> 25#include <linux/interrupt.h> 26#include <linux/platform_device.h> 27#include <linux/netdevice.h> 28#include <linux/can/dev.h> 29#include <linux/of_platform.h> 30#include <sysdev/fsl_soc.h> 31#include <linux/clk.h> 32#include <linux/io.h> 33#include <asm/mpc52xx.h> 34 35#include "mscan.h" 36 37#define DRV_NAME "mpc5xxx_can" 38 39struct mpc5xxx_can_data { 40 unsigned int type; 41 u32 (*get_clock)(struct platform_device *ofdev, const char *clock_name, 42 int *mscan_clksrc); 43 void (*put_clock)(struct platform_device *ofdev); 44}; 45 46#ifdef CONFIG_PPC_MPC52xx 47static struct of_device_id mpc52xx_cdm_ids[] = { 48 { .compatible = "fsl,mpc5200-cdm", }, 49 {} 50}; 51 52static u32 mpc52xx_can_get_clock(struct platform_device *ofdev, 53 const char *clock_name, int *mscan_clksrc) 54{ 55 unsigned int pvr; 56 struct mpc52xx_cdm __iomem *cdm; 57 struct device_node *np_cdm; 58 unsigned int freq; 59 u32 val; 60 61 pvr = mfspr(SPRN_PVR); 62 63 /* 64 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock 65 * (IP_CLK) can be selected as MSCAN clock source. According to 66 * the MPC5200 user's manual, the oscillator clock is the better 67 * choice as it has less jitter. For this reason, it is selected 68 * by default. Unfortunately, it can not be selected for the old 69 * MPC5200 Rev. A chips due to a hardware bug (check errata). 70 */ 71 if (clock_name && strcmp(clock_name, "ip") == 0) 72 *mscan_clksrc = MSCAN_CLKSRC_BUS; 73 else 74 *mscan_clksrc = MSCAN_CLKSRC_XTAL; 75 76 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); 77 if (!freq) 78 return 0; 79 80 if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011) 81 return freq; 82 83 /* Determine SYS_XTAL_IN frequency from the clock domain settings */ 84 np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids); 85 if (!np_cdm) { 86 dev_err(&ofdev->dev, "can't get clock node!\n"); 87 return 0; 88 } 89 cdm = of_iomap(np_cdm, 0); 90 91 if (in_8(&cdm->ipb_clk_sel) & 0x1) 92 freq *= 2; 93 val = in_be32(&cdm->rstcfg); 94 95 freq *= (val & (1 << 5)) ? 8 : 4; 96 freq /= (val & (1 << 6)) ? 12 : 16; 97 98 of_node_put(np_cdm); 99 iounmap(cdm); 100 101 return freq; 102} 103#else /* !CONFIG_PPC_MPC52xx */ 104static u32 mpc52xx_can_get_clock(struct platform_device *ofdev, 105 const char *clock_name, int *mscan_clksrc) 106{ 107 return 0; 108} 109#endif /* CONFIG_PPC_MPC52xx */ 110 111#ifdef CONFIG_PPC_MPC512x 112 113#if IS_ENABLED(CONFIG_COMMON_CLK) 114 115static u32 mpc512x_can_get_clock(struct platform_device *ofdev, 116 const char *clock_source, int *mscan_clksrc) 117{ 118 struct device_node *np; 119 u32 clockdiv; 120 enum { 121 CLK_FROM_AUTO, 122 CLK_FROM_IPS, 123 CLK_FROM_SYS, 124 CLK_FROM_REF, 125 } clk_from; 126 struct clk *clk_in, *clk_can; 127 unsigned long freq_calc; 128 struct mscan_priv *priv; 129 struct clk *clk_ipg; 130 131 /* the caller passed in the clock source spec that was read from 132 * the device tree, get the optional clock divider as well 133 */ 134 np = ofdev->dev.of_node; 135 clockdiv = 1; 136 of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv); 137 dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n", 138 clock_source ? clock_source : "<NULL>", clockdiv); 139 140 /* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to 141 * get set, and the 'ips' clock is the input to the MSCAN 142 * component 143 * 144 * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC] 145 * bit needs to get cleared, an optional clock-divider may have 146 * been specified (the default value is 1), the appropriate 147 * MSCAN related MCLK is the input to the MSCAN component 148 * 149 * in the absence of a clock-source spec, first an optimal clock 150 * gets determined based on the 'sys' clock, if that fails the 151 * 'ref' clock is used 152 */ 153 clk_from = CLK_FROM_AUTO; 154 if (clock_source) { 155 /* interpret the device tree's spec for the clock source */ 156 if (!strcmp(clock_source, "ip")) 157 clk_from = CLK_FROM_IPS; 158 else if (!strcmp(clock_source, "sys")) 159 clk_from = CLK_FROM_SYS; 160 else if (!strcmp(clock_source, "ref")) 161 clk_from = CLK_FROM_REF; 162 else 163 goto err_invalid; 164 dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from); 165 } 166 if (clk_from == CLK_FROM_AUTO) { 167 /* no spec so far, try the 'sys' clock; round to the 168 * next MHz and see if we can get a multiple of 16MHz 169 */ 170 dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n"); 171 clk_in = devm_clk_get(&ofdev->dev, "sys"); 172 if (IS_ERR(clk_in)) 173 goto err_notavail; 174 freq_calc = clk_get_rate(clk_in); 175 freq_calc += 499999; 176 freq_calc /= 1000000; 177 freq_calc *= 1000000; 178 if ((freq_calc % 16000000) == 0) { 179 clk_from = CLK_FROM_SYS; 180 clockdiv = freq_calc / 16000000; 181 dev_dbg(&ofdev->dev, 182 "clk fit, sys[%lu] div[%d] freq[%lu]\n", 183 freq_calc, clockdiv, freq_calc / clockdiv); 184 } 185 } 186 if (clk_from == CLK_FROM_AUTO) { 187 /* no spec so far, use the 'ref' clock */ 188 dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n"); 189 clk_in = devm_clk_get(&ofdev->dev, "ref"); 190 if (IS_ERR(clk_in)) 191 goto err_notavail; 192 clk_from = CLK_FROM_REF; 193 freq_calc = clk_get_rate(clk_in); 194 dev_dbg(&ofdev->dev, 195 "clk fit, ref[%lu] (no div) freq[%lu]\n", 196 freq_calc, freq_calc); 197 } 198 199 /* select IPS or MCLK as the MSCAN input (returned to the caller), 200 * setup the MCLK mux source and rate if applicable, apply the 201 * optionally specified or derived above divider, and determine 202 * the actual resulting clock rate to return to the caller 203 */ 204 switch (clk_from) { 205 case CLK_FROM_IPS: 206 clk_can = devm_clk_get(&ofdev->dev, "ips"); 207 if (IS_ERR(clk_can)) 208 goto err_notavail; 209 priv = netdev_priv(dev_get_drvdata(&ofdev->dev)); 210 priv->clk_can = clk_can; 211 freq_calc = clk_get_rate(clk_can); 212 *mscan_clksrc = MSCAN_CLKSRC_IPS; 213 dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n", 214 *mscan_clksrc, freq_calc); 215 break; 216 case CLK_FROM_SYS: 217 case CLK_FROM_REF: 218 clk_can = devm_clk_get(&ofdev->dev, "mclk"); 219 if (IS_ERR(clk_can)) 220 goto err_notavail; 221 priv = netdev_priv(dev_get_drvdata(&ofdev->dev)); 222 priv->clk_can = clk_can; 223 if (clk_from == CLK_FROM_SYS) 224 clk_in = devm_clk_get(&ofdev->dev, "sys"); 225 if (clk_from == CLK_FROM_REF) 226 clk_in = devm_clk_get(&ofdev->dev, "ref"); 227 if (IS_ERR(clk_in)) 228 goto err_notavail; 229 clk_set_parent(clk_can, clk_in); 230 freq_calc = clk_get_rate(clk_in); 231 freq_calc /= clockdiv; 232 clk_set_rate(clk_can, freq_calc); 233 freq_calc = clk_get_rate(clk_can); 234 *mscan_clksrc = MSCAN_CLKSRC_BUS; 235 dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n", 236 *mscan_clksrc, freq_calc); 237 break; 238 default: 239 goto err_invalid; 240 } 241 242 /* the above clk_can item is used for the bitrate, access to 243 * the peripheral's register set needs the clk_ipg item 244 */ 245 clk_ipg = devm_clk_get(&ofdev->dev, "ipg"); 246 if (IS_ERR(clk_ipg)) 247 goto err_notavail_ipg; 248 if (clk_prepare_enable(clk_ipg)) 249 goto err_notavail_ipg; 250 priv = netdev_priv(dev_get_drvdata(&ofdev->dev)); 251 priv->clk_ipg = clk_ipg; 252 253 /* return the determined clock source rate */ 254 return freq_calc; 255 256err_invalid: 257 dev_err(&ofdev->dev, "invalid clock source specification\n"); 258 /* clock source rate could not get determined */ 259 return 0; 260 261err_notavail: 262 dev_err(&ofdev->dev, "cannot acquire or setup bitrate clock source\n"); 263 /* clock source rate could not get determined */ 264 return 0; 265 266err_notavail_ipg: 267 dev_err(&ofdev->dev, "cannot acquire or setup register clock\n"); 268 /* clock source rate could not get determined */ 269 return 0; 270} 271 272static void mpc512x_can_put_clock(struct platform_device *ofdev) 273{ 274 struct mscan_priv *priv; 275 276 priv = netdev_priv(dev_get_drvdata(&ofdev->dev)); 277 if (priv->clk_ipg) 278 clk_disable_unprepare(priv->clk_ipg); 279} 280 281#else /* COMMON_CLK */ 282 283struct mpc512x_clockctl { 284 u32 spmr; /* System PLL Mode Reg */ 285 u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */ 286 u32 scfr1; /* System Clk Freq Reg 1 */ 287 u32 scfr2; /* System Clk Freq Reg 2 */ 288 u32 reserved; 289 u32 bcr; /* Bread Crumb Reg */ 290 u32 pccr[12]; /* PSC Clk Ctrl Reg 0-11 */ 291 u32 spccr; /* SPDIF Clk Ctrl Reg */ 292 u32 cccr; /* CFM Clk Ctrl Reg */ 293 u32 dccr; /* DIU Clk Cnfg Reg */ 294 u32 mccr[4]; /* MSCAN Clk Ctrl Reg 1-3 */ 295}; 296 297static struct of_device_id mpc512x_clock_ids[] = { 298 { .compatible = "fsl,mpc5121-clock", }, 299 {} 300}; 301 302static u32 mpc512x_can_get_clock(struct platform_device *ofdev, 303 const char *clock_name, int *mscan_clksrc) 304{ 305 struct mpc512x_clockctl __iomem *clockctl; 306 struct device_node *np_clock; 307 struct clk *sys_clk, *ref_clk; 308 int plen, clockidx, clocksrc = -1; 309 u32 sys_freq, val, clockdiv = 1, freq = 0; 310 const u32 *pval; 311 312 np_clock = of_find_matching_node(NULL, mpc512x_clock_ids); 313 if (!np_clock) { 314 dev_err(&ofdev->dev, "couldn't find clock node\n"); 315 return 0; 316 } 317 clockctl = of_iomap(np_clock, 0); 318 if (!clockctl) { 319 dev_err(&ofdev->dev, "couldn't map clock registers\n"); 320 goto exit_put; 321 } 322 323 /* Determine the MSCAN device index from the peripheral's 324 * physical address. Register address offsets against the 325 * IMMR base are: 0x1300, 0x1380, 0x2300, 0x2380 326 */ 327 pval = of_get_property(ofdev->dev.of_node, "reg", &plen); 328 BUG_ON(!pval || plen < sizeof(*pval)); 329 clockidx = (*pval & 0x80) ? 1 : 0; 330 if (*pval & 0x2000) 331 clockidx += 2; 332 333 /* 334 * Clock source and divider selection: 3 different clock sources 335 * can be selected: "ip", "ref" or "sys". For the latter two, a 336 * clock divider can be defined as well. If the clock source is 337 * not specified by the device tree, we first try to find an 338 * optimal CAN source clock based on the system clock. If that 339 * is not posslible, the reference clock will be used. 340 */ 341 if (clock_name && !strcmp(clock_name, "ip")) { 342 *mscan_clksrc = MSCAN_CLKSRC_IPS; 343 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); 344 } else { 345 *mscan_clksrc = MSCAN_CLKSRC_BUS; 346 347 pval = of_get_property(ofdev->dev.of_node, 348 "fsl,mscan-clock-divider", &plen); 349 if (pval && plen == sizeof(*pval)) 350 clockdiv = *pval; 351 if (!clockdiv) 352 clockdiv = 1; 353 354 if (!clock_name || !strcmp(clock_name, "sys")) { 355 sys_clk = devm_clk_get(&ofdev->dev, "sys_clk"); 356 if (IS_ERR(sys_clk)) { 357 dev_err(&ofdev->dev, "couldn't get sys_clk\n"); 358 goto exit_unmap; 359 } 360 /* Get and round up/down sys clock rate */ 361 sys_freq = 1000000 * 362 ((clk_get_rate(sys_clk) + 499999) / 1000000); 363 364 if (!clock_name) { 365 /* A multiple of 16 MHz would be optimal */ 366 if ((sys_freq % 16000000) == 0) { 367 clocksrc = 0; 368 clockdiv = sys_freq / 16000000; 369 freq = sys_freq / clockdiv; 370 } 371 } else { 372 clocksrc = 0; 373 freq = sys_freq / clockdiv; 374 } 375 } 376 377 if (clocksrc < 0) { 378 ref_clk = devm_clk_get(&ofdev->dev, "ref_clk"); 379 if (IS_ERR(ref_clk)) { 380 dev_err(&ofdev->dev, "couldn't get ref_clk\n"); 381 goto exit_unmap; 382 } 383 clocksrc = 1; 384 freq = clk_get_rate(ref_clk) / clockdiv; 385 } 386 } 387 388 /* Disable clock */ 389 out_be32(&clockctl->mccr[clockidx], 0x0); 390 if (clocksrc >= 0) { 391 /* Set source and divider */ 392 val = (clocksrc << 14) | ((clockdiv - 1) << 17); 393 out_be32(&clockctl->mccr[clockidx], val); 394 /* Enable clock */ 395 out_be32(&clockctl->mccr[clockidx], val | 0x10000); 396 } 397 398 /* Enable MSCAN clock domain */ 399 val = in_be32(&clockctl->sccr[1]); 400 if (!(val & (1 << 25))) 401 out_be32(&clockctl->sccr[1], val | (1 << 25)); 402 403 dev_dbg(&ofdev->dev, "using '%s' with frequency divider %d\n", 404 *mscan_clksrc == MSCAN_CLKSRC_IPS ? "ips_clk" : 405 clocksrc == 1 ? "ref_clk" : "sys_clk", clockdiv); 406 407exit_unmap: 408 iounmap(clockctl); 409exit_put: 410 of_node_put(np_clock); 411 return freq; 412} 413 414#define mpc512x_can_put_clock NULL 415 416#endif /* COMMON_CLK */ 417 418#else /* !CONFIG_PPC_MPC512x */ 419static u32 mpc512x_can_get_clock(struct platform_device *ofdev, 420 const char *clock_name, int *mscan_clksrc) 421{ 422 return 0; 423} 424#define mpc512x_can_put_clock NULL 425#endif /* CONFIG_PPC_MPC512x */ 426 427static const struct of_device_id mpc5xxx_can_table[]; 428static int mpc5xxx_can_probe(struct platform_device *ofdev) 429{ 430 const struct of_device_id *match; 431 const struct mpc5xxx_can_data *data; 432 struct device_node *np = ofdev->dev.of_node; 433 struct net_device *dev; 434 struct mscan_priv *priv; 435 void __iomem *base; 436 const char *clock_name = NULL; 437 int irq, mscan_clksrc = 0; 438 int err = -ENOMEM; 439 440 match = of_match_device(mpc5xxx_can_table, &ofdev->dev); 441 if (!match) 442 return -EINVAL; 443 data = match->data; 444 445 base = of_iomap(np, 0); 446 if (!base) { 447 dev_err(&ofdev->dev, "couldn't ioremap\n"); 448 return err; 449 } 450 451 irq = irq_of_parse_and_map(np, 0); 452 if (!irq) { 453 dev_err(&ofdev->dev, "no irq found\n"); 454 err = -ENODEV; 455 goto exit_unmap_mem; 456 } 457 458 dev = alloc_mscandev(); 459 if (!dev) 460 goto exit_dispose_irq; 461 platform_set_drvdata(ofdev, dev); 462 SET_NETDEV_DEV(dev, &ofdev->dev); 463 464 priv = netdev_priv(dev); 465 priv->reg_base = base; 466 dev->irq = irq; 467 468 clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL); 469 470 BUG_ON(!data); 471 priv->type = data->type; 472 priv->can.clock.freq = data->get_clock(ofdev, clock_name, 473 &mscan_clksrc); 474 if (!priv->can.clock.freq) { 475 dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n"); 476 goto exit_free_mscan; 477 } 478 479 err = register_mscandev(dev, mscan_clksrc); 480 if (err) { 481 dev_err(&ofdev->dev, "registering %s failed (err=%d)\n", 482 DRV_NAME, err); 483 goto exit_free_mscan; 484 } 485 486 dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n", 487 priv->reg_base, dev->irq, priv->can.clock.freq); 488 489 return 0; 490 491exit_free_mscan: 492 free_candev(dev); 493exit_dispose_irq: 494 irq_dispose_mapping(irq); 495exit_unmap_mem: 496 iounmap(base); 497 498 return err; 499} 500 501static int mpc5xxx_can_remove(struct platform_device *ofdev) 502{ 503 const struct of_device_id *match; 504 const struct mpc5xxx_can_data *data; 505 struct net_device *dev = platform_get_drvdata(ofdev); 506 struct mscan_priv *priv = netdev_priv(dev); 507 508 match = of_match_device(mpc5xxx_can_table, &ofdev->dev); 509 data = match ? match->data : NULL; 510 511 unregister_mscandev(dev); 512 if (data && data->put_clock) 513 data->put_clock(ofdev); 514 iounmap(priv->reg_base); 515 irq_dispose_mapping(dev->irq); 516 free_candev(dev); 517 518 return 0; 519} 520 521#ifdef CONFIG_PM 522static struct mscan_regs saved_regs; 523static int mpc5xxx_can_suspend(struct platform_device *ofdev, pm_message_t state) 524{ 525 struct net_device *dev = platform_get_drvdata(ofdev); 526 struct mscan_priv *priv = netdev_priv(dev); 527 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 528 529 _memcpy_fromio(&saved_regs, regs, sizeof(*regs)); 530 531 return 0; 532} 533 534static int mpc5xxx_can_resume(struct platform_device *ofdev) 535{ 536 struct net_device *dev = platform_get_drvdata(ofdev); 537 struct mscan_priv *priv = netdev_priv(dev); 538 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 539 540 regs->canctl0 |= MSCAN_INITRQ; 541 while (!(regs->canctl1 & MSCAN_INITAK)) 542 udelay(10); 543 544 regs->canctl1 = saved_regs.canctl1; 545 regs->canbtr0 = saved_regs.canbtr0; 546 regs->canbtr1 = saved_regs.canbtr1; 547 regs->canidac = saved_regs.canidac; 548 549 /* restore masks, buffers etc. */ 550 _memcpy_toio(®s->canidar1_0, (void *)&saved_regs.canidar1_0, 551 sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0)); 552 553 regs->canctl0 &= ~MSCAN_INITRQ; 554 regs->cantbsel = saved_regs.cantbsel; 555 regs->canrier = saved_regs.canrier; 556 regs->cantier = saved_regs.cantier; 557 regs->canctl0 = saved_regs.canctl0; 558 559 return 0; 560} 561#endif 562 563static const struct mpc5xxx_can_data mpc5200_can_data = { 564 .type = MSCAN_TYPE_MPC5200, 565 .get_clock = mpc52xx_can_get_clock, 566 /* .put_clock not applicable */ 567}; 568 569static const struct mpc5xxx_can_data mpc5121_can_data = { 570 .type = MSCAN_TYPE_MPC5121, 571 .get_clock = mpc512x_can_get_clock, 572 .put_clock = mpc512x_can_put_clock, 573}; 574 575static const struct of_device_id mpc5xxx_can_table[] = { 576 { .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, }, 577 /* Note that only MPC5121 Rev. 2 (and later) is supported */ 578 { .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, }, 579 {}, 580}; 581MODULE_DEVICE_TABLE(of, mpc5xxx_can_table); 582 583static struct platform_driver mpc5xxx_can_driver = { 584 .driver = { 585 .name = "mpc5xxx_can", 586 .owner = THIS_MODULE, 587 .of_match_table = mpc5xxx_can_table, 588 }, 589 .probe = mpc5xxx_can_probe, 590 .remove = mpc5xxx_can_remove, 591#ifdef CONFIG_PM 592 .suspend = mpc5xxx_can_suspend, 593 .resume = mpc5xxx_can_resume, 594#endif 595}; 596 597module_platform_driver(mpc5xxx_can_driver); 598 599MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>"); 600MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver"); 601MODULE_LICENSE("GPL v2"); 602