mpc5xxx_can.c revision bf3af54732bea5894ccc2cbde3ab566f0af7da56
1/* 2 * CAN bus driver for the Freescale MPC5xxx embedded CPU. 3 * 4 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>, 5 * Varma Electronics Oy 6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com> 7 * Copyright (C) 2009 Wolfram Sang, Pengutronix <w.sang@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23#include <linux/kernel.h> 24#include <linux/module.h> 25#include <linux/interrupt.h> 26#include <linux/platform_device.h> 27#include <linux/netdevice.h> 28#include <linux/can.h> 29#include <linux/can/dev.h> 30#include <linux/of_platform.h> 31#include <sysdev/fsl_soc.h> 32#include <linux/clk.h> 33#include <linux/io.h> 34#include <asm/mpc52xx.h> 35 36#include "mscan.h" 37 38#define DRV_NAME "mpc5xxx_can" 39 40struct mpc5xxx_can_data { 41 unsigned int type; 42 u32 (*get_clock)(struct of_device *ofdev, const char *clock_name, 43 int *mscan_clksrc); 44}; 45 46#ifdef CONFIG_PPC_MPC5200 47static struct of_device_id __devinitdata mpc52xx_cdm_ids[] = { 48 { .compatible = "fsl,mpc5200-cdm", }, 49 {} 50}; 51 52static u32 __devinit mpc52xx_can_get_clock(struct of_device *ofdev, 53 const char *clock_name, 54 int *mscan_clksrc) 55{ 56 unsigned int pvr; 57 struct mpc52xx_cdm __iomem *cdm; 58 struct device_node *np_cdm; 59 unsigned int freq; 60 u32 val; 61 62 pvr = mfspr(SPRN_PVR); 63 64 /* 65 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock 66 * (IP_CLK) can be selected as MSCAN clock source. According to 67 * the MPC5200 user's manual, the oscillator clock is the better 68 * choice as it has less jitter. For this reason, it is selected 69 * by default. Unfortunately, it can not be selected for the old 70 * MPC5200 Rev. A chips due to a hardware bug (check errata). 71 */ 72 if (clock_name && strcmp(clock_name, "ip") == 0) 73 *mscan_clksrc = MSCAN_CLKSRC_BUS; 74 else 75 *mscan_clksrc = MSCAN_CLKSRC_XTAL; 76 77 freq = mpc5xxx_get_bus_frequency(ofdev->node); 78 if (!freq) 79 return 0; 80 81 if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011) 82 return freq; 83 84 /* Determine SYS_XTAL_IN frequency from the clock domain settings */ 85 np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids); 86 if (!np_cdm) { 87 dev_err(&of->dev, "can't get clock node!\n"); 88 return 0; 89 } 90 cdm = of_iomap(np_cdm, 0); 91 92 if (in_8(&cdm->ipb_clk_sel) & 0x1) 93 freq *= 2; 94 val = in_be32(&cdm->rstcfg); 95 96 freq *= (val & (1 << 5)) ? 8 : 4; 97 freq /= (val & (1 << 6)) ? 12 : 16; 98 99 of_node_put(np_cdm); 100 iounmap(cdm); 101 102 return freq; 103} 104#else /* !CONFIG_PPC_MPC5200 */ 105static u32 __devinit mpc52xx_can_get_clock(struct of_device *ofdev, 106 const char *clock_name, 107 int *mscan_clksrc) 108{ 109 return 0; 110} 111#endif /* CONFIG_PPC_MPC5200 */ 112 113#ifdef CONFIG_PPC_MPC512x 114struct mpc512x_clockctl { 115 u32 spmr; /* System PLL Mode Reg */ 116 u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */ 117 u32 scfr1; /* System Clk Freq Reg 1 */ 118 u32 scfr2; /* System Clk Freq Reg 2 */ 119 u32 reserved; 120 u32 bcr; /* Bread Crumb Reg */ 121 u32 pccr[12]; /* PSC Clk Ctrl Reg 0-11 */ 122 u32 spccr; /* SPDIF Clk Ctrl Reg */ 123 u32 cccr; /* CFM Clk Ctrl Reg */ 124 u32 dccr; /* DIU Clk Cnfg Reg */ 125 u32 mccr[4]; /* MSCAN Clk Ctrl Reg 1-3 */ 126}; 127 128static struct of_device_id __devinitdata mpc512x_clock_ids[] = { 129 { .compatible = "fsl,mpc5121-clock", }, 130 {} 131}; 132 133static u32 __devinit mpc512x_can_get_clock(struct of_device *ofdev, 134 const char *clock_name, 135 int *mscan_clksrc) 136{ 137 struct mpc512x_clockctl __iomem *clockctl; 138 struct device_node *np_clock; 139 struct clk *sys_clk, *ref_clk; 140 int plen, clockidx, clocksrc = -1; 141 u32 sys_freq, val, clockdiv = 1, freq = 0; 142 const u32 *pval; 143 144 np_clock = of_find_matching_node(NULL, mpc512x_clock_ids); 145 if (!np_clock) { 146 dev_err(&ofdev->dev, "couldn't find clock node\n"); 147 return -ENODEV; 148 } 149 clockctl = of_iomap(np_clock, 0); 150 if (!clockctl) { 151 dev_err(&ofdev->dev, "couldn't map clock registers\n"); 152 return 0; 153 } 154 155 /* Determine the MSCAN device index from the physical address */ 156 pval = of_get_property(ofdev->node, "reg", &plen); 157 BUG_ON(!pval || plen < sizeof(*pval)); 158 clockidx = (*pval & 0x80) ? 1 : 0; 159 if (*pval & 0x2000) 160 clockidx += 2; 161 162 /* 163 * Clock source and divider selection: 3 different clock sources 164 * can be selected: "ip", "ref" or "sys". For the latter two, a 165 * clock divider can be defined as well. If the clock source is 166 * not specified by the device tree, we first try to find an 167 * optimal CAN source clock based on the system clock. If that 168 * is not posslible, the reference clock will be used. 169 */ 170 if (clock_name && !strcmp(clock_name, "ip")) { 171 *mscan_clksrc = MSCAN_CLKSRC_IPS; 172 freq = mpc5xxx_get_bus_frequency(ofdev->node); 173 } else { 174 *mscan_clksrc = MSCAN_CLKSRC_BUS; 175 176 pval = of_get_property(ofdev->node, 177 "fsl,mscan-clock-divider", &plen); 178 if (pval && plen == sizeof(*pval)) 179 clockdiv = *pval; 180 if (!clockdiv) 181 clockdiv = 1; 182 183 if (!clock_name || !strcmp(clock_name, "sys")) { 184 sys_clk = clk_get(&ofdev->dev, "sys_clk"); 185 if (!sys_clk) { 186 dev_err(&ofdev->dev, "couldn't get sys_clk\n"); 187 goto exit_unmap; 188 } 189 /* Get and round up/down sys clock rate */ 190 sys_freq = 1000000 * 191 ((clk_get_rate(sys_clk) + 499999) / 1000000); 192 193 if (!clock_name) { 194 /* A multiple of 16 MHz would be optimal */ 195 if ((sys_freq % 16000000) == 0) { 196 clocksrc = 0; 197 clockdiv = sys_freq / 16000000; 198 freq = sys_freq / clockdiv; 199 } 200 } else { 201 clocksrc = 0; 202 freq = sys_freq / clockdiv; 203 } 204 } 205 206 if (clocksrc < 0) { 207 ref_clk = clk_get(&ofdev->dev, "ref_clk"); 208 if (!ref_clk) { 209 dev_err(&ofdev->dev, "couldn't get ref_clk\n"); 210 goto exit_unmap; 211 } 212 clocksrc = 1; 213 freq = clk_get_rate(ref_clk) / clockdiv; 214 } 215 } 216 217 /* Disable clock */ 218 out_be32(&clockctl->mccr[clockidx], 0x0); 219 if (clocksrc >= 0) { 220 /* Set source and divider */ 221 val = (clocksrc << 14) | ((clockdiv - 1) << 17); 222 out_be32(&clockctl->mccr[clockidx], val); 223 /* Enable clock */ 224 out_be32(&clockctl->mccr[clockidx], val | 0x10000); 225 } 226 227 /* Enable MSCAN clock domain */ 228 val = in_be32(&clockctl->sccr[1]); 229 if (!(val & (1 << 25))) 230 out_be32(&clockctl->sccr[1], val | (1 << 25)); 231 232 dev_dbg(&ofdev->dev, "using '%s' with frequency divider %d\n", 233 *mscan_clksrc == MSCAN_CLKSRC_IPS ? "ips_clk" : 234 clocksrc == 1 ? "ref_clk" : "sys_clk", clockdiv); 235 236exit_unmap: 237 of_node_put(np_clock); 238 iounmap(clockctl); 239 240 return freq; 241} 242#else /* !CONFIG_PPC_MPC512x */ 243static u32 __devinit mpc512x_can_get_clock(struct of_device *ofdev, 244 const char *clock_name, 245 int *mscan_clksrc) 246{ 247 return 0; 248} 249#endif /* CONFIG_PPC_MPC512x */ 250 251static int __devinit mpc5xxx_can_probe(struct of_device *ofdev, 252 const struct of_device_id *id) 253{ 254 struct mpc5xxx_can_data *data = (struct mpc5xxx_can_data *)id->data; 255 struct device_node *np = ofdev->node; 256 struct net_device *dev; 257 struct mscan_priv *priv; 258 void __iomem *base; 259 const char *clock_name = NULL; 260 int irq, mscan_clksrc = 0; 261 int err = -ENOMEM; 262 263 base = of_iomap(np, 0); 264 if (!base) { 265 dev_err(&ofdev->dev, "couldn't ioremap\n"); 266 return err; 267 } 268 269 irq = irq_of_parse_and_map(np, 0); 270 if (!irq) { 271 dev_err(&ofdev->dev, "no irq found\n"); 272 err = -ENODEV; 273 goto exit_unmap_mem; 274 } 275 276 dev = alloc_mscandev(); 277 if (!dev) 278 goto exit_dispose_irq; 279 280 priv = netdev_priv(dev); 281 priv->reg_base = base; 282 dev->irq = irq; 283 284 clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL); 285 286 BUG_ON(!data); 287 priv->type = data->type; 288 priv->can.clock.freq = data->get_clock(ofdev, clock_name, 289 &mscan_clksrc); 290 if (!priv->can.clock.freq) { 291 dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n"); 292 goto exit_free_mscan; 293 } 294 295 SET_NETDEV_DEV(dev, &ofdev->dev); 296 297 err = register_mscandev(dev, mscan_clksrc); 298 if (err) { 299 dev_err(&ofdev->dev, "registering %s failed (err=%d)\n", 300 DRV_NAME, err); 301 goto exit_free_mscan; 302 } 303 304 dev_set_drvdata(&ofdev->dev, dev); 305 306 dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n", 307 priv->reg_base, dev->irq, priv->can.clock.freq); 308 309 return 0; 310 311exit_free_mscan: 312 free_candev(dev); 313exit_dispose_irq: 314 irq_dispose_mapping(irq); 315exit_unmap_mem: 316 iounmap(base); 317 318 return err; 319} 320 321static int __devexit mpc5xxx_can_remove(struct of_device *ofdev) 322{ 323 struct net_device *dev = dev_get_drvdata(&ofdev->dev); 324 struct mscan_priv *priv = netdev_priv(dev); 325 326 dev_set_drvdata(&ofdev->dev, NULL); 327 328 unregister_mscandev(dev); 329 iounmap(priv->reg_base); 330 irq_dispose_mapping(dev->irq); 331 free_candev(dev); 332 333 return 0; 334} 335 336#ifdef CONFIG_PM 337static struct mscan_regs saved_regs; 338static int mpc5xxx_can_suspend(struct of_device *ofdev, pm_message_t state) 339{ 340 struct net_device *dev = dev_get_drvdata(&ofdev->dev); 341 struct mscan_priv *priv = netdev_priv(dev); 342 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 343 344 _memcpy_fromio(&saved_regs, regs, sizeof(*regs)); 345 346 return 0; 347} 348 349static int mpc5xxx_can_resume(struct of_device *ofdev) 350{ 351 struct net_device *dev = dev_get_drvdata(&ofdev->dev); 352 struct mscan_priv *priv = netdev_priv(dev); 353 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 354 355 regs->canctl0 |= MSCAN_INITRQ; 356 while (!(regs->canctl1 & MSCAN_INITAK)) 357 udelay(10); 358 359 regs->canctl1 = saved_regs.canctl1; 360 regs->canbtr0 = saved_regs.canbtr0; 361 regs->canbtr1 = saved_regs.canbtr1; 362 regs->canidac = saved_regs.canidac; 363 364 /* restore masks, buffers etc. */ 365 _memcpy_toio(®s->canidar1_0, (void *)&saved_regs.canidar1_0, 366 sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0)); 367 368 regs->canctl0 &= ~MSCAN_INITRQ; 369 regs->cantbsel = saved_regs.cantbsel; 370 regs->canrier = saved_regs.canrier; 371 regs->cantier = saved_regs.cantier; 372 regs->canctl0 = saved_regs.canctl0; 373 374 return 0; 375} 376#endif 377 378static struct mpc5xxx_can_data __devinitdata mpc5200_can_data = { 379 .type = MSCAN_TYPE_MPC5200, 380 .get_clock = mpc52xx_can_get_clock, 381}; 382 383static struct mpc5xxx_can_data __devinitdata mpc5121_can_data = { 384 .type = MSCAN_TYPE_MPC5121, 385 .get_clock = mpc512x_can_get_clock, 386}; 387 388static struct of_device_id __devinitdata mpc5xxx_can_table[] = { 389 { .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, }, 390 /* Note that only MPC5121 Rev. 2 (and later) is supported */ 391 { .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, }, 392 {}, 393}; 394 395static struct of_platform_driver mpc5xxx_can_driver = { 396 .owner = THIS_MODULE, 397 .name = "mpc5xxx_can", 398 .probe = mpc5xxx_can_probe, 399 .remove = __devexit_p(mpc5xxx_can_remove), 400#ifdef CONFIG_PM 401 .suspend = mpc5xxx_can_suspend, 402 .resume = mpc5xxx_can_resume, 403#endif 404 .match_table = mpc5xxx_can_table, 405}; 406 407static int __init mpc5xxx_can_init(void) 408{ 409 return of_register_platform_driver(&mpc5xxx_can_driver); 410} 411module_init(mpc5xxx_can_init); 412 413static void __exit mpc5xxx_can_exit(void) 414{ 415 return of_unregister_platform_driver(&mpc5xxx_can_driver); 416}; 417module_exit(mpc5xxx_can_exit); 418 419MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>"); 420MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver"); 421MODULE_LICENSE("GPL v2"); 422