mscan.c revision 665d7eb8877c6bb777039efb22f894740be10bcb
1/* 2 * CAN bus driver for the alone generic (as possible as) MSCAN controller. 3 * 4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>, 5 * Varma Electronics Oy 6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com> 7 * Copyright (C) 2008-2009 Pengutronix <kernel@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23#include <linux/kernel.h> 24#include <linux/module.h> 25#include <linux/interrupt.h> 26#include <linux/delay.h> 27#include <linux/netdevice.h> 28#include <linux/if_arp.h> 29#include <linux/if_ether.h> 30#include <linux/list.h> 31#include <linux/can/dev.h> 32#include <linux/can/error.h> 33#include <linux/io.h> 34 35#include "mscan.h" 36 37static struct can_bittiming_const mscan_bittiming_const = { 38 .name = "mscan", 39 .tseg1_min = 4, 40 .tseg1_max = 16, 41 .tseg2_min = 2, 42 .tseg2_max = 8, 43 .sjw_max = 4, 44 .brp_min = 1, 45 .brp_max = 64, 46 .brp_inc = 1, 47}; 48 49struct mscan_state { 50 u8 mode; 51 u8 canrier; 52 u8 cantier; 53}; 54 55static enum can_state state_map[] = { 56 CAN_STATE_ERROR_ACTIVE, 57 CAN_STATE_ERROR_WARNING, 58 CAN_STATE_ERROR_PASSIVE, 59 CAN_STATE_BUS_OFF 60}; 61 62static int mscan_set_mode(struct net_device *dev, u8 mode) 63{ 64 struct mscan_priv *priv = netdev_priv(dev); 65 struct mscan_regs __iomem *regs = priv->reg_base; 66 int ret = 0; 67 int i; 68 u8 canctl1; 69 70 if (mode != MSCAN_NORMAL_MODE) { 71 if (priv->tx_active) { 72 /* Abort transfers before going to sleep */# 73 out_8(®s->cantarq, priv->tx_active); 74 /* Suppress TX done interrupts */ 75 out_8(®s->cantier, 0); 76 } 77 78 canctl1 = in_8(®s->canctl1); 79 if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) { 80 setbits8(®s->canctl0, MSCAN_SLPRQ); 81 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { 82 if (in_8(®s->canctl1) & MSCAN_SLPAK) 83 break; 84 udelay(100); 85 } 86 /* 87 * The mscan controller will fail to enter sleep mode, 88 * while there are irregular activities on bus, like 89 * somebody keeps retransmitting. This behavior is 90 * undocumented and seems to differ between mscan built 91 * in mpc5200b and mpc5200. We proceed in that case, 92 * since otherwise the slprq will be kept set and the 93 * controller will get stuck. NOTE: INITRQ or CSWAI 94 * will abort all active transmit actions, if still 95 * any, at once. 96 */ 97 if (i >= MSCAN_SET_MODE_RETRIES) 98 dev_dbg(dev->dev.parent, 99 "device failed to enter sleep mode. " 100 "We proceed anyhow.\n"); 101 else 102 priv->can.state = CAN_STATE_SLEEPING; 103 } 104 105 if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) { 106 setbits8(®s->canctl0, MSCAN_INITRQ); 107 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { 108 if (in_8(®s->canctl1) & MSCAN_INITAK) 109 break; 110 } 111 if (i >= MSCAN_SET_MODE_RETRIES) 112 ret = -ENODEV; 113 } 114 if (!ret) 115 priv->can.state = CAN_STATE_STOPPED; 116 117 if (mode & MSCAN_CSWAI) 118 setbits8(®s->canctl0, MSCAN_CSWAI); 119 120 } else { 121 canctl1 = in_8(®s->canctl1); 122 if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) { 123 clrbits8(®s->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ); 124 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { 125 canctl1 = in_8(®s->canctl1); 126 if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK))) 127 break; 128 } 129 if (i >= MSCAN_SET_MODE_RETRIES) 130 ret = -ENODEV; 131 else 132 priv->can.state = CAN_STATE_ERROR_ACTIVE; 133 } 134 } 135 return ret; 136} 137 138static int mscan_start(struct net_device *dev) 139{ 140 struct mscan_priv *priv = netdev_priv(dev); 141 struct mscan_regs __iomem *regs = priv->reg_base; 142 u8 canrflg; 143 int err; 144 145 out_8(®s->canrier, 0); 146 147 INIT_LIST_HEAD(&priv->tx_head); 148 priv->prev_buf_id = 0; 149 priv->cur_pri = 0; 150 priv->tx_active = 0; 151 priv->shadow_canrier = 0; 152 priv->flags = 0; 153 154 if (priv->type == MSCAN_TYPE_MPC5121) { 155 /* Clear pending bus-off condition */ 156 if (in_8(®s->canmisc) & MSCAN_BOHOLD) 157 out_8(®s->canmisc, MSCAN_BOHOLD); 158 } 159 160 err = mscan_set_mode(dev, MSCAN_NORMAL_MODE); 161 if (err) 162 return err; 163 164 canrflg = in_8(®s->canrflg); 165 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK; 166 priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg), 167 MSCAN_STATE_TX(canrflg))]; 168 out_8(®s->cantier, 0); 169 170 /* Enable receive interrupts. */ 171 out_8(®s->canrier, MSCAN_RX_INTS_ENABLE); 172 173 return 0; 174} 175 176static int mscan_restart(struct net_device *dev) 177{ 178 struct mscan_priv *priv = netdev_priv(dev); 179 180 if (priv->type == MSCAN_TYPE_MPC5121) { 181 struct mscan_regs __iomem *regs = priv->reg_base; 182 183 priv->can.state = CAN_STATE_ERROR_ACTIVE; 184 WARN(!(in_8(®s->canmisc) & MSCAN_BOHOLD), 185 "bus-off state expected\n"); 186 out_8(®s->canmisc, MSCAN_BOHOLD); 187 /* Re-enable receive interrupts. */ 188 out_8(®s->canrier, MSCAN_RX_INTS_ENABLE); 189 } else { 190 if (priv->can.state <= CAN_STATE_BUS_OFF) 191 mscan_set_mode(dev, MSCAN_INIT_MODE); 192 return mscan_start(dev); 193 } 194 195 return 0; 196} 197 198static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev) 199{ 200 struct can_frame *frame = (struct can_frame *)skb->data; 201 struct mscan_priv *priv = netdev_priv(dev); 202 struct mscan_regs __iomem *regs = priv->reg_base; 203 int i, rtr, buf_id; 204 u32 can_id; 205 206 if (can_dropped_invalid_skb(dev, skb)) 207 return NETDEV_TX_OK; 208 209 out_8(®s->cantier, 0); 210 211 i = ~priv->tx_active & MSCAN_TXE; 212 buf_id = ffs(i) - 1; 213 switch (hweight8(i)) { 214 case 0: 215 netif_stop_queue(dev); 216 dev_err(dev->dev.parent, "Tx Ring full when queue awake!\n"); 217 return NETDEV_TX_BUSY; 218 case 1: 219 /* 220 * if buf_id < 3, then current frame will be send out of order, 221 * since buffer with lower id have higher priority (hell..) 222 */ 223 netif_stop_queue(dev); 224 case 2: 225 if (buf_id < priv->prev_buf_id) { 226 priv->cur_pri++; 227 if (priv->cur_pri == 0xff) { 228 set_bit(F_TX_WAIT_ALL, &priv->flags); 229 netif_stop_queue(dev); 230 } 231 } 232 set_bit(F_TX_PROGRESS, &priv->flags); 233 break; 234 } 235 priv->prev_buf_id = buf_id; 236 out_8(®s->cantbsel, i); 237 238 rtr = frame->can_id & CAN_RTR_FLAG; 239 240 /* RTR is always the lowest bit of interest, then IDs follow */ 241 if (frame->can_id & CAN_EFF_FLAG) { 242 can_id = (frame->can_id & CAN_EFF_MASK) 243 << (MSCAN_EFF_RTR_SHIFT + 1); 244 if (rtr) 245 can_id |= 1 << MSCAN_EFF_RTR_SHIFT; 246 out_be16(®s->tx.idr3_2, can_id); 247 248 can_id >>= 16; 249 /* EFF_FLAGS are between the IDs :( */ 250 can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0) 251 | MSCAN_EFF_FLAGS; 252 } else { 253 can_id = (frame->can_id & CAN_SFF_MASK) 254 << (MSCAN_SFF_RTR_SHIFT + 1); 255 if (rtr) 256 can_id |= 1 << MSCAN_SFF_RTR_SHIFT; 257 } 258 out_be16(®s->tx.idr1_0, can_id); 259 260 if (!rtr) { 261 void __iomem *data = ®s->tx.dsr1_0; 262 u16 *payload = (u16 *)frame->data; 263 264 /* It is safe to write into dsr[dlc+1] */ 265 for (i = 0; i < (frame->can_dlc + 1) / 2; i++) { 266 out_be16(data, *payload++); 267 data += 2 + _MSCAN_RESERVED_DSR_SIZE; 268 } 269 } 270 271 out_8(®s->tx.dlr, frame->can_dlc); 272 out_8(®s->tx.tbpr, priv->cur_pri); 273 274 /* Start transmission. */ 275 out_8(®s->cantflg, 1 << buf_id); 276 277 if (!test_bit(F_TX_PROGRESS, &priv->flags)) 278 dev->trans_start = jiffies; 279 280 list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head); 281 282 can_put_echo_skb(skb, dev, buf_id); 283 284 /* Enable interrupt. */ 285 priv->tx_active |= 1 << buf_id; 286 out_8(®s->cantier, priv->tx_active); 287 288 return NETDEV_TX_OK; 289} 290 291/* This function returns the old state to see where we came from */ 292static enum can_state check_set_state(struct net_device *dev, u8 canrflg) 293{ 294 struct mscan_priv *priv = netdev_priv(dev); 295 enum can_state state, old_state = priv->can.state; 296 297 if (canrflg & MSCAN_CSCIF && old_state <= CAN_STATE_BUS_OFF) { 298 state = state_map[max(MSCAN_STATE_RX(canrflg), 299 MSCAN_STATE_TX(canrflg))]; 300 priv->can.state = state; 301 } 302 return old_state; 303} 304 305static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame) 306{ 307 struct mscan_priv *priv = netdev_priv(dev); 308 struct mscan_regs __iomem *regs = priv->reg_base; 309 u32 can_id; 310 int i; 311 312 can_id = in_be16(®s->rx.idr1_0); 313 if (can_id & (1 << 3)) { 314 frame->can_id = CAN_EFF_FLAG; 315 can_id = ((can_id << 16) | in_be16(®s->rx.idr3_2)); 316 can_id = ((can_id & 0xffe00000) | 317 ((can_id & 0x7ffff) << 2)) >> 2; 318 } else { 319 can_id >>= 4; 320 frame->can_id = 0; 321 } 322 323 frame->can_id |= can_id >> 1; 324 if (can_id & 1) 325 frame->can_id |= CAN_RTR_FLAG; 326 327 frame->can_dlc = get_can_dlc(in_8(®s->rx.dlr) & 0xf); 328 329 if (!(frame->can_id & CAN_RTR_FLAG)) { 330 void __iomem *data = ®s->rx.dsr1_0; 331 u16 *payload = (u16 *)frame->data; 332 333 for (i = 0; i < (frame->can_dlc + 1) / 2; i++) { 334 *payload++ = in_be16(data); 335 data += 2 + _MSCAN_RESERVED_DSR_SIZE; 336 } 337 } 338 339 out_8(®s->canrflg, MSCAN_RXF); 340} 341 342static void mscan_get_err_frame(struct net_device *dev, struct can_frame *frame, 343 u8 canrflg) 344{ 345 struct mscan_priv *priv = netdev_priv(dev); 346 struct mscan_regs __iomem *regs = priv->reg_base; 347 struct net_device_stats *stats = &dev->stats; 348 enum can_state old_state; 349 350 dev_dbg(dev->dev.parent, "error interrupt (canrflg=%#x)\n", canrflg); 351 frame->can_id = CAN_ERR_FLAG; 352 353 if (canrflg & MSCAN_OVRIF) { 354 frame->can_id |= CAN_ERR_CRTL; 355 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 356 stats->rx_over_errors++; 357 stats->rx_errors++; 358 } else { 359 frame->data[1] = 0; 360 } 361 362 old_state = check_set_state(dev, canrflg); 363 /* State changed */ 364 if (old_state != priv->can.state) { 365 switch (priv->can.state) { 366 case CAN_STATE_ERROR_WARNING: 367 frame->can_id |= CAN_ERR_CRTL; 368 priv->can.can_stats.error_warning++; 369 if ((priv->shadow_statflg & MSCAN_RSTAT_MSK) < 370 (canrflg & MSCAN_RSTAT_MSK)) 371 frame->data[1] |= CAN_ERR_CRTL_RX_WARNING; 372 if ((priv->shadow_statflg & MSCAN_TSTAT_MSK) < 373 (canrflg & MSCAN_TSTAT_MSK)) 374 frame->data[1] |= CAN_ERR_CRTL_TX_WARNING; 375 break; 376 case CAN_STATE_ERROR_PASSIVE: 377 frame->can_id |= CAN_ERR_CRTL; 378 priv->can.can_stats.error_passive++; 379 frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 380 break; 381 case CAN_STATE_BUS_OFF: 382 frame->can_id |= CAN_ERR_BUSOFF; 383 /* 384 * The MSCAN on the MPC5200 does recover from bus-off 385 * automatically. To avoid that we stop the chip doing 386 * a light-weight stop (we are in irq-context). 387 */ 388 if (priv->type != MSCAN_TYPE_MPC5121) { 389 out_8(®s->cantier, 0); 390 out_8(®s->canrier, 0); 391 setbits8(®s->canctl0, 392 MSCAN_SLPRQ | MSCAN_INITRQ); 393 } 394 can_bus_off(dev); 395 break; 396 default: 397 break; 398 } 399 } 400 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK; 401 frame->can_dlc = CAN_ERR_DLC; 402 out_8(®s->canrflg, MSCAN_ERR_IF); 403} 404 405static int mscan_rx_poll(struct napi_struct *napi, int quota) 406{ 407 struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi); 408 struct net_device *dev = napi->dev; 409 struct mscan_regs __iomem *regs = priv->reg_base; 410 struct net_device_stats *stats = &dev->stats; 411 int npackets = 0; 412 int ret = 1; 413 struct sk_buff *skb; 414 struct can_frame *frame; 415 u8 canrflg; 416 417 while (npackets < quota) { 418 canrflg = in_8(®s->canrflg); 419 if (!(canrflg & (MSCAN_RXF | MSCAN_ERR_IF))) 420 break; 421 422 skb = alloc_can_skb(dev, &frame); 423 if (!skb) { 424 if (printk_ratelimit()) 425 dev_notice(dev->dev.parent, "packet dropped\n"); 426 stats->rx_dropped++; 427 out_8(®s->canrflg, canrflg); 428 continue; 429 } 430 431 if (canrflg & MSCAN_RXF) 432 mscan_get_rx_frame(dev, frame); 433 else if (canrflg & MSCAN_ERR_IF) 434 mscan_get_err_frame(dev, frame, canrflg); 435 436 stats->rx_packets++; 437 stats->rx_bytes += frame->can_dlc; 438 npackets++; 439 netif_receive_skb(skb); 440 } 441 442 if (!(in_8(®s->canrflg) & (MSCAN_RXF | MSCAN_ERR_IF))) { 443 napi_complete(&priv->napi); 444 clear_bit(F_RX_PROGRESS, &priv->flags); 445 if (priv->can.state < CAN_STATE_BUS_OFF) 446 out_8(®s->canrier, priv->shadow_canrier); 447 ret = 0; 448 } 449 return ret; 450} 451 452static irqreturn_t mscan_isr(int irq, void *dev_id) 453{ 454 struct net_device *dev = (struct net_device *)dev_id; 455 struct mscan_priv *priv = netdev_priv(dev); 456 struct mscan_regs __iomem *regs = priv->reg_base; 457 struct net_device_stats *stats = &dev->stats; 458 u8 cantier, cantflg, canrflg; 459 irqreturn_t ret = IRQ_NONE; 460 461 cantier = in_8(®s->cantier) & MSCAN_TXE; 462 cantflg = in_8(®s->cantflg) & cantier; 463 464 if (cantier && cantflg) { 465 struct list_head *tmp, *pos; 466 467 list_for_each_safe(pos, tmp, &priv->tx_head) { 468 struct tx_queue_entry *entry = 469 list_entry(pos, struct tx_queue_entry, list); 470 u8 mask = entry->mask; 471 472 if (!(cantflg & mask)) 473 continue; 474 475 out_8(®s->cantbsel, mask); 476 stats->tx_bytes += in_8(®s->tx.dlr); 477 stats->tx_packets++; 478 can_get_echo_skb(dev, entry->id); 479 priv->tx_active &= ~mask; 480 list_del(pos); 481 } 482 483 if (list_empty(&priv->tx_head)) { 484 clear_bit(F_TX_WAIT_ALL, &priv->flags); 485 clear_bit(F_TX_PROGRESS, &priv->flags); 486 priv->cur_pri = 0; 487 } else { 488 dev->trans_start = jiffies; 489 } 490 491 if (!test_bit(F_TX_WAIT_ALL, &priv->flags)) 492 netif_wake_queue(dev); 493 494 out_8(®s->cantier, priv->tx_active); 495 ret = IRQ_HANDLED; 496 } 497 498 canrflg = in_8(®s->canrflg); 499 if ((canrflg & ~MSCAN_STAT_MSK) && 500 !test_and_set_bit(F_RX_PROGRESS, &priv->flags)) { 501 if (canrflg & ~MSCAN_STAT_MSK) { 502 priv->shadow_canrier = in_8(®s->canrier); 503 out_8(®s->canrier, 0); 504 napi_schedule(&priv->napi); 505 ret = IRQ_HANDLED; 506 } else { 507 clear_bit(F_RX_PROGRESS, &priv->flags); 508 } 509 } 510 return ret; 511} 512 513static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode) 514{ 515 struct mscan_priv *priv = netdev_priv(dev); 516 int ret = 0; 517 518 if (!priv->open_time) 519 return -EINVAL; 520 521 switch (mode) { 522 case CAN_MODE_START: 523 ret = mscan_restart(dev); 524 if (ret) 525 break; 526 if (netif_queue_stopped(dev)) 527 netif_wake_queue(dev); 528 break; 529 530 default: 531 ret = -EOPNOTSUPP; 532 break; 533 } 534 return ret; 535} 536 537static int mscan_do_set_bittiming(struct net_device *dev) 538{ 539 struct mscan_priv *priv = netdev_priv(dev); 540 struct mscan_regs __iomem *regs = priv->reg_base; 541 struct can_bittiming *bt = &priv->can.bittiming; 542 u8 btr0, btr1; 543 544 btr0 = BTR0_SET_BRP(bt->brp) | BTR0_SET_SJW(bt->sjw); 545 btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) | 546 BTR1_SET_TSEG2(bt->phase_seg2) | 547 BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)); 548 549 dev_info(dev->dev.parent, "setting BTR0=0x%02x BTR1=0x%02x\n", 550 btr0, btr1); 551 552 out_8(®s->canbtr0, btr0); 553 out_8(®s->canbtr1, btr1); 554 555 return 0; 556} 557 558static int mscan_open(struct net_device *dev) 559{ 560 int ret; 561 struct mscan_priv *priv = netdev_priv(dev); 562 struct mscan_regs __iomem *regs = priv->reg_base; 563 564 /* common open */ 565 ret = open_candev(dev); 566 if (ret) 567 return ret; 568 569 napi_enable(&priv->napi); 570 571 ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev); 572 if (ret < 0) { 573 dev_err(dev->dev.parent, "failed to attach interrupt\n"); 574 goto exit_napi_disable; 575 } 576 577 priv->open_time = jiffies; 578 579 clrbits8(®s->canctl1, MSCAN_LISTEN); 580 581 ret = mscan_start(dev); 582 if (ret) 583 goto exit_free_irq; 584 585 netif_start_queue(dev); 586 587 return 0; 588 589exit_free_irq: 590 priv->open_time = 0; 591 free_irq(dev->irq, dev); 592exit_napi_disable: 593 napi_disable(&priv->napi); 594 close_candev(dev); 595 return ret; 596} 597 598static int mscan_close(struct net_device *dev) 599{ 600 struct mscan_priv *priv = netdev_priv(dev); 601 struct mscan_regs __iomem *regs = priv->reg_base; 602 603 netif_stop_queue(dev); 604 napi_disable(&priv->napi); 605 606 out_8(®s->cantier, 0); 607 out_8(®s->canrier, 0); 608 mscan_set_mode(dev, MSCAN_INIT_MODE); 609 close_candev(dev); 610 free_irq(dev->irq, dev); 611 priv->open_time = 0; 612 613 return 0; 614} 615 616static const struct net_device_ops mscan_netdev_ops = { 617 .ndo_open = mscan_open, 618 .ndo_stop = mscan_close, 619 .ndo_start_xmit = mscan_start_xmit, 620}; 621 622int register_mscandev(struct net_device *dev, int mscan_clksrc) 623{ 624 struct mscan_priv *priv = netdev_priv(dev); 625 struct mscan_regs __iomem *regs = priv->reg_base; 626 u8 ctl1; 627 628 ctl1 = in_8(®s->canctl1); 629 if (mscan_clksrc) 630 ctl1 |= MSCAN_CLKSRC; 631 else 632 ctl1 &= ~MSCAN_CLKSRC; 633 634 if (priv->type == MSCAN_TYPE_MPC5121) 635 ctl1 |= MSCAN_BORM; /* bus-off recovery upon request */ 636 637 ctl1 |= MSCAN_CANE; 638 out_8(®s->canctl1, ctl1); 639 udelay(100); 640 641 /* acceptance mask/acceptance code (accept everything) */ 642 out_be16(®s->canidar1_0, 0); 643 out_be16(®s->canidar3_2, 0); 644 out_be16(®s->canidar5_4, 0); 645 out_be16(®s->canidar7_6, 0); 646 647 out_be16(®s->canidmr1_0, 0xffff); 648 out_be16(®s->canidmr3_2, 0xffff); 649 out_be16(®s->canidmr5_4, 0xffff); 650 out_be16(®s->canidmr7_6, 0xffff); 651 /* Two 32 bit Acceptance Filters */ 652 out_8(®s->canidac, MSCAN_AF_32BIT); 653 654 mscan_set_mode(dev, MSCAN_INIT_MODE); 655 656 return register_candev(dev); 657} 658 659void unregister_mscandev(struct net_device *dev) 660{ 661 struct mscan_priv *priv = netdev_priv(dev); 662 struct mscan_regs __iomem *regs = priv->reg_base; 663 mscan_set_mode(dev, MSCAN_INIT_MODE); 664 clrbits8(®s->canctl1, MSCAN_CANE); 665 unregister_candev(dev); 666} 667 668struct net_device *alloc_mscandev(void) 669{ 670 struct net_device *dev; 671 struct mscan_priv *priv; 672 int i; 673 674 dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX); 675 if (!dev) 676 return NULL; 677 priv = netdev_priv(dev); 678 679 dev->netdev_ops = &mscan_netdev_ops; 680 681 dev->flags |= IFF_ECHO; /* we support local echo */ 682 683 netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8); 684 685 priv->can.bittiming_const = &mscan_bittiming_const; 686 priv->can.do_set_bittiming = mscan_do_set_bittiming; 687 priv->can.do_set_mode = mscan_do_set_mode; 688 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 689 690 for (i = 0; i < TX_QUEUE_SIZE; i++) { 691 priv->tx_queue[i].id = i; 692 priv->tx_queue[i].mask = 1 << i; 693 } 694 695 return dev; 696} 697 698MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>"); 699MODULE_LICENSE("GPL v2"); 700MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips"); 701