mscan.c revision 68bd7422a2e07a4e5502137cd4bddb8c2774a912
1/* 2 * CAN bus driver for the alone generic (as possible as) MSCAN controller. 3 * 4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>, 5 * Varma Electronics Oy 6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com> 7 * Copytight (C) 2008-2009 Pengutronix <kernel@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23#include <linux/kernel.h> 24#include <linux/module.h> 25#include <linux/interrupt.h> 26#include <linux/delay.h> 27#include <linux/netdevice.h> 28#include <linux/if_arp.h> 29#include <linux/if_ether.h> 30#include <linux/list.h> 31#include <linux/can.h> 32#include <linux/can/dev.h> 33#include <linux/can/error.h> 34#include <linux/io.h> 35 36#include "mscan.h" 37 38static struct can_bittiming_const mscan_bittiming_const = { 39 .name = "mscan", 40 .tseg1_min = 4, 41 .tseg1_max = 16, 42 .tseg2_min = 2, 43 .tseg2_max = 8, 44 .sjw_max = 4, 45 .brp_min = 1, 46 .brp_max = 64, 47 .brp_inc = 1, 48}; 49 50struct mscan_state { 51 u8 mode; 52 u8 canrier; 53 u8 cantier; 54}; 55 56static enum can_state state_map[] = { 57 CAN_STATE_ERROR_ACTIVE, 58 CAN_STATE_ERROR_WARNING, 59 CAN_STATE_ERROR_PASSIVE, 60 CAN_STATE_BUS_OFF 61}; 62 63static int mscan_set_mode(struct net_device *dev, u8 mode) 64{ 65 struct mscan_priv *priv = netdev_priv(dev); 66 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 67 int ret = 0; 68 int i; 69 u8 canctl1; 70 71 if (mode != MSCAN_NORMAL_MODE) { 72 if (priv->tx_active) { 73 /* Abort transfers before going to sleep */# 74 out_8(®s->cantarq, priv->tx_active); 75 /* Suppress TX done interrupts */ 76 out_8(®s->cantier, 0); 77 } 78 79 canctl1 = in_8(®s->canctl1); 80 if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) { 81 setbits8(®s->canctl0, MSCAN_SLPRQ); 82 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { 83 if (in_8(®s->canctl1) & MSCAN_SLPAK) 84 break; 85 udelay(100); 86 } 87 /* 88 * The mscan controller will fail to enter sleep mode, 89 * while there are irregular activities on bus, like 90 * somebody keeps retransmitting. This behavior is 91 * undocumented and seems to differ between mscan built 92 * in mpc5200b and mpc5200. We proceed in that case, 93 * since otherwise the slprq will be kept set and the 94 * controller will get stuck. NOTE: INITRQ or CSWAI 95 * will abort all active transmit actions, if still 96 * any, at once. 97 */ 98 if (i >= MSCAN_SET_MODE_RETRIES) 99 dev_dbg(dev->dev.parent, 100 "device failed to enter sleep mode. " 101 "We proceed anyhow.\n"); 102 else 103 priv->can.state = CAN_STATE_SLEEPING; 104 } 105 106 if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) { 107 setbits8(®s->canctl0, MSCAN_INITRQ); 108 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { 109 if (in_8(®s->canctl1) & MSCAN_INITAK) 110 break; 111 } 112 if (i >= MSCAN_SET_MODE_RETRIES) 113 ret = -ENODEV; 114 } 115 if (!ret) 116 priv->can.state = CAN_STATE_STOPPED; 117 118 if (mode & MSCAN_CSWAI) 119 setbits8(®s->canctl0, MSCAN_CSWAI); 120 121 } else { 122 canctl1 = in_8(®s->canctl1); 123 if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) { 124 clrbits8(®s->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ); 125 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { 126 canctl1 = in_8(®s->canctl1); 127 if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK))) 128 break; 129 } 130 if (i >= MSCAN_SET_MODE_RETRIES) 131 ret = -ENODEV; 132 else 133 priv->can.state = CAN_STATE_ERROR_ACTIVE; 134 } 135 } 136 return ret; 137} 138 139static int mscan_start(struct net_device *dev) 140{ 141 struct mscan_priv *priv = netdev_priv(dev); 142 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 143 u8 canrflg; 144 int err; 145 146 out_8(®s->canrier, 0); 147 148 INIT_LIST_HEAD(&priv->tx_head); 149 priv->prev_buf_id = 0; 150 priv->cur_pri = 0; 151 priv->tx_active = 0; 152 priv->shadow_canrier = 0; 153 priv->flags = 0; 154 155 err = mscan_set_mode(dev, MSCAN_NORMAL_MODE); 156 if (err) 157 return err; 158 159 canrflg = in_8(®s->canrflg); 160 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK; 161 priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg), 162 MSCAN_STATE_TX(canrflg))]; 163 out_8(®s->cantier, 0); 164 165 /* Enable receive interrupts. */ 166 out_8(®s->canrier, MSCAN_OVRIE | MSCAN_RXFIE | MSCAN_CSCIE | 167 MSCAN_RSTATE1 | MSCAN_RSTATE0 | MSCAN_TSTATE1 | MSCAN_TSTATE0); 168 169 return 0; 170} 171 172static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev) 173{ 174 struct can_frame *frame = (struct can_frame *)skb->data; 175 struct mscan_priv *priv = netdev_priv(dev); 176 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 177 int i, rtr, buf_id; 178 u32 can_id; 179 180 if (frame->can_dlc > 8) 181 return -EINVAL; 182 183 out_8(®s->cantier, 0); 184 185 i = ~priv->tx_active & MSCAN_TXE; 186 buf_id = ffs(i) - 1; 187 switch (hweight8(i)) { 188 case 0: 189 netif_stop_queue(dev); 190 dev_err(dev->dev.parent, "Tx Ring full when queue awake!\n"); 191 return NETDEV_TX_BUSY; 192 case 1: 193 /* 194 * if buf_id < 3, then current frame will be send out of order, 195 * since buffer with lower id have higher priority (hell..) 196 */ 197 netif_stop_queue(dev); 198 case 2: 199 if (buf_id < priv->prev_buf_id) { 200 priv->cur_pri++; 201 if (priv->cur_pri == 0xff) { 202 set_bit(F_TX_WAIT_ALL, &priv->flags); 203 netif_stop_queue(dev); 204 } 205 } 206 set_bit(F_TX_PROGRESS, &priv->flags); 207 break; 208 } 209 priv->prev_buf_id = buf_id; 210 out_8(®s->cantbsel, i); 211 212 rtr = frame->can_id & CAN_RTR_FLAG; 213 214 if (frame->can_id & CAN_EFF_FLAG) { 215 can_id = (frame->can_id & CAN_EFF_MASK) << 1; 216 if (rtr) 217 can_id |= 1; 218 out_be16(®s->tx.idr3_2, can_id); 219 220 can_id >>= 16; 221 can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0) | (3 << 3); 222 } else { 223 can_id = (frame->can_id & CAN_SFF_MASK) << 5; 224 if (rtr) 225 can_id |= 1 << 4; 226 } 227 out_be16(®s->tx.idr1_0, can_id); 228 229 if (!rtr) { 230 void __iomem *data = ®s->tx.dsr1_0; 231 u16 *payload = (u16 *)frame->data; 232 233 /* It is safe to write into dsr[dlc+1] */ 234 for (i = 0; i < (frame->can_dlc + 1) / 2; i++) { 235 out_be16(data, *payload++); 236 data += 2 + _MSCAN_RESERVED_DSR_SIZE; 237 } 238 } 239 240 out_8(®s->tx.dlr, frame->can_dlc); 241 out_8(®s->tx.tbpr, priv->cur_pri); 242 243 /* Start transmission. */ 244 out_8(®s->cantflg, 1 << buf_id); 245 246 if (!test_bit(F_TX_PROGRESS, &priv->flags)) 247 dev->trans_start = jiffies; 248 249 list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head); 250 251 can_put_echo_skb(skb, dev, buf_id); 252 253 /* Enable interrupt. */ 254 priv->tx_active |= 1 << buf_id; 255 out_8(®s->cantier, priv->tx_active); 256 257 return NETDEV_TX_OK; 258} 259 260/* This function returns the old state to see where we came from */ 261static enum can_state check_set_state(struct net_device *dev, u8 canrflg) 262{ 263 struct mscan_priv *priv = netdev_priv(dev); 264 enum can_state state, old_state = priv->can.state; 265 266 if (canrflg & MSCAN_CSCIF && old_state <= CAN_STATE_BUS_OFF) { 267 state = state_map[max(MSCAN_STATE_RX(canrflg), 268 MSCAN_STATE_TX(canrflg))]; 269 priv->can.state = state; 270 } 271 return old_state; 272} 273 274static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame) 275{ 276 struct mscan_priv *priv = netdev_priv(dev); 277 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 278 u32 can_id; 279 int i; 280 281 can_id = in_be16(®s->rx.idr1_0); 282 if (can_id & (1 << 3)) { 283 frame->can_id = CAN_EFF_FLAG; 284 can_id = ((can_id << 16) | in_be16(®s->rx.idr3_2)); 285 can_id = ((can_id & 0xffe00000) | 286 ((can_id & 0x7ffff) << 2)) >> 2; 287 } else { 288 can_id >>= 4; 289 frame->can_id = 0; 290 } 291 292 frame->can_id |= can_id >> 1; 293 if (can_id & 1) 294 frame->can_id |= CAN_RTR_FLAG; 295 frame->can_dlc = in_8(®s->rx.dlr) & 0xf; 296 297 if (!(frame->can_id & CAN_RTR_FLAG)) { 298 void __iomem *data = ®s->rx.dsr1_0; 299 u16 *payload = (u16 *)frame->data; 300 301 for (i = 0; i < (frame->can_dlc + 1) / 2; i++) { 302 *payload++ = in_be16(data); 303 data += 2 + _MSCAN_RESERVED_DSR_SIZE; 304 } 305 } 306 307 out_8(®s->canrflg, MSCAN_RXF); 308} 309 310static void mscan_get_err_frame(struct net_device *dev, struct can_frame *frame, 311 u8 canrflg) 312{ 313 struct mscan_priv *priv = netdev_priv(dev); 314 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 315 struct net_device_stats *stats = &dev->stats; 316 enum can_state old_state; 317 318 dev_dbg(dev->dev.parent, "error interrupt (canrflg=%#x)\n", canrflg); 319 frame->can_id = CAN_ERR_FLAG; 320 321 if (canrflg & MSCAN_OVRIF) { 322 frame->can_id |= CAN_ERR_CRTL; 323 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 324 stats->rx_over_errors++; 325 stats->rx_errors++; 326 } else { 327 frame->data[1] = 0; 328 } 329 330 old_state = check_set_state(dev, canrflg); 331 /* State changed */ 332 if (old_state != priv->can.state) { 333 switch (priv->can.state) { 334 case CAN_STATE_ERROR_WARNING: 335 frame->can_id |= CAN_ERR_CRTL; 336 priv->can.can_stats.error_warning++; 337 if ((priv->shadow_statflg & MSCAN_RSTAT_MSK) < 338 (canrflg & MSCAN_RSTAT_MSK)) 339 frame->data[1] |= CAN_ERR_CRTL_RX_WARNING; 340 if ((priv->shadow_statflg & MSCAN_TSTAT_MSK) < 341 (canrflg & MSCAN_TSTAT_MSK)) 342 frame->data[1] |= CAN_ERR_CRTL_TX_WARNING; 343 break; 344 case CAN_STATE_ERROR_PASSIVE: 345 frame->can_id |= CAN_ERR_CRTL; 346 priv->can.can_stats.error_passive++; 347 frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 348 break; 349 case CAN_STATE_BUS_OFF: 350 frame->can_id |= CAN_ERR_BUSOFF; 351 /* 352 * The MSCAN on the MPC5200 does recover from bus-off 353 * automatically. To avoid that we stop the chip doing 354 * a light-weight stop (we are in irq-context). 355 */ 356 out_8(®s->cantier, 0); 357 out_8(®s->canrier, 0); 358 setbits8(®s->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ); 359 can_bus_off(dev); 360 break; 361 default: 362 break; 363 } 364 } 365 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK; 366 frame->can_dlc = CAN_ERR_DLC; 367 out_8(®s->canrflg, MSCAN_ERR_IF); 368} 369 370static int mscan_rx_poll(struct napi_struct *napi, int quota) 371{ 372 struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi); 373 struct net_device *dev = napi->dev; 374 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 375 struct net_device_stats *stats = &dev->stats; 376 int npackets = 0; 377 int ret = 1; 378 struct sk_buff *skb; 379 struct can_frame *frame; 380 u8 canrflg; 381 382 while (npackets < quota) { 383 canrflg = in_8(®s->canrflg); 384 if (!(canrflg & (MSCAN_RXF | MSCAN_ERR_IF))) 385 break; 386 387 skb = alloc_can_skb(dev, &frame); 388 if (!skb) { 389 if (printk_ratelimit()) 390 dev_notice(dev->dev.parent, "packet dropped\n"); 391 stats->rx_dropped++; 392 out_8(®s->canrflg, canrflg); 393 continue; 394 } 395 396 if (canrflg & MSCAN_RXF) 397 mscan_get_rx_frame(dev, frame); 398 else if (canrflg & MSCAN_ERR_IF) 399 mscan_get_err_frame(dev, frame, canrflg); 400 401 stats->rx_packets++; 402 stats->rx_bytes += frame->can_dlc; 403 npackets++; 404 netif_receive_skb(skb); 405 } 406 407 if (!(in_8(®s->canrflg) & (MSCAN_RXF | MSCAN_ERR_IF))) { 408 napi_complete(&priv->napi); 409 clear_bit(F_RX_PROGRESS, &priv->flags); 410 if (priv->can.state < CAN_STATE_BUS_OFF) 411 out_8(®s->canrier, priv->shadow_canrier); 412 ret = 0; 413 } 414 return ret; 415} 416 417static irqreturn_t mscan_isr(int irq, void *dev_id) 418{ 419 struct net_device *dev = (struct net_device *)dev_id; 420 struct mscan_priv *priv = netdev_priv(dev); 421 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 422 struct net_device_stats *stats = &dev->stats; 423 u8 cantier, cantflg, canrflg; 424 irqreturn_t ret = IRQ_NONE; 425 426 cantier = in_8(®s->cantier) & MSCAN_TXE; 427 cantflg = in_8(®s->cantflg) & cantier; 428 429 if (cantier && cantflg) { 430 struct list_head *tmp, *pos; 431 432 list_for_each_safe(pos, tmp, &priv->tx_head) { 433 struct tx_queue_entry *entry = 434 list_entry(pos, struct tx_queue_entry, list); 435 u8 mask = entry->mask; 436 437 if (!(cantflg & mask)) 438 continue; 439 440 out_8(®s->cantbsel, mask); 441 stats->tx_bytes += in_8(®s->tx.dlr); 442 stats->tx_packets++; 443 can_get_echo_skb(dev, entry->id); 444 priv->tx_active &= ~mask; 445 list_del(pos); 446 } 447 448 if (list_empty(&priv->tx_head)) { 449 clear_bit(F_TX_WAIT_ALL, &priv->flags); 450 clear_bit(F_TX_PROGRESS, &priv->flags); 451 priv->cur_pri = 0; 452 } else { 453 dev->trans_start = jiffies; 454 } 455 456 if (!test_bit(F_TX_WAIT_ALL, &priv->flags)) 457 netif_wake_queue(dev); 458 459 out_8(®s->cantier, priv->tx_active); 460 ret = IRQ_HANDLED; 461 } 462 463 canrflg = in_8(®s->canrflg); 464 if ((canrflg & ~MSCAN_STAT_MSK) && 465 !test_and_set_bit(F_RX_PROGRESS, &priv->flags)) { 466 if (canrflg & ~MSCAN_STAT_MSK) { 467 priv->shadow_canrier = in_8(®s->canrier); 468 out_8(®s->canrier, 0); 469 napi_schedule(&priv->napi); 470 ret = IRQ_HANDLED; 471 } else { 472 clear_bit(F_RX_PROGRESS, &priv->flags); 473 } 474 } 475 return ret; 476} 477 478static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode) 479{ 480 struct mscan_priv *priv = netdev_priv(dev); 481 int ret = 0; 482 483 if (!priv->open_time) 484 return -EINVAL; 485 486 switch (mode) { 487 case CAN_MODE_START: 488 if (priv->can.state <= CAN_STATE_BUS_OFF) 489 mscan_set_mode(dev, MSCAN_INIT_MODE); 490 ret = mscan_start(dev); 491 if (ret) 492 break; 493 if (netif_queue_stopped(dev)) 494 netif_wake_queue(dev); 495 break; 496 497 default: 498 ret = -EOPNOTSUPP; 499 break; 500 } 501 return ret; 502} 503 504static int mscan_do_set_bittiming(struct net_device *dev) 505{ 506 struct mscan_priv *priv = netdev_priv(dev); 507 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 508 struct can_bittiming *bt = &priv->can.bittiming; 509 u8 btr0, btr1; 510 511 btr0 = BTR0_SET_BRP(bt->brp) | BTR0_SET_SJW(bt->sjw); 512 btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) | 513 BTR1_SET_TSEG2(bt->phase_seg2) | 514 BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)); 515 516 dev_info(dev->dev.parent, "setting BTR0=0x%02x BTR1=0x%02x\n", 517 btr0, btr1); 518 519 out_8(®s->canbtr0, btr0); 520 out_8(®s->canbtr1, btr1); 521 522 return 0; 523} 524 525static int mscan_open(struct net_device *dev) 526{ 527 int ret; 528 struct mscan_priv *priv = netdev_priv(dev); 529 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 530 531 /* common open */ 532 ret = open_candev(dev); 533 if (ret) 534 return ret; 535 536 napi_enable(&priv->napi); 537 538 ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev); 539 if (ret < 0) { 540 napi_disable(&priv->napi); 541 printk(KERN_ERR "%s - failed to attach interrupt\n", 542 dev->name); 543 return ret; 544 } 545 546 priv->open_time = jiffies; 547 548 clrbits8(®s->canctl1, MSCAN_LISTEN); 549 550 ret = mscan_start(dev); 551 if (ret) 552 return ret; 553 554 netif_start_queue(dev); 555 556 return 0; 557} 558 559static int mscan_close(struct net_device *dev) 560{ 561 struct mscan_priv *priv = netdev_priv(dev); 562 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 563 564 netif_stop_queue(dev); 565 napi_disable(&priv->napi); 566 567 out_8(®s->cantier, 0); 568 out_8(®s->canrier, 0); 569 mscan_set_mode(dev, MSCAN_INIT_MODE); 570 close_candev(dev); 571 free_irq(dev->irq, dev); 572 priv->open_time = 0; 573 574 return 0; 575} 576 577static const struct net_device_ops mscan_netdev_ops = { 578 .ndo_open = mscan_open, 579 .ndo_stop = mscan_close, 580 .ndo_start_xmit = mscan_start_xmit, 581}; 582 583int register_mscandev(struct net_device *dev, int clock_src) 584{ 585 struct mscan_priv *priv = netdev_priv(dev); 586 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 587 u8 ctl1; 588 589 ctl1 = in_8(®s->canctl1); 590 if (clock_src) 591 ctl1 |= MSCAN_CLKSRC; 592 else 593 ctl1 &= ~MSCAN_CLKSRC; 594 595 ctl1 |= MSCAN_CANE; 596 out_8(®s->canctl1, ctl1); 597 udelay(100); 598 599 /* acceptance mask/acceptance code (accept everything) */ 600 out_be16(®s->canidar1_0, 0); 601 out_be16(®s->canidar3_2, 0); 602 out_be16(®s->canidar5_4, 0); 603 out_be16(®s->canidar7_6, 0); 604 605 out_be16(®s->canidmr1_0, 0xffff); 606 out_be16(®s->canidmr3_2, 0xffff); 607 out_be16(®s->canidmr5_4, 0xffff); 608 out_be16(®s->canidmr7_6, 0xffff); 609 /* Two 32 bit Acceptance Filters */ 610 out_8(®s->canidac, MSCAN_AF_32BIT); 611 612 mscan_set_mode(dev, MSCAN_INIT_MODE); 613 614 return register_candev(dev); 615} 616 617void unregister_mscandev(struct net_device *dev) 618{ 619 struct mscan_priv *priv = netdev_priv(dev); 620 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 621 mscan_set_mode(dev, MSCAN_INIT_MODE); 622 clrbits8(®s->canctl1, MSCAN_CANE); 623 unregister_candev(dev); 624} 625 626struct net_device *alloc_mscandev(void) 627{ 628 struct net_device *dev; 629 struct mscan_priv *priv; 630 int i; 631 632 dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX); 633 if (!dev) 634 return NULL; 635 priv = netdev_priv(dev); 636 637 dev->netdev_ops = &mscan_netdev_ops; 638 639 dev->flags |= IFF_ECHO; /* we support local echo */ 640 641 netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8); 642 643 priv->can.bittiming_const = &mscan_bittiming_const; 644 priv->can.do_set_bittiming = mscan_do_set_bittiming; 645 priv->can.do_set_mode = mscan_do_set_mode; 646 647 for (i = 0; i < TX_QUEUE_SIZE; i++) { 648 priv->tx_queue[i].id = i; 649 priv->tx_queue[i].mask = 1 << i; 650 } 651 652 return dev; 653} 654 655MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>"); 656MODULE_LICENSE("GPL v2"); 657MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips"); 658