mscan.c revision 74ff60b29ec602322178d32cb2a82b24ddb884fc
1/* 2 * CAN bus driver for the alone generic (as possible as) MSCAN controller. 3 * 4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>, 5 * Varma Electronics Oy 6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com> 7 * Copytight (C) 2008-2009 Pengutronix <kernel@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23#include <linux/kernel.h> 24#include <linux/module.h> 25#include <linux/interrupt.h> 26#include <linux/delay.h> 27#include <linux/netdevice.h> 28#include <linux/if_arp.h> 29#include <linux/if_ether.h> 30#include <linux/list.h> 31#include <linux/can.h> 32#include <linux/can/dev.h> 33#include <linux/can/error.h> 34#include <linux/io.h> 35 36#include "mscan.h" 37 38static struct can_bittiming_const mscan_bittiming_const = { 39 .name = "mscan", 40 .tseg1_min = 4, 41 .tseg1_max = 16, 42 .tseg2_min = 2, 43 .tseg2_max = 8, 44 .sjw_max = 4, 45 .brp_min = 1, 46 .brp_max = 64, 47 .brp_inc = 1, 48}; 49 50struct mscan_state { 51 u8 mode; 52 u8 canrier; 53 u8 cantier; 54}; 55 56static enum can_state state_map[] = { 57 CAN_STATE_ERROR_ACTIVE, 58 CAN_STATE_ERROR_WARNING, 59 CAN_STATE_ERROR_PASSIVE, 60 CAN_STATE_BUS_OFF 61}; 62 63static int mscan_set_mode(struct net_device *dev, u8 mode) 64{ 65 struct mscan_priv *priv = netdev_priv(dev); 66 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 67 int ret = 0; 68 int i; 69 u8 canctl1; 70 71 if (mode != MSCAN_NORMAL_MODE) { 72 if (priv->tx_active) { 73 /* Abort transfers before going to sleep */# 74 out_8(®s->cantarq, priv->tx_active); 75 /* Suppress TX done interrupts */ 76 out_8(®s->cantier, 0); 77 } 78 79 canctl1 = in_8(®s->canctl1); 80 if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) { 81 setbits8(®s->canctl0, MSCAN_SLPRQ); 82 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { 83 if (in_8(®s->canctl1) & MSCAN_SLPAK) 84 break; 85 udelay(100); 86 } 87 /* 88 * The mscan controller will fail to enter sleep mode, 89 * while there are irregular activities on bus, like 90 * somebody keeps retransmitting. This behavior is 91 * undocumented and seems to differ between mscan built 92 * in mpc5200b and mpc5200. We proceed in that case, 93 * since otherwise the slprq will be kept set and the 94 * controller will get stuck. NOTE: INITRQ or CSWAI 95 * will abort all active transmit actions, if still 96 * any, at once. 97 */ 98 if (i >= MSCAN_SET_MODE_RETRIES) 99 dev_dbg(dev->dev.parent, 100 "device failed to enter sleep mode. " 101 "We proceed anyhow.\n"); 102 else 103 priv->can.state = CAN_STATE_SLEEPING; 104 } 105 106 if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) { 107 setbits8(®s->canctl0, MSCAN_INITRQ); 108 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { 109 if (in_8(®s->canctl1) & MSCAN_INITAK) 110 break; 111 } 112 if (i >= MSCAN_SET_MODE_RETRIES) 113 ret = -ENODEV; 114 } 115 if (!ret) 116 priv->can.state = CAN_STATE_STOPPED; 117 118 if (mode & MSCAN_CSWAI) 119 setbits8(®s->canctl0, MSCAN_CSWAI); 120 121 } else { 122 canctl1 = in_8(®s->canctl1); 123 if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) { 124 clrbits8(®s->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ); 125 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { 126 canctl1 = in_8(®s->canctl1); 127 if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK))) 128 break; 129 } 130 if (i >= MSCAN_SET_MODE_RETRIES) 131 ret = -ENODEV; 132 else 133 priv->can.state = CAN_STATE_ERROR_ACTIVE; 134 } 135 } 136 return ret; 137} 138 139static int mscan_start(struct net_device *dev) 140{ 141 struct mscan_priv *priv = netdev_priv(dev); 142 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 143 u8 canrflg; 144 int err; 145 146 out_8(®s->canrier, 0); 147 148 INIT_LIST_HEAD(&priv->tx_head); 149 priv->prev_buf_id = 0; 150 priv->cur_pri = 0; 151 priv->tx_active = 0; 152 priv->shadow_canrier = 0; 153 priv->flags = 0; 154 155 err = mscan_set_mode(dev, MSCAN_NORMAL_MODE); 156 if (err) 157 return err; 158 159 canrflg = in_8(®s->canrflg); 160 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK; 161 priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg), 162 MSCAN_STATE_TX(canrflg))]; 163 out_8(®s->cantier, 0); 164 165 /* Enable receive interrupts. */ 166 out_8(®s->canrier, MSCAN_OVRIE | MSCAN_RXFIE | MSCAN_CSCIE | 167 MSCAN_RSTATE1 | MSCAN_RSTATE0 | MSCAN_TSTATE1 | MSCAN_TSTATE0); 168 169 return 0; 170} 171 172static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev) 173{ 174 struct can_frame *frame = (struct can_frame *)skb->data; 175 struct mscan_priv *priv = netdev_priv(dev); 176 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 177 int i, rtr, buf_id; 178 u32 can_id; 179 180 if (frame->can_dlc > 8) 181 return -EINVAL; 182 183 out_8(®s->cantier, 0); 184 185 i = ~priv->tx_active & MSCAN_TXE; 186 buf_id = ffs(i) - 1; 187 switch (hweight8(i)) { 188 case 0: 189 netif_stop_queue(dev); 190 dev_err(dev->dev.parent, "Tx Ring full when queue awake!\n"); 191 return NETDEV_TX_BUSY; 192 case 1: 193 /* 194 * if buf_id < 3, then current frame will be send out of order, 195 * since buffer with lower id have higher priority (hell..) 196 */ 197 netif_stop_queue(dev); 198 case 2: 199 if (buf_id < priv->prev_buf_id) { 200 priv->cur_pri++; 201 if (priv->cur_pri == 0xff) { 202 set_bit(F_TX_WAIT_ALL, &priv->flags); 203 netif_stop_queue(dev); 204 } 205 } 206 set_bit(F_TX_PROGRESS, &priv->flags); 207 break; 208 } 209 priv->prev_buf_id = buf_id; 210 out_8(®s->cantbsel, i); 211 212 rtr = frame->can_id & CAN_RTR_FLAG; 213 214 /* RTR is always the lowest bit of interest, then IDs follow */ 215 if (frame->can_id & CAN_EFF_FLAG) { 216 can_id = (frame->can_id & CAN_EFF_MASK) 217 << (MSCAN_EFF_RTR_SHIFT + 1); 218 if (rtr) 219 can_id |= 1 << MSCAN_EFF_RTR_SHIFT; 220 out_be16(®s->tx.idr3_2, can_id); 221 222 can_id >>= 16; 223 /* EFF_FLAGS are inbetween the IDs :( */ 224 can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0) 225 | MSCAN_EFF_FLAGS; 226 } else { 227 can_id = (frame->can_id & CAN_SFF_MASK) 228 << (MSCAN_SFF_RTR_SHIFT + 1); 229 if (rtr) 230 can_id |= 1 << MSCAN_SFF_RTR_SHIFT; 231 } 232 out_be16(®s->tx.idr1_0, can_id); 233 234 if (!rtr) { 235 void __iomem *data = ®s->tx.dsr1_0; 236 u16 *payload = (u16 *)frame->data; 237 238 /* It is safe to write into dsr[dlc+1] */ 239 for (i = 0; i < (frame->can_dlc + 1) / 2; i++) { 240 out_be16(data, *payload++); 241 data += 2 + _MSCAN_RESERVED_DSR_SIZE; 242 } 243 } 244 245 out_8(®s->tx.dlr, frame->can_dlc); 246 out_8(®s->tx.tbpr, priv->cur_pri); 247 248 /* Start transmission. */ 249 out_8(®s->cantflg, 1 << buf_id); 250 251 if (!test_bit(F_TX_PROGRESS, &priv->flags)) 252 dev->trans_start = jiffies; 253 254 list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head); 255 256 can_put_echo_skb(skb, dev, buf_id); 257 258 /* Enable interrupt. */ 259 priv->tx_active |= 1 << buf_id; 260 out_8(®s->cantier, priv->tx_active); 261 262 return NETDEV_TX_OK; 263} 264 265/* This function returns the old state to see where we came from */ 266static enum can_state check_set_state(struct net_device *dev, u8 canrflg) 267{ 268 struct mscan_priv *priv = netdev_priv(dev); 269 enum can_state state, old_state = priv->can.state; 270 271 if (canrflg & MSCAN_CSCIF && old_state <= CAN_STATE_BUS_OFF) { 272 state = state_map[max(MSCAN_STATE_RX(canrflg), 273 MSCAN_STATE_TX(canrflg))]; 274 priv->can.state = state; 275 } 276 return old_state; 277} 278 279static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame) 280{ 281 struct mscan_priv *priv = netdev_priv(dev); 282 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 283 u32 can_id; 284 int i; 285 286 can_id = in_be16(®s->rx.idr1_0); 287 if (can_id & (1 << 3)) { 288 frame->can_id = CAN_EFF_FLAG; 289 can_id = ((can_id << 16) | in_be16(®s->rx.idr3_2)); 290 can_id = ((can_id & 0xffe00000) | 291 ((can_id & 0x7ffff) << 2)) >> 2; 292 } else { 293 can_id >>= 4; 294 frame->can_id = 0; 295 } 296 297 frame->can_id |= can_id >> 1; 298 if (can_id & 1) 299 frame->can_id |= CAN_RTR_FLAG; 300 frame->can_dlc = in_8(®s->rx.dlr) & 0xf; 301 302 if (!(frame->can_id & CAN_RTR_FLAG)) { 303 void __iomem *data = ®s->rx.dsr1_0; 304 u16 *payload = (u16 *)frame->data; 305 306 for (i = 0; i < (frame->can_dlc + 1) / 2; i++) { 307 *payload++ = in_be16(data); 308 data += 2 + _MSCAN_RESERVED_DSR_SIZE; 309 } 310 } 311 312 out_8(®s->canrflg, MSCAN_RXF); 313} 314 315static void mscan_get_err_frame(struct net_device *dev, struct can_frame *frame, 316 u8 canrflg) 317{ 318 struct mscan_priv *priv = netdev_priv(dev); 319 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 320 struct net_device_stats *stats = &dev->stats; 321 enum can_state old_state; 322 323 dev_dbg(dev->dev.parent, "error interrupt (canrflg=%#x)\n", canrflg); 324 frame->can_id = CAN_ERR_FLAG; 325 326 if (canrflg & MSCAN_OVRIF) { 327 frame->can_id |= CAN_ERR_CRTL; 328 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 329 stats->rx_over_errors++; 330 stats->rx_errors++; 331 } else { 332 frame->data[1] = 0; 333 } 334 335 old_state = check_set_state(dev, canrflg); 336 /* State changed */ 337 if (old_state != priv->can.state) { 338 switch (priv->can.state) { 339 case CAN_STATE_ERROR_WARNING: 340 frame->can_id |= CAN_ERR_CRTL; 341 priv->can.can_stats.error_warning++; 342 if ((priv->shadow_statflg & MSCAN_RSTAT_MSK) < 343 (canrflg & MSCAN_RSTAT_MSK)) 344 frame->data[1] |= CAN_ERR_CRTL_RX_WARNING; 345 if ((priv->shadow_statflg & MSCAN_TSTAT_MSK) < 346 (canrflg & MSCAN_TSTAT_MSK)) 347 frame->data[1] |= CAN_ERR_CRTL_TX_WARNING; 348 break; 349 case CAN_STATE_ERROR_PASSIVE: 350 frame->can_id |= CAN_ERR_CRTL; 351 priv->can.can_stats.error_passive++; 352 frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 353 break; 354 case CAN_STATE_BUS_OFF: 355 frame->can_id |= CAN_ERR_BUSOFF; 356 /* 357 * The MSCAN on the MPC5200 does recover from bus-off 358 * automatically. To avoid that we stop the chip doing 359 * a light-weight stop (we are in irq-context). 360 */ 361 out_8(®s->cantier, 0); 362 out_8(®s->canrier, 0); 363 setbits8(®s->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ); 364 can_bus_off(dev); 365 break; 366 default: 367 break; 368 } 369 } 370 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK; 371 frame->can_dlc = CAN_ERR_DLC; 372 out_8(®s->canrflg, MSCAN_ERR_IF); 373} 374 375static int mscan_rx_poll(struct napi_struct *napi, int quota) 376{ 377 struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi); 378 struct net_device *dev = napi->dev; 379 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 380 struct net_device_stats *stats = &dev->stats; 381 int npackets = 0; 382 int ret = 1; 383 struct sk_buff *skb; 384 struct can_frame *frame; 385 u8 canrflg; 386 387 while (npackets < quota) { 388 canrflg = in_8(®s->canrflg); 389 if (!(canrflg & (MSCAN_RXF | MSCAN_ERR_IF))) 390 break; 391 392 skb = alloc_can_skb(dev, &frame); 393 if (!skb) { 394 if (printk_ratelimit()) 395 dev_notice(dev->dev.parent, "packet dropped\n"); 396 stats->rx_dropped++; 397 out_8(®s->canrflg, canrflg); 398 continue; 399 } 400 401 if (canrflg & MSCAN_RXF) 402 mscan_get_rx_frame(dev, frame); 403 else if (canrflg & MSCAN_ERR_IF) 404 mscan_get_err_frame(dev, frame, canrflg); 405 406 stats->rx_packets++; 407 stats->rx_bytes += frame->can_dlc; 408 npackets++; 409 netif_receive_skb(skb); 410 } 411 412 if (!(in_8(®s->canrflg) & (MSCAN_RXF | MSCAN_ERR_IF))) { 413 napi_complete(&priv->napi); 414 clear_bit(F_RX_PROGRESS, &priv->flags); 415 if (priv->can.state < CAN_STATE_BUS_OFF) 416 out_8(®s->canrier, priv->shadow_canrier); 417 ret = 0; 418 } 419 return ret; 420} 421 422static irqreturn_t mscan_isr(int irq, void *dev_id) 423{ 424 struct net_device *dev = (struct net_device *)dev_id; 425 struct mscan_priv *priv = netdev_priv(dev); 426 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 427 struct net_device_stats *stats = &dev->stats; 428 u8 cantier, cantflg, canrflg; 429 irqreturn_t ret = IRQ_NONE; 430 431 cantier = in_8(®s->cantier) & MSCAN_TXE; 432 cantflg = in_8(®s->cantflg) & cantier; 433 434 if (cantier && cantflg) { 435 struct list_head *tmp, *pos; 436 437 list_for_each_safe(pos, tmp, &priv->tx_head) { 438 struct tx_queue_entry *entry = 439 list_entry(pos, struct tx_queue_entry, list); 440 u8 mask = entry->mask; 441 442 if (!(cantflg & mask)) 443 continue; 444 445 out_8(®s->cantbsel, mask); 446 stats->tx_bytes += in_8(®s->tx.dlr); 447 stats->tx_packets++; 448 can_get_echo_skb(dev, entry->id); 449 priv->tx_active &= ~mask; 450 list_del(pos); 451 } 452 453 if (list_empty(&priv->tx_head)) { 454 clear_bit(F_TX_WAIT_ALL, &priv->flags); 455 clear_bit(F_TX_PROGRESS, &priv->flags); 456 priv->cur_pri = 0; 457 } else { 458 dev->trans_start = jiffies; 459 } 460 461 if (!test_bit(F_TX_WAIT_ALL, &priv->flags)) 462 netif_wake_queue(dev); 463 464 out_8(®s->cantier, priv->tx_active); 465 ret = IRQ_HANDLED; 466 } 467 468 canrflg = in_8(®s->canrflg); 469 if ((canrflg & ~MSCAN_STAT_MSK) && 470 !test_and_set_bit(F_RX_PROGRESS, &priv->flags)) { 471 if (canrflg & ~MSCAN_STAT_MSK) { 472 priv->shadow_canrier = in_8(®s->canrier); 473 out_8(®s->canrier, 0); 474 napi_schedule(&priv->napi); 475 ret = IRQ_HANDLED; 476 } else { 477 clear_bit(F_RX_PROGRESS, &priv->flags); 478 } 479 } 480 return ret; 481} 482 483static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode) 484{ 485 struct mscan_priv *priv = netdev_priv(dev); 486 int ret = 0; 487 488 if (!priv->open_time) 489 return -EINVAL; 490 491 switch (mode) { 492 case CAN_MODE_START: 493 if (priv->can.state <= CAN_STATE_BUS_OFF) 494 mscan_set_mode(dev, MSCAN_INIT_MODE); 495 ret = mscan_start(dev); 496 if (ret) 497 break; 498 if (netif_queue_stopped(dev)) 499 netif_wake_queue(dev); 500 break; 501 502 default: 503 ret = -EOPNOTSUPP; 504 break; 505 } 506 return ret; 507} 508 509static int mscan_do_set_bittiming(struct net_device *dev) 510{ 511 struct mscan_priv *priv = netdev_priv(dev); 512 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 513 struct can_bittiming *bt = &priv->can.bittiming; 514 u8 btr0, btr1; 515 516 btr0 = BTR0_SET_BRP(bt->brp) | BTR0_SET_SJW(bt->sjw); 517 btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) | 518 BTR1_SET_TSEG2(bt->phase_seg2) | 519 BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)); 520 521 dev_info(dev->dev.parent, "setting BTR0=0x%02x BTR1=0x%02x\n", 522 btr0, btr1); 523 524 out_8(®s->canbtr0, btr0); 525 out_8(®s->canbtr1, btr1); 526 527 return 0; 528} 529 530static int mscan_open(struct net_device *dev) 531{ 532 int ret; 533 struct mscan_priv *priv = netdev_priv(dev); 534 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 535 536 /* common open */ 537 ret = open_candev(dev); 538 if (ret) 539 return ret; 540 541 napi_enable(&priv->napi); 542 543 ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev); 544 if (ret < 0) { 545 napi_disable(&priv->napi); 546 printk(KERN_ERR "%s - failed to attach interrupt\n", 547 dev->name); 548 return ret; 549 } 550 551 priv->open_time = jiffies; 552 553 clrbits8(®s->canctl1, MSCAN_LISTEN); 554 555 ret = mscan_start(dev); 556 if (ret) 557 return ret; 558 559 netif_start_queue(dev); 560 561 return 0; 562} 563 564static int mscan_close(struct net_device *dev) 565{ 566 struct mscan_priv *priv = netdev_priv(dev); 567 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 568 569 netif_stop_queue(dev); 570 napi_disable(&priv->napi); 571 572 out_8(®s->cantier, 0); 573 out_8(®s->canrier, 0); 574 mscan_set_mode(dev, MSCAN_INIT_MODE); 575 close_candev(dev); 576 free_irq(dev->irq, dev); 577 priv->open_time = 0; 578 579 return 0; 580} 581 582static const struct net_device_ops mscan_netdev_ops = { 583 .ndo_open = mscan_open, 584 .ndo_stop = mscan_close, 585 .ndo_start_xmit = mscan_start_xmit, 586}; 587 588int register_mscandev(struct net_device *dev, int clock_src) 589{ 590 struct mscan_priv *priv = netdev_priv(dev); 591 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 592 u8 ctl1; 593 594 ctl1 = in_8(®s->canctl1); 595 if (clock_src) 596 ctl1 |= MSCAN_CLKSRC; 597 else 598 ctl1 &= ~MSCAN_CLKSRC; 599 600 ctl1 |= MSCAN_CANE; 601 out_8(®s->canctl1, ctl1); 602 udelay(100); 603 604 /* acceptance mask/acceptance code (accept everything) */ 605 out_be16(®s->canidar1_0, 0); 606 out_be16(®s->canidar3_2, 0); 607 out_be16(®s->canidar5_4, 0); 608 out_be16(®s->canidar7_6, 0); 609 610 out_be16(®s->canidmr1_0, 0xffff); 611 out_be16(®s->canidmr3_2, 0xffff); 612 out_be16(®s->canidmr5_4, 0xffff); 613 out_be16(®s->canidmr7_6, 0xffff); 614 /* Two 32 bit Acceptance Filters */ 615 out_8(®s->canidac, MSCAN_AF_32BIT); 616 617 mscan_set_mode(dev, MSCAN_INIT_MODE); 618 619 return register_candev(dev); 620} 621 622void unregister_mscandev(struct net_device *dev) 623{ 624 struct mscan_priv *priv = netdev_priv(dev); 625 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 626 mscan_set_mode(dev, MSCAN_INIT_MODE); 627 clrbits8(®s->canctl1, MSCAN_CANE); 628 unregister_candev(dev); 629} 630 631struct net_device *alloc_mscandev(void) 632{ 633 struct net_device *dev; 634 struct mscan_priv *priv; 635 int i; 636 637 dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX); 638 if (!dev) 639 return NULL; 640 priv = netdev_priv(dev); 641 642 dev->netdev_ops = &mscan_netdev_ops; 643 644 dev->flags |= IFF_ECHO; /* we support local echo */ 645 646 netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8); 647 648 priv->can.bittiming_const = &mscan_bittiming_const; 649 priv->can.do_set_bittiming = mscan_do_set_bittiming; 650 priv->can.do_set_mode = mscan_do_set_mode; 651 652 for (i = 0; i < TX_QUEUE_SIZE; i++) { 653 priv->tx_queue[i].id = i; 654 priv->tx_queue[i].mask = 1 << i; 655 } 656 657 return dev; 658} 659 660MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>"); 661MODULE_LICENSE("GPL v2"); 662MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips"); 663