mscan.c revision c7cd606f60e7679c7f9eee7010f02a6f000209c1
1/* 2 * CAN bus driver for the alone generic (as possible as) MSCAN controller. 3 * 4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>, 5 * Varma Electronics Oy 6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com> 7 * Copytight (C) 2008-2009 Pengutronix <kernel@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23#include <linux/kernel.h> 24#include <linux/module.h> 25#include <linux/interrupt.h> 26#include <linux/delay.h> 27#include <linux/netdevice.h> 28#include <linux/if_arp.h> 29#include <linux/if_ether.h> 30#include <linux/list.h> 31#include <linux/can.h> 32#include <linux/can/dev.h> 33#include <linux/can/error.h> 34#include <linux/io.h> 35 36#include "mscan.h" 37 38static struct can_bittiming_const mscan_bittiming_const = { 39 .name = "mscan", 40 .tseg1_min = 4, 41 .tseg1_max = 16, 42 .tseg2_min = 2, 43 .tseg2_max = 8, 44 .sjw_max = 4, 45 .brp_min = 1, 46 .brp_max = 64, 47 .brp_inc = 1, 48}; 49 50struct mscan_state { 51 u8 mode; 52 u8 canrier; 53 u8 cantier; 54}; 55 56static enum can_state state_map[] = { 57 CAN_STATE_ERROR_ACTIVE, 58 CAN_STATE_ERROR_WARNING, 59 CAN_STATE_ERROR_PASSIVE, 60 CAN_STATE_BUS_OFF 61}; 62 63static int mscan_set_mode(struct net_device *dev, u8 mode) 64{ 65 struct mscan_priv *priv = netdev_priv(dev); 66 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 67 int ret = 0; 68 int i; 69 u8 canctl1; 70 71 if (mode != MSCAN_NORMAL_MODE) { 72 if (priv->tx_active) { 73 /* Abort transfers before going to sleep */# 74 out_8(®s->cantarq, priv->tx_active); 75 /* Suppress TX done interrupts */ 76 out_8(®s->cantier, 0); 77 } 78 79 canctl1 = in_8(®s->canctl1); 80 if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) { 81 setbits8(®s->canctl0, MSCAN_SLPRQ); 82 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { 83 if (in_8(®s->canctl1) & MSCAN_SLPAK) 84 break; 85 udelay(100); 86 } 87 /* 88 * The mscan controller will fail to enter sleep mode, 89 * while there are irregular activities on bus, like 90 * somebody keeps retransmitting. This behavior is 91 * undocumented and seems to differ between mscan built 92 * in mpc5200b and mpc5200. We proceed in that case, 93 * since otherwise the slprq will be kept set and the 94 * controller will get stuck. NOTE: INITRQ or CSWAI 95 * will abort all active transmit actions, if still 96 * any, at once. 97 */ 98 if (i >= MSCAN_SET_MODE_RETRIES) 99 dev_dbg(dev->dev.parent, 100 "device failed to enter sleep mode. " 101 "We proceed anyhow.\n"); 102 else 103 priv->can.state = CAN_STATE_SLEEPING; 104 } 105 106 if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) { 107 setbits8(®s->canctl0, MSCAN_INITRQ); 108 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { 109 if (in_8(®s->canctl1) & MSCAN_INITAK) 110 break; 111 } 112 if (i >= MSCAN_SET_MODE_RETRIES) 113 ret = -ENODEV; 114 } 115 if (!ret) 116 priv->can.state = CAN_STATE_STOPPED; 117 118 if (mode & MSCAN_CSWAI) 119 setbits8(®s->canctl0, MSCAN_CSWAI); 120 121 } else { 122 canctl1 = in_8(®s->canctl1); 123 if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) { 124 clrbits8(®s->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ); 125 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { 126 canctl1 = in_8(®s->canctl1); 127 if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK))) 128 break; 129 } 130 if (i >= MSCAN_SET_MODE_RETRIES) 131 ret = -ENODEV; 132 else 133 priv->can.state = CAN_STATE_ERROR_ACTIVE; 134 } 135 } 136 return ret; 137} 138 139static int mscan_start(struct net_device *dev) 140{ 141 struct mscan_priv *priv = netdev_priv(dev); 142 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 143 u8 canrflg; 144 int err; 145 146 out_8(®s->canrier, 0); 147 148 INIT_LIST_HEAD(&priv->tx_head); 149 priv->prev_buf_id = 0; 150 priv->cur_pri = 0; 151 priv->tx_active = 0; 152 priv->shadow_canrier = 0; 153 priv->flags = 0; 154 155 err = mscan_set_mode(dev, MSCAN_NORMAL_MODE); 156 if (err) 157 return err; 158 159 canrflg = in_8(®s->canrflg); 160 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK; 161 priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg), 162 MSCAN_STATE_TX(canrflg))]; 163 out_8(®s->cantier, 0); 164 165 /* Enable receive interrupts. */ 166 out_8(®s->canrier, MSCAN_OVRIE | MSCAN_RXFIE | MSCAN_CSCIE | 167 MSCAN_RSTATE1 | MSCAN_RSTATE0 | MSCAN_TSTATE1 | MSCAN_TSTATE0); 168 169 return 0; 170} 171 172static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev) 173{ 174 struct can_frame *frame = (struct can_frame *)skb->data; 175 struct mscan_priv *priv = netdev_priv(dev); 176 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 177 int i, rtr, buf_id; 178 u32 can_id; 179 180 if (frame->can_dlc > 8) 181 return -EINVAL; 182 183 out_8(®s->cantier, 0); 184 185 i = ~priv->tx_active & MSCAN_TXE; 186 buf_id = ffs(i) - 1; 187 switch (hweight8(i)) { 188 case 0: 189 netif_stop_queue(dev); 190 dev_err(dev->dev.parent, "Tx Ring full when queue awake!\n"); 191 return NETDEV_TX_BUSY; 192 case 1: 193 /* 194 * if buf_id < 3, then current frame will be send out of order, 195 * since buffer with lower id have higher priority (hell..) 196 */ 197 netif_stop_queue(dev); 198 case 2: 199 if (buf_id < priv->prev_buf_id) { 200 priv->cur_pri++; 201 if (priv->cur_pri == 0xff) { 202 set_bit(F_TX_WAIT_ALL, &priv->flags); 203 netif_stop_queue(dev); 204 } 205 } 206 set_bit(F_TX_PROGRESS, &priv->flags); 207 break; 208 } 209 priv->prev_buf_id = buf_id; 210 out_8(®s->cantbsel, i); 211 212 rtr = frame->can_id & CAN_RTR_FLAG; 213 214 /* RTR is always the lowest bit of interest, then IDs follow */ 215 if (frame->can_id & CAN_EFF_FLAG) { 216 can_id = (frame->can_id & CAN_EFF_MASK) 217 << (MSCAN_EFF_RTR_SHIFT + 1); 218 if (rtr) 219 can_id |= 1 << MSCAN_EFF_RTR_SHIFT; 220 out_be16(®s->tx.idr3_2, can_id); 221 222 can_id >>= 16; 223 /* EFF_FLAGS are inbetween the IDs :( */ 224 can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0) 225 | MSCAN_EFF_FLAGS; 226 } else { 227 can_id = (frame->can_id & CAN_SFF_MASK) 228 << (MSCAN_SFF_RTR_SHIFT + 1); 229 if (rtr) 230 can_id |= 1 << MSCAN_SFF_RTR_SHIFT; 231 } 232 out_be16(®s->tx.idr1_0, can_id); 233 234 if (!rtr) { 235 void __iomem *data = ®s->tx.dsr1_0; 236 u16 *payload = (u16 *)frame->data; 237 238 /* It is safe to write into dsr[dlc+1] */ 239 for (i = 0; i < (frame->can_dlc + 1) / 2; i++) { 240 out_be16(data, *payload++); 241 data += 2 + _MSCAN_RESERVED_DSR_SIZE; 242 } 243 } 244 245 out_8(®s->tx.dlr, frame->can_dlc); 246 out_8(®s->tx.tbpr, priv->cur_pri); 247 248 /* Start transmission. */ 249 out_8(®s->cantflg, 1 << buf_id); 250 251 if (!test_bit(F_TX_PROGRESS, &priv->flags)) 252 dev->trans_start = jiffies; 253 254 list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head); 255 256 can_put_echo_skb(skb, dev, buf_id); 257 258 /* Enable interrupt. */ 259 priv->tx_active |= 1 << buf_id; 260 out_8(®s->cantier, priv->tx_active); 261 262 return NETDEV_TX_OK; 263} 264 265/* This function returns the old state to see where we came from */ 266static enum can_state check_set_state(struct net_device *dev, u8 canrflg) 267{ 268 struct mscan_priv *priv = netdev_priv(dev); 269 enum can_state state, old_state = priv->can.state; 270 271 if (canrflg & MSCAN_CSCIF && old_state <= CAN_STATE_BUS_OFF) { 272 state = state_map[max(MSCAN_STATE_RX(canrflg), 273 MSCAN_STATE_TX(canrflg))]; 274 priv->can.state = state; 275 } 276 return old_state; 277} 278 279static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame) 280{ 281 struct mscan_priv *priv = netdev_priv(dev); 282 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 283 u32 can_id; 284 int i; 285 286 can_id = in_be16(®s->rx.idr1_0); 287 if (can_id & (1 << 3)) { 288 frame->can_id = CAN_EFF_FLAG; 289 can_id = ((can_id << 16) | in_be16(®s->rx.idr3_2)); 290 can_id = ((can_id & 0xffe00000) | 291 ((can_id & 0x7ffff) << 2)) >> 2; 292 } else { 293 can_id >>= 4; 294 frame->can_id = 0; 295 } 296 297 frame->can_id |= can_id >> 1; 298 if (can_id & 1) 299 frame->can_id |= CAN_RTR_FLAG; 300 301 frame->can_dlc = get_can_dlc(in_8(®s->rx.dlr) & 0xf); 302 303 if (!(frame->can_id & CAN_RTR_FLAG)) { 304 void __iomem *data = ®s->rx.dsr1_0; 305 u16 *payload = (u16 *)frame->data; 306 307 for (i = 0; i < (frame->can_dlc + 1) / 2; i++) { 308 *payload++ = in_be16(data); 309 data += 2 + _MSCAN_RESERVED_DSR_SIZE; 310 } 311 } 312 313 out_8(®s->canrflg, MSCAN_RXF); 314} 315 316static void mscan_get_err_frame(struct net_device *dev, struct can_frame *frame, 317 u8 canrflg) 318{ 319 struct mscan_priv *priv = netdev_priv(dev); 320 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 321 struct net_device_stats *stats = &dev->stats; 322 enum can_state old_state; 323 324 dev_dbg(dev->dev.parent, "error interrupt (canrflg=%#x)\n", canrflg); 325 frame->can_id = CAN_ERR_FLAG; 326 327 if (canrflg & MSCAN_OVRIF) { 328 frame->can_id |= CAN_ERR_CRTL; 329 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 330 stats->rx_over_errors++; 331 stats->rx_errors++; 332 } else { 333 frame->data[1] = 0; 334 } 335 336 old_state = check_set_state(dev, canrflg); 337 /* State changed */ 338 if (old_state != priv->can.state) { 339 switch (priv->can.state) { 340 case CAN_STATE_ERROR_WARNING: 341 frame->can_id |= CAN_ERR_CRTL; 342 priv->can.can_stats.error_warning++; 343 if ((priv->shadow_statflg & MSCAN_RSTAT_MSK) < 344 (canrflg & MSCAN_RSTAT_MSK)) 345 frame->data[1] |= CAN_ERR_CRTL_RX_WARNING; 346 if ((priv->shadow_statflg & MSCAN_TSTAT_MSK) < 347 (canrflg & MSCAN_TSTAT_MSK)) 348 frame->data[1] |= CAN_ERR_CRTL_TX_WARNING; 349 break; 350 case CAN_STATE_ERROR_PASSIVE: 351 frame->can_id |= CAN_ERR_CRTL; 352 priv->can.can_stats.error_passive++; 353 frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 354 break; 355 case CAN_STATE_BUS_OFF: 356 frame->can_id |= CAN_ERR_BUSOFF; 357 /* 358 * The MSCAN on the MPC5200 does recover from bus-off 359 * automatically. To avoid that we stop the chip doing 360 * a light-weight stop (we are in irq-context). 361 */ 362 out_8(®s->cantier, 0); 363 out_8(®s->canrier, 0); 364 setbits8(®s->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ); 365 can_bus_off(dev); 366 break; 367 default: 368 break; 369 } 370 } 371 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK; 372 frame->can_dlc = CAN_ERR_DLC; 373 out_8(®s->canrflg, MSCAN_ERR_IF); 374} 375 376static int mscan_rx_poll(struct napi_struct *napi, int quota) 377{ 378 struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi); 379 struct net_device *dev = napi->dev; 380 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 381 struct net_device_stats *stats = &dev->stats; 382 int npackets = 0; 383 int ret = 1; 384 struct sk_buff *skb; 385 struct can_frame *frame; 386 u8 canrflg; 387 388 while (npackets < quota) { 389 canrflg = in_8(®s->canrflg); 390 if (!(canrflg & (MSCAN_RXF | MSCAN_ERR_IF))) 391 break; 392 393 skb = alloc_can_skb(dev, &frame); 394 if (!skb) { 395 if (printk_ratelimit()) 396 dev_notice(dev->dev.parent, "packet dropped\n"); 397 stats->rx_dropped++; 398 out_8(®s->canrflg, canrflg); 399 continue; 400 } 401 402 if (canrflg & MSCAN_RXF) 403 mscan_get_rx_frame(dev, frame); 404 else if (canrflg & MSCAN_ERR_IF) 405 mscan_get_err_frame(dev, frame, canrflg); 406 407 stats->rx_packets++; 408 stats->rx_bytes += frame->can_dlc; 409 npackets++; 410 netif_receive_skb(skb); 411 } 412 413 if (!(in_8(®s->canrflg) & (MSCAN_RXF | MSCAN_ERR_IF))) { 414 napi_complete(&priv->napi); 415 clear_bit(F_RX_PROGRESS, &priv->flags); 416 if (priv->can.state < CAN_STATE_BUS_OFF) 417 out_8(®s->canrier, priv->shadow_canrier); 418 ret = 0; 419 } 420 return ret; 421} 422 423static irqreturn_t mscan_isr(int irq, void *dev_id) 424{ 425 struct net_device *dev = (struct net_device *)dev_id; 426 struct mscan_priv *priv = netdev_priv(dev); 427 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 428 struct net_device_stats *stats = &dev->stats; 429 u8 cantier, cantflg, canrflg; 430 irqreturn_t ret = IRQ_NONE; 431 432 cantier = in_8(®s->cantier) & MSCAN_TXE; 433 cantflg = in_8(®s->cantflg) & cantier; 434 435 if (cantier && cantflg) { 436 struct list_head *tmp, *pos; 437 438 list_for_each_safe(pos, tmp, &priv->tx_head) { 439 struct tx_queue_entry *entry = 440 list_entry(pos, struct tx_queue_entry, list); 441 u8 mask = entry->mask; 442 443 if (!(cantflg & mask)) 444 continue; 445 446 out_8(®s->cantbsel, mask); 447 stats->tx_bytes += in_8(®s->tx.dlr); 448 stats->tx_packets++; 449 can_get_echo_skb(dev, entry->id); 450 priv->tx_active &= ~mask; 451 list_del(pos); 452 } 453 454 if (list_empty(&priv->tx_head)) { 455 clear_bit(F_TX_WAIT_ALL, &priv->flags); 456 clear_bit(F_TX_PROGRESS, &priv->flags); 457 priv->cur_pri = 0; 458 } else { 459 dev->trans_start = jiffies; 460 } 461 462 if (!test_bit(F_TX_WAIT_ALL, &priv->flags)) 463 netif_wake_queue(dev); 464 465 out_8(®s->cantier, priv->tx_active); 466 ret = IRQ_HANDLED; 467 } 468 469 canrflg = in_8(®s->canrflg); 470 if ((canrflg & ~MSCAN_STAT_MSK) && 471 !test_and_set_bit(F_RX_PROGRESS, &priv->flags)) { 472 if (canrflg & ~MSCAN_STAT_MSK) { 473 priv->shadow_canrier = in_8(®s->canrier); 474 out_8(®s->canrier, 0); 475 napi_schedule(&priv->napi); 476 ret = IRQ_HANDLED; 477 } else { 478 clear_bit(F_RX_PROGRESS, &priv->flags); 479 } 480 } 481 return ret; 482} 483 484static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode) 485{ 486 struct mscan_priv *priv = netdev_priv(dev); 487 int ret = 0; 488 489 if (!priv->open_time) 490 return -EINVAL; 491 492 switch (mode) { 493 case CAN_MODE_START: 494 if (priv->can.state <= CAN_STATE_BUS_OFF) 495 mscan_set_mode(dev, MSCAN_INIT_MODE); 496 ret = mscan_start(dev); 497 if (ret) 498 break; 499 if (netif_queue_stopped(dev)) 500 netif_wake_queue(dev); 501 break; 502 503 default: 504 ret = -EOPNOTSUPP; 505 break; 506 } 507 return ret; 508} 509 510static int mscan_do_set_bittiming(struct net_device *dev) 511{ 512 struct mscan_priv *priv = netdev_priv(dev); 513 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 514 struct can_bittiming *bt = &priv->can.bittiming; 515 u8 btr0, btr1; 516 517 btr0 = BTR0_SET_BRP(bt->brp) | BTR0_SET_SJW(bt->sjw); 518 btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) | 519 BTR1_SET_TSEG2(bt->phase_seg2) | 520 BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)); 521 522 dev_info(dev->dev.parent, "setting BTR0=0x%02x BTR1=0x%02x\n", 523 btr0, btr1); 524 525 out_8(®s->canbtr0, btr0); 526 out_8(®s->canbtr1, btr1); 527 528 return 0; 529} 530 531static int mscan_open(struct net_device *dev) 532{ 533 int ret; 534 struct mscan_priv *priv = netdev_priv(dev); 535 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 536 537 /* common open */ 538 ret = open_candev(dev); 539 if (ret) 540 return ret; 541 542 napi_enable(&priv->napi); 543 544 ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev); 545 if (ret < 0) { 546 dev_err(dev->dev.parent, "failed to attach interrupt\n"); 547 goto exit_napi_disable; 548 } 549 550 priv->open_time = jiffies; 551 552 clrbits8(®s->canctl1, MSCAN_LISTEN); 553 554 ret = mscan_start(dev); 555 if (ret) 556 goto exit_free_irq; 557 558 netif_start_queue(dev); 559 560 return 0; 561 562exit_free_irq: 563 priv->open_time = 0; 564 free_irq(dev->irq, dev); 565exit_napi_disable: 566 napi_disable(&priv->napi); 567 close_candev(dev); 568 return ret; 569} 570 571static int mscan_close(struct net_device *dev) 572{ 573 struct mscan_priv *priv = netdev_priv(dev); 574 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 575 576 netif_stop_queue(dev); 577 napi_disable(&priv->napi); 578 579 out_8(®s->cantier, 0); 580 out_8(®s->canrier, 0); 581 mscan_set_mode(dev, MSCAN_INIT_MODE); 582 close_candev(dev); 583 free_irq(dev->irq, dev); 584 priv->open_time = 0; 585 586 return 0; 587} 588 589static const struct net_device_ops mscan_netdev_ops = { 590 .ndo_open = mscan_open, 591 .ndo_stop = mscan_close, 592 .ndo_start_xmit = mscan_start_xmit, 593}; 594 595int register_mscandev(struct net_device *dev, int clock_src) 596{ 597 struct mscan_priv *priv = netdev_priv(dev); 598 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 599 u8 ctl1; 600 601 ctl1 = in_8(®s->canctl1); 602 if (clock_src) 603 ctl1 |= MSCAN_CLKSRC; 604 else 605 ctl1 &= ~MSCAN_CLKSRC; 606 607 ctl1 |= MSCAN_CANE; 608 out_8(®s->canctl1, ctl1); 609 udelay(100); 610 611 /* acceptance mask/acceptance code (accept everything) */ 612 out_be16(®s->canidar1_0, 0); 613 out_be16(®s->canidar3_2, 0); 614 out_be16(®s->canidar5_4, 0); 615 out_be16(®s->canidar7_6, 0); 616 617 out_be16(®s->canidmr1_0, 0xffff); 618 out_be16(®s->canidmr3_2, 0xffff); 619 out_be16(®s->canidmr5_4, 0xffff); 620 out_be16(®s->canidmr7_6, 0xffff); 621 /* Two 32 bit Acceptance Filters */ 622 out_8(®s->canidac, MSCAN_AF_32BIT); 623 624 mscan_set_mode(dev, MSCAN_INIT_MODE); 625 626 return register_candev(dev); 627} 628 629void unregister_mscandev(struct net_device *dev) 630{ 631 struct mscan_priv *priv = netdev_priv(dev); 632 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 633 mscan_set_mode(dev, MSCAN_INIT_MODE); 634 clrbits8(®s->canctl1, MSCAN_CANE); 635 unregister_candev(dev); 636} 637 638struct net_device *alloc_mscandev(void) 639{ 640 struct net_device *dev; 641 struct mscan_priv *priv; 642 int i; 643 644 dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX); 645 if (!dev) 646 return NULL; 647 priv = netdev_priv(dev); 648 649 dev->netdev_ops = &mscan_netdev_ops; 650 651 dev->flags |= IFF_ECHO; /* we support local echo */ 652 653 netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8); 654 655 priv->can.bittiming_const = &mscan_bittiming_const; 656 priv->can.do_set_bittiming = mscan_do_set_bittiming; 657 priv->can.do_set_mode = mscan_do_set_mode; 658 659 for (i = 0; i < TX_QUEUE_SIZE; i++) { 660 priv->tx_queue[i].id = i; 661 priv->tx_queue[i].mask = 1 << i; 662 } 663 664 return dev; 665} 666 667MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>"); 668MODULE_LICENSE("GPL v2"); 669MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips"); 670