pch_can.c revision 15ffc8fddf72712cc45d51c64bd500760ec63c80
1/* 2 * Copyright (C) 1999 - 2010 Intel Corporation. 3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19#include <linux/interrupt.h> 20#include <linux/delay.h> 21#include <linux/io.h> 22#include <linux/module.h> 23#include <linux/sched.h> 24#include <linux/pci.h> 25#include <linux/init.h> 26#include <linux/kernel.h> 27#include <linux/types.h> 28#include <linux/errno.h> 29#include <linux/netdevice.h> 30#include <linux/skbuff.h> 31#include <linux/can.h> 32#include <linux/can/dev.h> 33#include <linux/can/error.h> 34 35#define PCH_ENABLE 1 /* The enable flag */ 36#define PCH_DISABLE 0 /* The disable flag */ 37#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */ 38#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */ 39#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1)) 40#define PCH_CTRL_CCE BIT(6) 41#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */ 42#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */ 43#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */ 44 45#define PCH_CMASK_RX_TX_SET 0x00f3 46#define PCH_CMASK_RX_TX_GET 0x0073 47#define PCH_CMASK_ALL 0xff 48#define PCH_CMASK_NEWDAT BIT(2) 49#define PCH_CMASK_CLRINTPND BIT(3) 50#define PCH_CMASK_CTRL BIT(4) 51#define PCH_CMASK_ARB BIT(5) 52#define PCH_CMASK_MASK BIT(6) 53#define PCH_CMASK_RDWR BIT(7) 54#define PCH_IF_MCONT_NEWDAT BIT(15) 55#define PCH_IF_MCONT_MSGLOST BIT(14) 56#define PCH_IF_MCONT_INTPND BIT(13) 57#define PCH_IF_MCONT_UMASK BIT(12) 58#define PCH_IF_MCONT_TXIE BIT(11) 59#define PCH_IF_MCONT_RXIE BIT(10) 60#define PCH_IF_MCONT_RMTEN BIT(9) 61#define PCH_IF_MCONT_TXRQXT BIT(8) 62#define PCH_IF_MCONT_EOB BIT(7) 63#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 64#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15)) 65#define PCH_ID2_DIR BIT(13) 66#define PCH_ID2_XTD BIT(14) 67#define PCH_ID_MSGVAL BIT(15) 68#define PCH_IF_CREQ_BUSY BIT(15) 69 70#define PCH_STATUS_INT 0x8000 71#define PCH_REC 0x00007f00 72#define PCH_TEC 0x000000ff 73 74#define PCH_TX_OK BIT(3) 75#define PCH_RX_OK BIT(4) 76#define PCH_EPASSIV BIT(5) 77#define PCH_EWARN BIT(6) 78#define PCH_BUS_OFF BIT(7) 79#define PCH_LEC0 BIT(0) 80#define PCH_LEC1 BIT(1) 81#define PCH_LEC2 BIT(2) 82#define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2) 83#define PCH_STUF_ERR PCH_LEC0 84#define PCH_FORM_ERR PCH_LEC1 85#define PCH_ACK_ERR (PCH_LEC0 | PCH_LEC1) 86#define PCH_BIT1_ERR PCH_LEC2 87#define PCH_BIT0_ERR (PCH_LEC0 | PCH_LEC2) 88#define PCH_CRC_ERR (PCH_LEC1 | PCH_LEC2) 89 90/* bit position of certain controller bits. */ 91#define PCH_BIT_BRP 0 92#define PCH_BIT_SJW 6 93#define PCH_BIT_TSEG1 8 94#define PCH_BIT_TSEG2 12 95#define PCH_BIT_BRPE_BRPE 6 96#define PCH_MSK_BITT_BRP 0x3f 97#define PCH_MSK_BRPE_BRPE 0x3c0 98#define PCH_MSK_CTRL_IE_SIE_EIE 0x07 99#define PCH_COUNTER_LIMIT 10 100 101#define PCH_CAN_CLK 50000000 /* 50MHz */ 102 103/* Define the number of message object. 104 * PCH CAN communications are done via Message RAM. 105 * The Message RAM consists of 32 message objects. */ 106#define PCH_RX_OBJ_NUM 26 107#define PCH_TX_OBJ_NUM 6 108#define PCH_RX_OBJ_START 1 109#define PCH_RX_OBJ_END PCH_RX_OBJ_NUM 110#define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1) 111#define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM) 112 113#define PCH_FIFO_THRESH 16 114 115enum pch_ifreg { 116 PCH_RX_IFREG, 117 PCH_TX_IFREG, 118}; 119 120enum pch_can_mode { 121 PCH_CAN_ENABLE, 122 PCH_CAN_DISABLE, 123 PCH_CAN_ALL, 124 PCH_CAN_NONE, 125 PCH_CAN_STOP, 126 PCH_CAN_RUN 127}; 128 129struct pch_can_if_regs { 130 u32 creq; 131 u32 cmask; 132 u32 mask1; 133 u32 mask2; 134 u32 id1; 135 u32 id2; 136 u32 mcont; 137 u32 dataa1; 138 u32 dataa2; 139 u32 datab1; 140 u32 datab2; 141 u32 rsv[13]; 142}; 143 144struct pch_can_regs { 145 u32 cont; 146 u32 stat; 147 u32 errc; 148 u32 bitt; 149 u32 intr; 150 u32 opt; 151 u32 brpe; 152 u32 reserve; 153 struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */ 154 u32 reserve1[8]; 155 u32 treq1; 156 u32 treq2; 157 u32 reserve2[6]; 158 u32 data1; 159 u32 data2; 160 u32 reserve3[6]; 161 u32 canipend1; 162 u32 canipend2; 163 u32 reserve4[6]; 164 u32 canmval1; 165 u32 canmval2; 166 u32 reserve5[37]; 167 u32 srst; 168}; 169 170struct pch_can_priv { 171 struct can_priv can; 172 unsigned int can_num; 173 struct pci_dev *dev; 174 int tx_enable[PCH_TX_OBJ_END]; 175 int rx_enable[PCH_TX_OBJ_END]; 176 int rx_link[PCH_TX_OBJ_END]; 177 unsigned int int_enables; 178 unsigned int int_stat; 179 struct net_device *ndev; 180 spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/ 181 unsigned int msg_obj[PCH_TX_OBJ_END]; 182 struct pch_can_regs __iomem *regs; 183 struct napi_struct napi; 184 unsigned int tx_obj; /* Point next Tx Obj index */ 185 unsigned int use_msi; 186}; 187 188static struct can_bittiming_const pch_can_bittiming_const = { 189 .name = KBUILD_MODNAME, 190 .tseg1_min = 1, 191 .tseg1_max = 16, 192 .tseg2_min = 1, 193 .tseg2_max = 8, 194 .sjw_max = 4, 195 .brp_min = 1, 196 .brp_max = 1024, /* 6bit + extended 4bit */ 197 .brp_inc = 1, 198}; 199 200static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = { 201 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,}, 202 {0,} 203}; 204MODULE_DEVICE_TABLE(pci, pch_pci_tbl); 205 206static inline void pch_can_bit_set(void __iomem *addr, u32 mask) 207{ 208 iowrite32(ioread32(addr) | mask, addr); 209} 210 211static inline void pch_can_bit_clear(void __iomem *addr, u32 mask) 212{ 213 iowrite32(ioread32(addr) & ~mask, addr); 214} 215 216static void pch_can_set_run_mode(struct pch_can_priv *priv, 217 enum pch_can_mode mode) 218{ 219 switch (mode) { 220 case PCH_CAN_RUN: 221 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT); 222 break; 223 224 case PCH_CAN_STOP: 225 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT); 226 break; 227 228 default: 229 dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__); 230 break; 231 } 232} 233 234static void pch_can_set_optmode(struct pch_can_priv *priv) 235{ 236 u32 reg_val = ioread32(&priv->regs->opt); 237 238 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 239 reg_val |= PCH_OPT_SILENT; 240 241 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 242 reg_val |= PCH_OPT_LBACK; 243 244 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT); 245 iowrite32(reg_val, &priv->regs->opt); 246} 247 248static void pch_can_set_int_custom(struct pch_can_priv *priv) 249{ 250 /* Clearing the IE, SIE and EIE bits of Can control register. */ 251 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 252 253 /* Appropriately setting them. */ 254 pch_can_bit_set(&priv->regs->cont, 255 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1)); 256} 257 258/* This function retrieves interrupt enabled for the CAN device. */ 259static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables) 260{ 261 /* Obtaining the status of IE, SIE and EIE interrupt bits. */ 262 *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1); 263} 264 265static void pch_can_set_int_enables(struct pch_can_priv *priv, 266 enum pch_can_mode interrupt_no) 267{ 268 switch (interrupt_no) { 269 case PCH_CAN_ENABLE: 270 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE); 271 break; 272 273 case PCH_CAN_DISABLE: 274 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE); 275 break; 276 277 case PCH_CAN_ALL: 278 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 279 break; 280 281 case PCH_CAN_NONE: 282 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 283 break; 284 285 default: 286 dev_err(&priv->ndev->dev, "Invalid interrupt number.\n"); 287 break; 288 } 289} 290 291static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num) 292{ 293 u32 counter = PCH_COUNTER_LIMIT; 294 u32 ifx_creq; 295 296 iowrite32(num, creq_addr); 297 while (counter) { 298 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY; 299 if (!ifx_creq) 300 break; 301 counter--; 302 udelay(1); 303 } 304 if (!counter) 305 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__); 306} 307 308static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, 309 u32 set, enum pch_ifreg dir) 310{ 311 unsigned long flags; 312 u32 ie; 313 314 if (dir) 315 ie = PCH_IF_MCONT_TXIE; 316 else 317 ie = PCH_IF_MCONT_RXIE; 318 319 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 320 /* Reading the receive buffer data from RAM to Interface1 registers */ 321 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); 322 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 323 324 /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */ 325 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL, 326 &priv->regs->ifregs[dir].cmask); 327 328 if (set == PCH_ENABLE) { 329 /* Setting the MsgVal and RxIE bits */ 330 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie); 331 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); 332 333 } else if (set == PCH_DISABLE) { 334 /* Resetting the MsgVal and RxIE bits */ 335 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie); 336 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); 337 } 338 339 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 340 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 341} 342 343 344static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set) 345{ 346 int i; 347 348 /* Traversing to obtain the object configured as receivers. */ 349 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) 350 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG); 351} 352 353static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set) 354{ 355 int i; 356 357 /* Traversing to obtain the object configured as transmit object. */ 358 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 359 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG); 360} 361 362static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, 363 enum pch_ifreg dir) 364{ 365 unsigned long flags; 366 u32 ie, enable; 367 368 if (dir) 369 ie = PCH_IF_MCONT_RXIE; 370 else 371 ie = PCH_IF_MCONT_TXIE; 372 373 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 374 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); 375 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 376 377 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) && 378 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) { 379 enable = 1; 380 } else { 381 enable = 0; 382 } 383 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 384 return enable; 385} 386 387static int pch_can_int_pending(struct pch_can_priv *priv) 388{ 389 return ioread32(&priv->regs->intr) & 0xffff; 390} 391 392static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, 393 u32 buffer_num, u32 set) 394{ 395 unsigned long flags; 396 397 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 398 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 399 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 400 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, 401 &priv->regs->ifregs[0].cmask); 402 if (set == PCH_ENABLE) 403 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 404 PCH_IF_MCONT_EOB); 405 else 406 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB); 407 408 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 409 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 410} 411 412static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv, 413 u32 buffer_num, u32 *link) 414{ 415 unsigned long flags; 416 417 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 418 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 419 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 420 421 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB) 422 *link = PCH_DISABLE; 423 else 424 *link = PCH_ENABLE; 425 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 426} 427 428static void pch_can_clear_buffers(struct pch_can_priv *priv) 429{ 430 int i; 431 432 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 433 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask); 434 iowrite32(0xffff, &priv->regs->ifregs[0].mask1); 435 iowrite32(0xffff, &priv->regs->ifregs[0].mask2); 436 iowrite32(0x0, &priv->regs->ifregs[0].id1); 437 iowrite32(0x0, &priv->regs->ifregs[0].id2); 438 iowrite32(0x0, &priv->regs->ifregs[0].mcont); 439 iowrite32(0x0, &priv->regs->ifregs[0].dataa1); 440 iowrite32(0x0, &priv->regs->ifregs[0].dataa2); 441 iowrite32(0x0, &priv->regs->ifregs[0].datab1); 442 iowrite32(0x0, &priv->regs->ifregs[0].datab2); 443 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 444 PCH_CMASK_ARB | PCH_CMASK_CTRL, 445 &priv->regs->ifregs[0].cmask); 446 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 447 } 448 449 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { 450 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[1].cmask); 451 iowrite32(0xffff, &priv->regs->ifregs[1].mask1); 452 iowrite32(0xffff, &priv->regs->ifregs[1].mask2); 453 iowrite32(0x0, &priv->regs->ifregs[1].id1); 454 iowrite32(0x0, &priv->regs->ifregs[1].id2); 455 iowrite32(0x0, &priv->regs->ifregs[1].mcont); 456 iowrite32(0x0, &priv->regs->ifregs[1].dataa1); 457 iowrite32(0x0, &priv->regs->ifregs[1].dataa2); 458 iowrite32(0x0, &priv->regs->ifregs[1].datab1); 459 iowrite32(0x0, &priv->regs->ifregs[1].datab2); 460 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 461 PCH_CMASK_ARB | PCH_CMASK_CTRL, 462 &priv->regs->ifregs[1].cmask); 463 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 464 } 465} 466 467static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) 468{ 469 int i; 470 unsigned long flags; 471 472 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 473 474 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 475 iowrite32(PCH_CMASK_RX_TX_GET, 476 &priv->regs->ifregs[0].cmask); 477 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 478 479 iowrite32(0x0, &priv->regs->ifregs[0].id1); 480 iowrite32(0x0, &priv->regs->ifregs[0].id2); 481 482 pch_can_bit_set(&priv->regs->ifregs[0].mcont, 483 PCH_IF_MCONT_UMASK); 484 485 /* Set FIFO mode set to 0 except last Rx Obj*/ 486 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 487 PCH_IF_MCONT_EOB); 488 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */ 489 if (i == PCH_RX_OBJ_END) 490 pch_can_bit_set(&priv->regs->ifregs[0].mcont, 491 PCH_IF_MCONT_EOB); 492 493 iowrite32(0, &priv->regs->ifregs[0].mask1); 494 pch_can_bit_clear(&priv->regs->ifregs[0].mask2, 495 0x1fff | PCH_MASK2_MDIR_MXTD); 496 497 /* Setting CMASK for writing */ 498 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 499 PCH_CMASK_ARB | PCH_CMASK_CTRL, 500 &priv->regs->ifregs[0].cmask); 501 502 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 503 } 504 505 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { 506 iowrite32(PCH_CMASK_RX_TX_GET, 507 &priv->regs->ifregs[1].cmask); 508 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 509 510 /* Resetting DIR bit for reception */ 511 iowrite32(0x0, &priv->regs->ifregs[1].id1); 512 iowrite32(0x0, &priv->regs->ifregs[1].id2); 513 pch_can_bit_set(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); 514 515 /* Setting EOB bit for transmitter */ 516 iowrite32(PCH_IF_MCONT_EOB, &priv->regs->ifregs[1].mcont); 517 518 pch_can_bit_set(&priv->regs->ifregs[1].mcont, 519 PCH_IF_MCONT_UMASK); 520 521 iowrite32(0, &priv->regs->ifregs[1].mask1); 522 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff); 523 524 /* Setting CMASK for writing */ 525 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 526 PCH_CMASK_ARB | PCH_CMASK_CTRL, 527 &priv->regs->ifregs[1].cmask); 528 529 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 530 } 531 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 532} 533 534static void pch_can_init(struct pch_can_priv *priv) 535{ 536 /* Stopping the Can device. */ 537 pch_can_set_run_mode(priv, PCH_CAN_STOP); 538 539 /* Clearing all the message object buffers. */ 540 pch_can_clear_buffers(priv); 541 542 /* Configuring the respective message object as either rx/tx object. */ 543 pch_can_config_rx_tx_buffers(priv); 544 545 /* Enabling the interrupts. */ 546 pch_can_set_int_enables(priv, PCH_CAN_ALL); 547} 548 549static void pch_can_release(struct pch_can_priv *priv) 550{ 551 /* Stooping the CAN device. */ 552 pch_can_set_run_mode(priv, PCH_CAN_STOP); 553 554 /* Disabling the interrupts. */ 555 pch_can_set_int_enables(priv, PCH_CAN_NONE); 556 557 /* Disabling all the receive object. */ 558 pch_can_set_rx_all(priv, 0); 559 560 /* Disabling all the transmit object. */ 561 pch_can_set_tx_all(priv, 0); 562} 563 564/* This function clears interrupt(s) from the CAN device. */ 565static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) 566{ 567 if (mask == PCH_STATUS_INT) { 568 ioread32(&priv->regs->stat); 569 return; 570 } 571 572 /* Clear interrupt for transmit object */ 573 if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) { 574 /* Setting CMASK for clearing the reception interrupts. */ 575 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, 576 &priv->regs->ifregs[0].cmask); 577 578 /* Clearing the Dir bit. */ 579 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); 580 581 /* Clearing NewDat & IntPnd */ 582 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 583 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND); 584 585 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, mask); 586 } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) { 587 /* Setting CMASK for clearing interrupts for 588 frame transmission. */ 589 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, 590 &priv->regs->ifregs[1].cmask); 591 592 /* Resetting the ID registers. */ 593 pch_can_bit_set(&priv->regs->ifregs[1].id2, 594 PCH_ID2_DIR | (0x7ff << 2)); 595 iowrite32(0x0, &priv->regs->ifregs[1].id1); 596 597 /* Claring NewDat, TxRqst & IntPnd */ 598 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 599 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | 600 PCH_IF_MCONT_TXRQXT); 601 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, mask); 602 } 603} 604 605static int pch_can_get_buffer_status(struct pch_can_priv *priv) 606{ 607 return (ioread32(&priv->regs->treq1) & 0xffff) | 608 ((ioread32(&priv->regs->treq2) & 0xffff) << 16); 609} 610 611static void pch_can_reset(struct pch_can_priv *priv) 612{ 613 /* write to sw reset register */ 614 iowrite32(1, &priv->regs->srst); 615 iowrite32(0, &priv->regs->srst); 616} 617 618static void pch_can_error(struct net_device *ndev, u32 status) 619{ 620 struct sk_buff *skb; 621 struct pch_can_priv *priv = netdev_priv(ndev); 622 struct can_frame *cf; 623 u32 errc; 624 struct net_device_stats *stats = &(priv->ndev->stats); 625 enum can_state state = priv->can.state; 626 627 skb = alloc_can_err_skb(ndev, &cf); 628 if (!skb) 629 return; 630 631 if (status & PCH_BUS_OFF) { 632 pch_can_set_tx_all(priv, 0); 633 pch_can_set_rx_all(priv, 0); 634 state = CAN_STATE_BUS_OFF; 635 cf->can_id |= CAN_ERR_BUSOFF; 636 can_bus_off(ndev); 637 pch_can_set_run_mode(priv, PCH_CAN_RUN); 638 dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__); 639 } 640 641 /* Warning interrupt. */ 642 if (status & PCH_EWARN) { 643 state = CAN_STATE_ERROR_WARNING; 644 priv->can.can_stats.error_warning++; 645 cf->can_id |= CAN_ERR_CRTL; 646 errc = ioread32(&priv->regs->errc); 647 if (((errc & PCH_REC) >> 8) > 96) 648 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; 649 if ((errc & PCH_TEC) > 96) 650 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; 651 dev_warn(&ndev->dev, 652 "%s -> Error Counter is more than 96.\n", __func__); 653 } 654 /* Error passive interrupt. */ 655 if (status & PCH_EPASSIV) { 656 priv->can.can_stats.error_passive++; 657 state = CAN_STATE_ERROR_PASSIVE; 658 cf->can_id |= CAN_ERR_CRTL; 659 errc = ioread32(&priv->regs->errc); 660 if (((errc & PCH_REC) >> 8) > 127) 661 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 662 if ((errc & PCH_TEC) > 127) 663 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 664 dev_err(&ndev->dev, 665 "%s -> CAN controller is ERROR PASSIVE .\n", __func__); 666 } 667 668 if (status & PCH_LEC_ALL) { 669 priv->can.can_stats.bus_error++; 670 stats->rx_errors++; 671 switch (status & PCH_LEC_ALL) { 672 case PCH_STUF_ERR: 673 cf->data[2] |= CAN_ERR_PROT_STUFF; 674 break; 675 case PCH_FORM_ERR: 676 cf->data[2] |= CAN_ERR_PROT_FORM; 677 break; 678 case PCH_ACK_ERR: 679 cf->data[2] |= CAN_ERR_PROT_LOC_ACK | 680 CAN_ERR_PROT_LOC_ACK_DEL; 681 break; 682 case PCH_BIT1_ERR: 683 case PCH_BIT0_ERR: 684 cf->data[2] |= CAN_ERR_PROT_BIT; 685 break; 686 case PCH_CRC_ERR: 687 cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ | 688 CAN_ERR_PROT_LOC_CRC_DEL; 689 break; 690 default: 691 iowrite32(status | PCH_LEC_ALL, &priv->regs->stat); 692 break; 693 } 694 695 } 696 697 priv->can.state = state; 698 netif_rx(skb); 699 700 stats->rx_packets++; 701 stats->rx_bytes += cf->can_dlc; 702} 703 704static irqreturn_t pch_can_interrupt(int irq, void *dev_id) 705{ 706 struct net_device *ndev = (struct net_device *)dev_id; 707 struct pch_can_priv *priv = netdev_priv(ndev); 708 709 pch_can_set_int_enables(priv, PCH_CAN_NONE); 710 711 napi_schedule(&priv->napi); 712 713 return IRQ_HANDLED; 714} 715 716static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat) 717{ 718 u32 reg; 719 canid_t id; 720 u32 ide; 721 u32 rtr; 722 int i, j, k; 723 int rcv_pkts = 0; 724 struct sk_buff *skb; 725 struct can_frame *cf; 726 struct pch_can_priv *priv = netdev_priv(ndev); 727 struct net_device_stats *stats = &(priv->ndev->stats); 728 729 /* Reading the messsage object from the Message RAM */ 730 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 731 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, int_stat); 732 733 /* Reading the MCONT register. */ 734 reg = ioread32(&priv->regs->ifregs[0].mcont); 735 reg &= 0xffff; 736 737 for (k = int_stat; !(reg & PCH_IF_MCONT_EOB); k++) { 738 /* If MsgLost bit set. */ 739 if (reg & PCH_IF_MCONT_MSGLOST) { 740 dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n"); 741 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 742 PCH_IF_MCONT_MSGLOST); 743 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, 744 &priv->regs->ifregs[0].cmask); 745 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 746 747 skb = alloc_can_err_skb(ndev, &cf); 748 if (!skb) 749 return -ENOMEM; 750 751 priv->can.can_stats.error_passive++; 752 priv->can.state = CAN_STATE_ERROR_PASSIVE; 753 cf->can_id |= CAN_ERR_CRTL; 754 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; 755 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 756 stats->rx_packets++; 757 stats->rx_bytes += cf->can_dlc; 758 759 netif_receive_skb(skb); 760 rcv_pkts++; 761 goto RX_NEXT; 762 } 763 if (!(reg & PCH_IF_MCONT_NEWDAT)) 764 goto RX_NEXT; 765 766 skb = alloc_can_skb(priv->ndev, &cf); 767 if (!skb) 768 return -ENOMEM; 769 770 /* Get Received data */ 771 ide = ((ioread32(&priv->regs->ifregs[0].id2)) & PCH_ID2_XTD) >> 772 14; 773 if (ide) { 774 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff); 775 id |= (((ioread32(&priv->regs->ifregs[0].id2)) & 776 0x1fff) << 16); 777 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; 778 } else { 779 id = (((ioread32(&priv->regs->ifregs[0].id2)) & 780 (CAN_SFF_MASK << 2)) >> 2); 781 cf->can_id = (id & CAN_SFF_MASK); 782 } 783 784 rtr = (ioread32(&priv->regs->ifregs[0].id2) & PCH_ID2_DIR); 785 if (rtr) { 786 cf->can_dlc = 0; 787 cf->can_id |= CAN_RTR_FLAG; 788 } else { 789 cf->can_dlc = 790 ((ioread32(&priv->regs->ifregs[0].mcont)) & 0x0f); 791 } 792 793 for (i = 0, j = 0; i < cf->can_dlc; j++) { 794 reg = ioread32(&priv->regs->ifregs[0].dataa1 + j*4); 795 cf->data[i++] = cpu_to_le32(reg & 0xff); 796 if (i == cf->can_dlc) 797 break; 798 cf->data[i++] = cpu_to_le32((reg >> 8) & 0xff); 799 } 800 801 netif_receive_skb(skb); 802 rcv_pkts++; 803 stats->rx_packets++; 804 stats->rx_bytes += cf->can_dlc; 805 806 if (k < PCH_FIFO_THRESH) { 807 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | 808 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask); 809 810 /* Clearing the Dir bit. */ 811 pch_can_bit_clear(&priv->regs->ifregs[0].id2, 812 PCH_ID2_DIR); 813 814 /* Clearing NewDat & IntPnd */ 815 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 816 PCH_IF_MCONT_INTPND); 817 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 818 } else if (k > PCH_FIFO_THRESH) { 819 pch_can_int_clr(priv, k); 820 } else if (k == PCH_FIFO_THRESH) { 821 int cnt; 822 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++) 823 pch_can_int_clr(priv, cnt+1); 824 } 825RX_NEXT: 826 /* Reading the messsage object from the Message RAM */ 827 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 828 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 829 reg = ioread32(&priv->regs->ifregs[0].mcont); 830 } 831 832 return rcv_pkts; 833} 834static int pch_can_rx_poll(struct napi_struct *napi, int quota) 835{ 836 struct net_device *ndev = napi->dev; 837 struct pch_can_priv *priv = netdev_priv(ndev); 838 struct net_device_stats *stats = &(priv->ndev->stats); 839 u32 dlc; 840 u32 int_stat; 841 int rcv_pkts = 0; 842 u32 reg_stat; 843 unsigned long flags; 844 845 int_stat = pch_can_int_pending(priv); 846 if (!int_stat) 847 return 0; 848 849INT_STAT: 850 if (int_stat == PCH_STATUS_INT) { 851 reg_stat = ioread32(&priv->regs->stat); 852 if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) { 853 if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) 854 pch_can_error(ndev, reg_stat); 855 } 856 857 if (reg_stat & PCH_TX_OK) { 858 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 859 iowrite32(PCH_CMASK_RX_TX_GET, 860 &priv->regs->ifregs[1].cmask); 861 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, 862 ioread32(&priv->regs->intr)); 863 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 864 pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK); 865 } 866 867 if (reg_stat & PCH_RX_OK) 868 pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK); 869 870 int_stat = pch_can_int_pending(priv); 871 if (int_stat == PCH_STATUS_INT) 872 goto INT_STAT; 873 } 874 875MSG_OBJ: 876 if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) { 877 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 878 rcv_pkts = pch_can_rx_normal(ndev, int_stat); 879 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 880 if (rcv_pkts < 0) 881 return 0; 882 } else if ((int_stat >= PCH_TX_OBJ_START) && 883 (int_stat <= PCH_TX_OBJ_END)) { 884 /* Handle transmission interrupt */ 885 can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1); 886 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 887 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND, 888 &priv->regs->ifregs[1].cmask); 889 dlc = ioread32(&priv->regs->ifregs[1].mcont) & 890 PCH_IF_MCONT_DLC; 891 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat); 892 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 893 if (dlc > 8) 894 dlc = 8; 895 stats->tx_bytes += dlc; 896 stats->tx_packets++; 897 } 898 899 int_stat = pch_can_int_pending(priv); 900 if (int_stat == PCH_STATUS_INT) 901 goto INT_STAT; 902 else if (int_stat >= 1 && int_stat <= 32) 903 goto MSG_OBJ; 904 905 napi_complete(napi); 906 pch_can_set_int_enables(priv, PCH_CAN_ALL); 907 908 return rcv_pkts; 909} 910 911static int pch_set_bittiming(struct net_device *ndev) 912{ 913 struct pch_can_priv *priv = netdev_priv(ndev); 914 const struct can_bittiming *bt = &priv->can.bittiming; 915 u32 canbit; 916 u32 bepe; 917 u32 brp; 918 919 /* Setting the CCE bit for accessing the Can Timing register. */ 920 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE); 921 922 brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1; 923 canbit = brp & PCH_MSK_BITT_BRP; 924 canbit |= (bt->sjw - 1) << PCH_BIT_SJW; 925 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1; 926 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2; 927 bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE; 928 iowrite32(canbit, &priv->regs->bitt); 929 iowrite32(bepe, &priv->regs->brpe); 930 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE); 931 932 return 0; 933} 934 935static void pch_can_start(struct net_device *ndev) 936{ 937 struct pch_can_priv *priv = netdev_priv(ndev); 938 939 if (priv->can.state != CAN_STATE_STOPPED) 940 pch_can_reset(priv); 941 942 pch_set_bittiming(ndev); 943 pch_can_set_optmode(priv); 944 945 pch_can_set_tx_all(priv, 1); 946 pch_can_set_rx_all(priv, 1); 947 948 /* Setting the CAN to run mode. */ 949 pch_can_set_run_mode(priv, PCH_CAN_RUN); 950 951 priv->can.state = CAN_STATE_ERROR_ACTIVE; 952 953 return; 954} 955 956static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 957{ 958 int ret = 0; 959 960 switch (mode) { 961 case CAN_MODE_START: 962 pch_can_start(ndev); 963 netif_wake_queue(ndev); 964 break; 965 default: 966 ret = -EOPNOTSUPP; 967 break; 968 } 969 970 return ret; 971} 972 973static int pch_can_open(struct net_device *ndev) 974{ 975 struct pch_can_priv *priv = netdev_priv(ndev); 976 int retval; 977 978 retval = pci_enable_msi(priv->dev); 979 if (retval) { 980 dev_info(&ndev->dev, "PCH CAN opened without MSI\n"); 981 priv->use_msi = 0; 982 } else { 983 dev_info(&ndev->dev, "PCH CAN opened with MSI\n"); 984 priv->use_msi = 1; 985 } 986 987 /* Regsitering the interrupt. */ 988 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED, 989 ndev->name, ndev); 990 if (retval) { 991 dev_err(&ndev->dev, "request_irq failed.\n"); 992 goto req_irq_err; 993 } 994 995 /* Open common can device */ 996 retval = open_candev(ndev); 997 if (retval) { 998 dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval); 999 goto err_open_candev; 1000 } 1001 1002 pch_can_init(priv); 1003 pch_can_start(ndev); 1004 napi_enable(&priv->napi); 1005 netif_start_queue(ndev); 1006 1007 return 0; 1008 1009err_open_candev: 1010 free_irq(priv->dev->irq, ndev); 1011req_irq_err: 1012 if (priv->use_msi) 1013 pci_disable_msi(priv->dev); 1014 1015 pch_can_release(priv); 1016 1017 return retval; 1018} 1019 1020static int pch_close(struct net_device *ndev) 1021{ 1022 struct pch_can_priv *priv = netdev_priv(ndev); 1023 1024 netif_stop_queue(ndev); 1025 napi_disable(&priv->napi); 1026 pch_can_release(priv); 1027 free_irq(priv->dev->irq, ndev); 1028 if (priv->use_msi) 1029 pci_disable_msi(priv->dev); 1030 close_candev(ndev); 1031 priv->can.state = CAN_STATE_STOPPED; 1032 return 0; 1033} 1034 1035static int pch_get_msg_obj_sts(struct net_device *ndev, u32 obj_id) 1036{ 1037 u32 buffer_status = 0; 1038 struct pch_can_priv *priv = netdev_priv(ndev); 1039 1040 /* Getting the message object status. */ 1041 buffer_status = (u32) pch_can_get_buffer_status(priv); 1042 1043 return buffer_status & obj_id; 1044} 1045 1046 1047static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) 1048{ 1049 int i, j; 1050 unsigned long flags; 1051 struct pch_can_priv *priv = netdev_priv(ndev); 1052 struct can_frame *cf = (struct can_frame *)skb->data; 1053 int tx_buffer_avail = 0; 1054 1055 if (can_dropped_invalid_skb(ndev, skb)) 1056 return NETDEV_TX_OK; 1057 1058 if (priv->tx_obj == PCH_TX_OBJ_END) { /* Point tail Obj */ 1059 while (pch_get_msg_obj_sts(ndev, (((1 << PCH_TX_OBJ_NUM)-1) << 1060 PCH_RX_OBJ_NUM))) 1061 udelay(500); 1062 1063 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj ID */ 1064 tx_buffer_avail = priv->tx_obj; /* Point Tail of Tx Obj */ 1065 } else { 1066 tx_buffer_avail = priv->tx_obj; 1067 } 1068 priv->tx_obj++; 1069 1070 /* Attaining the lock. */ 1071 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 1072 1073 /* Reading the Msg Obj from the Msg RAM to the Interface register. */ 1074 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); 1075 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); 1076 1077 /* Setting the CMASK register. */ 1078 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL); 1079 1080 /* If ID extended is set. */ 1081 pch_can_bit_clear(&priv->regs->ifregs[1].id1, 0xffff); 1082 pch_can_bit_clear(&priv->regs->ifregs[1].id2, 0x1fff | PCH_ID2_XTD); 1083 if (cf->can_id & CAN_EFF_FLAG) { 1084 pch_can_bit_set(&priv->regs->ifregs[1].id1, 1085 cf->can_id & 0xffff); 1086 pch_can_bit_set(&priv->regs->ifregs[1].id2, 1087 ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD); 1088 } else { 1089 pch_can_bit_set(&priv->regs->ifregs[1].id1, 0); 1090 pch_can_bit_set(&priv->regs->ifregs[1].id2, 1091 (cf->can_id & CAN_SFF_MASK) << 2); 1092 } 1093 1094 /* If remote frame has to be transmitted.. */ 1095 if (cf->can_id & CAN_RTR_FLAG) 1096 pch_can_bit_clear(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); 1097 1098 for (i = 0, j = 0; i < cf->can_dlc; j++) { 1099 iowrite32(le32_to_cpu(cf->data[i++]), 1100 (&priv->regs->ifregs[1].dataa1) + j*4); 1101 if (i == cf->can_dlc) 1102 break; 1103 iowrite32(le32_to_cpu(cf->data[i++] << 8), 1104 (&priv->regs->ifregs[1].dataa1) + j*4); 1105 } 1106 1107 can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_END - 1); 1108 1109 /* Updating the size of the data. */ 1110 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 0x0f); 1111 pch_can_bit_set(&priv->regs->ifregs[1].mcont, cf->can_dlc); 1112 1113 /* Clearing IntPend, NewDat & TxRqst */ 1114 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 1115 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | 1116 PCH_IF_MCONT_TXRQXT); 1117 1118 /* Setting NewDat, TxRqst bits */ 1119 pch_can_bit_set(&priv->regs->ifregs[1].mcont, 1120 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT); 1121 1122 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); 1123 1124 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 1125 1126 return NETDEV_TX_OK; 1127} 1128 1129static const struct net_device_ops pch_can_netdev_ops = { 1130 .ndo_open = pch_can_open, 1131 .ndo_stop = pch_close, 1132 .ndo_start_xmit = pch_xmit, 1133}; 1134 1135static void __devexit pch_can_remove(struct pci_dev *pdev) 1136{ 1137 struct net_device *ndev = pci_get_drvdata(pdev); 1138 struct pch_can_priv *priv = netdev_priv(ndev); 1139 1140 unregister_candev(priv->ndev); 1141 free_candev(priv->ndev); 1142 pci_iounmap(pdev, priv->regs); 1143 pci_release_regions(pdev); 1144 pci_disable_device(pdev); 1145 pci_set_drvdata(pdev, NULL); 1146 pch_can_reset(priv); 1147} 1148 1149#ifdef CONFIG_PM 1150static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state) 1151{ 1152 int i; /* Counter variable. */ 1153 int retval; /* Return value. */ 1154 u32 buf_stat; /* Variable for reading the transmit buffer status. */ 1155 u32 counter = 0xFFFFFF; 1156 1157 struct net_device *dev = pci_get_drvdata(pdev); 1158 struct pch_can_priv *priv = netdev_priv(dev); 1159 1160 /* Stop the CAN controller */ 1161 pch_can_set_run_mode(priv, PCH_CAN_STOP); 1162 1163 /* Indicate that we are aboutto/in suspend */ 1164 priv->can.state = CAN_STATE_SLEEPING; 1165 1166 /* Waiting for all transmission to complete. */ 1167 while (counter) { 1168 buf_stat = pch_can_get_buffer_status(priv); 1169 if (!buf_stat) 1170 break; 1171 counter--; 1172 udelay(1); 1173 } 1174 if (!counter) 1175 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__); 1176 1177 /* Save interrupt configuration and then disable them */ 1178 pch_can_get_int_enables(priv, &(priv->int_enables)); 1179 pch_can_set_int_enables(priv, PCH_CAN_DISABLE); 1180 1181 /* Save Tx buffer enable state */ 1182 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 1183 priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_TX_IFREG); 1184 1185 /* Disable all Transmit buffers */ 1186 pch_can_set_tx_all(priv, 0); 1187 1188 /* Save Rx buffer enable state */ 1189 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 1190 priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG); 1191 pch_can_get_rx_buffer_link(priv, i, &priv->rx_link[i]); 1192 } 1193 1194 /* Disable all Receive buffers */ 1195 pch_can_set_rx_all(priv, 0); 1196 retval = pci_save_state(pdev); 1197 if (retval) { 1198 dev_err(&pdev->dev, "pci_save_state failed.\n"); 1199 } else { 1200 pci_enable_wake(pdev, PCI_D3hot, 0); 1201 pci_disable_device(pdev); 1202 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1203 } 1204 1205 return retval; 1206} 1207 1208static int pch_can_resume(struct pci_dev *pdev) 1209{ 1210 int i; /* Counter variable. */ 1211 int retval; /* Return variable. */ 1212 struct net_device *dev = pci_get_drvdata(pdev); 1213 struct pch_can_priv *priv = netdev_priv(dev); 1214 1215 pci_set_power_state(pdev, PCI_D0); 1216 pci_restore_state(pdev); 1217 retval = pci_enable_device(pdev); 1218 if (retval) { 1219 dev_err(&pdev->dev, "pci_enable_device failed.\n"); 1220 return retval; 1221 } 1222 1223 pci_enable_wake(pdev, PCI_D3hot, 0); 1224 1225 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1226 1227 /* Disabling all interrupts. */ 1228 pch_can_set_int_enables(priv, PCH_CAN_DISABLE); 1229 1230 /* Setting the CAN device in Stop Mode. */ 1231 pch_can_set_run_mode(priv, PCH_CAN_STOP); 1232 1233 /* Configuring the transmit and receive buffers. */ 1234 pch_can_config_rx_tx_buffers(priv); 1235 1236 /* Restore the CAN state */ 1237 pch_set_bittiming(dev); 1238 1239 /* Listen/Active */ 1240 pch_can_set_optmode(priv); 1241 1242 /* Enabling the transmit buffer. */ 1243 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 1244 pch_can_set_rxtx(priv, i, priv->tx_enable[i], PCH_TX_IFREG); 1245 1246 /* Configuring the receive buffer and enabling them. */ 1247 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 1248 /* Restore buffer link */ 1249 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]); 1250 1251 /* Restore buffer enables */ 1252 pch_can_set_rxtx(priv, i, priv->rx_enable[i], PCH_RX_IFREG); 1253 } 1254 1255 /* Enable CAN Interrupts */ 1256 pch_can_set_int_custom(priv); 1257 1258 /* Restore Run Mode */ 1259 pch_can_set_run_mode(priv, PCH_CAN_RUN); 1260 1261 return retval; 1262} 1263#else 1264#define pch_can_suspend NULL 1265#define pch_can_resume NULL 1266#endif 1267 1268static int pch_can_get_berr_counter(const struct net_device *dev, 1269 struct can_berr_counter *bec) 1270{ 1271 struct pch_can_priv *priv = netdev_priv(dev); 1272 1273 bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC; 1274 bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8; 1275 1276 return 0; 1277} 1278 1279static int __devinit pch_can_probe(struct pci_dev *pdev, 1280 const struct pci_device_id *id) 1281{ 1282 struct net_device *ndev; 1283 struct pch_can_priv *priv; 1284 int rc; 1285 void __iomem *addr; 1286 1287 rc = pci_enable_device(pdev); 1288 if (rc) { 1289 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc); 1290 goto probe_exit_endev; 1291 } 1292 1293 rc = pci_request_regions(pdev, KBUILD_MODNAME); 1294 if (rc) { 1295 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc); 1296 goto probe_exit_pcireq; 1297 } 1298 1299 addr = pci_iomap(pdev, 1, 0); 1300 if (!addr) { 1301 rc = -EIO; 1302 dev_err(&pdev->dev, "Failed pci_iomap\n"); 1303 goto probe_exit_ipmap; 1304 } 1305 1306 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END); 1307 if (!ndev) { 1308 rc = -ENOMEM; 1309 dev_err(&pdev->dev, "Failed alloc_candev\n"); 1310 goto probe_exit_alloc_candev; 1311 } 1312 1313 priv = netdev_priv(ndev); 1314 priv->ndev = ndev; 1315 priv->regs = addr; 1316 priv->dev = pdev; 1317 priv->can.bittiming_const = &pch_can_bittiming_const; 1318 priv->can.do_set_mode = pch_can_do_set_mode; 1319 priv->can.do_get_berr_counter = pch_can_get_berr_counter; 1320 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | 1321 CAN_CTRLMODE_LOOPBACK; 1322 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */ 1323 1324 ndev->irq = pdev->irq; 1325 ndev->flags |= IFF_ECHO; 1326 1327 pci_set_drvdata(pdev, ndev); 1328 SET_NETDEV_DEV(ndev, &pdev->dev); 1329 ndev->netdev_ops = &pch_can_netdev_ops; 1330 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */ 1331 1332 netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_END); 1333 1334 rc = register_candev(ndev); 1335 if (rc) { 1336 dev_err(&pdev->dev, "Failed register_candev %d\n", rc); 1337 goto probe_exit_reg_candev; 1338 } 1339 1340 return 0; 1341 1342probe_exit_reg_candev: 1343 free_candev(ndev); 1344probe_exit_alloc_candev: 1345 pci_iounmap(pdev, addr); 1346probe_exit_ipmap: 1347 pci_release_regions(pdev); 1348probe_exit_pcireq: 1349 pci_disable_device(pdev); 1350probe_exit_endev: 1351 return rc; 1352} 1353 1354static struct pci_driver pch_can_pci_driver = { 1355 .name = "pch_can", 1356 .id_table = pch_pci_tbl, 1357 .probe = pch_can_probe, 1358 .remove = __devexit_p(pch_can_remove), 1359 .suspend = pch_can_suspend, 1360 .resume = pch_can_resume, 1361}; 1362 1363static int __init pch_can_pci_init(void) 1364{ 1365 return pci_register_driver(&pch_can_pci_driver); 1366} 1367module_init(pch_can_pci_init); 1368 1369static void __exit pch_can_pci_exit(void) 1370{ 1371 pci_unregister_driver(&pch_can_pci_driver); 1372} 1373module_exit(pch_can_pci_exit); 1374 1375MODULE_DESCRIPTION("Controller Area Network Driver"); 1376MODULE_LICENSE("GPL v2"); 1377MODULE_VERSION("0.94"); 1378