pch_can.c revision 2989042ca86b94bf4ffa9486921bb300ad44225f
1/* 2 * Copyright (C) 1999 - 2010 Intel Corporation. 3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19#include <linux/interrupt.h> 20#include <linux/delay.h> 21#include <linux/io.h> 22#include <linux/module.h> 23#include <linux/sched.h> 24#include <linux/pci.h> 25#include <linux/init.h> 26#include <linux/kernel.h> 27#include <linux/types.h> 28#include <linux/errno.h> 29#include <linux/netdevice.h> 30#include <linux/skbuff.h> 31#include <linux/can.h> 32#include <linux/can/dev.h> 33#include <linux/can/error.h> 34 35#define PCH_ENABLE 1 /* The enable flag */ 36#define PCH_DISABLE 0 /* The disable flag */ 37#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */ 38#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */ 39#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1)) 40#define PCH_CTRL_CCE BIT(6) 41#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */ 42#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */ 43#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */ 44 45#define PCH_CMASK_RX_TX_SET 0x00f3 46#define PCH_CMASK_RX_TX_GET 0x0073 47#define PCH_CMASK_ALL 0xff 48#define PCH_CMASK_NEWDAT BIT(2) 49#define PCH_CMASK_CLRINTPND BIT(3) 50#define PCH_CMASK_CTRL BIT(4) 51#define PCH_CMASK_ARB BIT(5) 52#define PCH_CMASK_MASK BIT(6) 53#define PCH_CMASK_RDWR BIT(7) 54#define PCH_IF_MCONT_NEWDAT BIT(15) 55#define PCH_IF_MCONT_MSGLOST BIT(14) 56#define PCH_IF_MCONT_INTPND BIT(13) 57#define PCH_IF_MCONT_UMASK BIT(12) 58#define PCH_IF_MCONT_TXIE BIT(11) 59#define PCH_IF_MCONT_RXIE BIT(10) 60#define PCH_IF_MCONT_RMTEN BIT(9) 61#define PCH_IF_MCONT_TXRQXT BIT(8) 62#define PCH_IF_MCONT_EOB BIT(7) 63#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 64#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15)) 65#define PCH_ID2_DIR BIT(13) 66#define PCH_ID2_XTD BIT(14) 67#define PCH_ID_MSGVAL BIT(15) 68#define PCH_IF_CREQ_BUSY BIT(15) 69 70#define PCH_STATUS_INT 0x8000 71#define PCH_REC 0x00007f00 72#define PCH_TEC 0x000000ff 73 74#define PCH_TX_OK BIT(3) 75#define PCH_RX_OK BIT(4) 76#define PCH_EPASSIV BIT(5) 77#define PCH_EWARN BIT(6) 78#define PCH_BUS_OFF BIT(7) 79 80/* bit position of certain controller bits. */ 81#define PCH_BIT_BRP 0 82#define PCH_BIT_SJW 6 83#define PCH_BIT_TSEG1 8 84#define PCH_BIT_TSEG2 12 85#define PCH_BIT_BRPE_BRPE 6 86#define PCH_MSK_BITT_BRP 0x3f 87#define PCH_MSK_BRPE_BRPE 0x3c0 88#define PCH_MSK_CTRL_IE_SIE_EIE 0x07 89#define PCH_COUNTER_LIMIT 10 90 91#define PCH_CAN_CLK 50000000 /* 50MHz */ 92 93/* Define the number of message object. 94 * PCH CAN communications are done via Message RAM. 95 * The Message RAM consists of 32 message objects. */ 96#define PCH_RX_OBJ_NUM 26 97#define PCH_TX_OBJ_NUM 6 98#define PCH_RX_OBJ_START 1 99#define PCH_RX_OBJ_END PCH_RX_OBJ_NUM 100#define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1) 101#define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM) 102 103#define PCH_FIFO_THRESH 16 104 105enum pch_ifreg { 106 PCH_RX_IFREG, 107 PCH_TX_IFREG, 108}; 109 110enum pch_can_err { 111 PCH_STUF_ERR = 1, 112 PCH_FORM_ERR, 113 PCH_ACK_ERR, 114 PCH_BIT1_ERR, 115 PCH_BIT0_ERR, 116 PCH_CRC_ERR, 117 PCH_LEC_ALL, 118}; 119 120enum pch_can_mode { 121 PCH_CAN_ENABLE, 122 PCH_CAN_DISABLE, 123 PCH_CAN_ALL, 124 PCH_CAN_NONE, 125 PCH_CAN_STOP, 126 PCH_CAN_RUN 127}; 128 129struct pch_can_if_regs { 130 u32 creq; 131 u32 cmask; 132 u32 mask1; 133 u32 mask2; 134 u32 id1; 135 u32 id2; 136 u32 mcont; 137 u32 dataa1; 138 u32 dataa2; 139 u32 datab1; 140 u32 datab2; 141 u32 rsv[13]; 142}; 143 144struct pch_can_regs { 145 u32 cont; 146 u32 stat; 147 u32 errc; 148 u32 bitt; 149 u32 intr; 150 u32 opt; 151 u32 brpe; 152 u32 reserve; 153 struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */ 154 u32 reserve1[8]; 155 u32 treq1; 156 u32 treq2; 157 u32 reserve2[6]; 158 u32 data1; 159 u32 data2; 160 u32 reserve3[6]; 161 u32 canipend1; 162 u32 canipend2; 163 u32 reserve4[6]; 164 u32 canmval1; 165 u32 canmval2; 166 u32 reserve5[37]; 167 u32 srst; 168}; 169 170struct pch_can_priv { 171 struct can_priv can; 172 unsigned int can_num; 173 struct pci_dev *dev; 174 int tx_enable[PCH_TX_OBJ_END]; 175 int rx_enable[PCH_TX_OBJ_END]; 176 int rx_link[PCH_TX_OBJ_END]; 177 unsigned int int_enables; 178 unsigned int int_stat; 179 struct net_device *ndev; 180 unsigned int msg_obj[PCH_TX_OBJ_END]; 181 struct pch_can_regs __iomem *regs; 182 struct napi_struct napi; 183 unsigned int tx_obj; /* Point next Tx Obj index */ 184 unsigned int use_msi; 185}; 186 187static struct can_bittiming_const pch_can_bittiming_const = { 188 .name = KBUILD_MODNAME, 189 .tseg1_min = 1, 190 .tseg1_max = 16, 191 .tseg2_min = 1, 192 .tseg2_max = 8, 193 .sjw_max = 4, 194 .brp_min = 1, 195 .brp_max = 1024, /* 6bit + extended 4bit */ 196 .brp_inc = 1, 197}; 198 199static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = { 200 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,}, 201 {0,} 202}; 203MODULE_DEVICE_TABLE(pci, pch_pci_tbl); 204 205static inline void pch_can_bit_set(void __iomem *addr, u32 mask) 206{ 207 iowrite32(ioread32(addr) | mask, addr); 208} 209 210static inline void pch_can_bit_clear(void __iomem *addr, u32 mask) 211{ 212 iowrite32(ioread32(addr) & ~mask, addr); 213} 214 215static void pch_can_set_run_mode(struct pch_can_priv *priv, 216 enum pch_can_mode mode) 217{ 218 switch (mode) { 219 case PCH_CAN_RUN: 220 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT); 221 break; 222 223 case PCH_CAN_STOP: 224 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT); 225 break; 226 227 default: 228 dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__); 229 break; 230 } 231} 232 233static void pch_can_set_optmode(struct pch_can_priv *priv) 234{ 235 u32 reg_val = ioread32(&priv->regs->opt); 236 237 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 238 reg_val |= PCH_OPT_SILENT; 239 240 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 241 reg_val |= PCH_OPT_LBACK; 242 243 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT); 244 iowrite32(reg_val, &priv->regs->opt); 245} 246 247static void pch_can_set_int_custom(struct pch_can_priv *priv) 248{ 249 /* Clearing the IE, SIE and EIE bits of Can control register. */ 250 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 251 252 /* Appropriately setting them. */ 253 pch_can_bit_set(&priv->regs->cont, 254 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1)); 255} 256 257/* This function retrieves interrupt enabled for the CAN device. */ 258static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables) 259{ 260 /* Obtaining the status of IE, SIE and EIE interrupt bits. */ 261 *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1); 262} 263 264static void pch_can_set_int_enables(struct pch_can_priv *priv, 265 enum pch_can_mode interrupt_no) 266{ 267 switch (interrupt_no) { 268 case PCH_CAN_ENABLE: 269 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE); 270 break; 271 272 case PCH_CAN_DISABLE: 273 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE); 274 break; 275 276 case PCH_CAN_ALL: 277 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 278 break; 279 280 case PCH_CAN_NONE: 281 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 282 break; 283 284 default: 285 dev_err(&priv->ndev->dev, "Invalid interrupt number.\n"); 286 break; 287 } 288} 289 290static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num) 291{ 292 u32 counter = PCH_COUNTER_LIMIT; 293 u32 ifx_creq; 294 295 iowrite32(num, creq_addr); 296 while (counter) { 297 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY; 298 if (!ifx_creq) 299 break; 300 counter--; 301 udelay(1); 302 } 303 if (!counter) 304 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__); 305} 306 307static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, 308 u32 set, enum pch_ifreg dir) 309{ 310 u32 ie; 311 312 if (dir) 313 ie = PCH_IF_MCONT_TXIE; 314 else 315 ie = PCH_IF_MCONT_RXIE; 316 317 /* Reading the receive buffer data from RAM to Interface1 registers */ 318 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); 319 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 320 321 /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */ 322 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL, 323 &priv->regs->ifregs[dir].cmask); 324 325 if (set == PCH_ENABLE) { 326 /* Setting the MsgVal and RxIE bits */ 327 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie); 328 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); 329 330 } else if (set == PCH_DISABLE) { 331 /* Resetting the MsgVal and RxIE bits */ 332 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie); 333 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); 334 } 335 336 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 337} 338 339static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set) 340{ 341 int i; 342 343 /* Traversing to obtain the object configured as receivers. */ 344 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) 345 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG); 346} 347 348static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set) 349{ 350 int i; 351 352 /* Traversing to obtain the object configured as transmit object. */ 353 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 354 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG); 355} 356 357static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, 358 enum pch_ifreg dir) 359{ 360 u32 ie, enable; 361 362 if (dir) 363 ie = PCH_IF_MCONT_RXIE; 364 else 365 ie = PCH_IF_MCONT_TXIE; 366 367 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); 368 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 369 370 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) && 371 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) { 372 enable = 1; 373 } else { 374 enable = 0; 375 } 376 return enable; 377} 378 379static int pch_can_int_pending(struct pch_can_priv *priv) 380{ 381 return ioread32(&priv->regs->intr) & 0xffff; 382} 383 384static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, 385 u32 buffer_num, u32 set) 386{ 387 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 388 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 389 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, 390 &priv->regs->ifregs[0].cmask); 391 if (set == PCH_ENABLE) 392 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 393 PCH_IF_MCONT_EOB); 394 else 395 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB); 396 397 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 398} 399 400static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv, 401 u32 buffer_num, u32 *link) 402{ 403 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 404 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 405 406 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB) 407 *link = PCH_DISABLE; 408 else 409 *link = PCH_ENABLE; 410} 411 412static void pch_can_clear_buffers(struct pch_can_priv *priv) 413{ 414 int i; 415 416 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 417 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask); 418 iowrite32(0xffff, &priv->regs->ifregs[0].mask1); 419 iowrite32(0xffff, &priv->regs->ifregs[0].mask2); 420 iowrite32(0x0, &priv->regs->ifregs[0].id1); 421 iowrite32(0x0, &priv->regs->ifregs[0].id2); 422 iowrite32(0x0, &priv->regs->ifregs[0].mcont); 423 iowrite32(0x0, &priv->regs->ifregs[0].dataa1); 424 iowrite32(0x0, &priv->regs->ifregs[0].dataa2); 425 iowrite32(0x0, &priv->regs->ifregs[0].datab1); 426 iowrite32(0x0, &priv->regs->ifregs[0].datab2); 427 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 428 PCH_CMASK_ARB | PCH_CMASK_CTRL, 429 &priv->regs->ifregs[0].cmask); 430 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 431 } 432 433 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { 434 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[1].cmask); 435 iowrite32(0xffff, &priv->regs->ifregs[1].mask1); 436 iowrite32(0xffff, &priv->regs->ifregs[1].mask2); 437 iowrite32(0x0, &priv->regs->ifregs[1].id1); 438 iowrite32(0x0, &priv->regs->ifregs[1].id2); 439 iowrite32(0x0, &priv->regs->ifregs[1].mcont); 440 iowrite32(0x0, &priv->regs->ifregs[1].dataa1); 441 iowrite32(0x0, &priv->regs->ifregs[1].dataa2); 442 iowrite32(0x0, &priv->regs->ifregs[1].datab1); 443 iowrite32(0x0, &priv->regs->ifregs[1].datab2); 444 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 445 PCH_CMASK_ARB | PCH_CMASK_CTRL, 446 &priv->regs->ifregs[1].cmask); 447 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 448 } 449} 450 451static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) 452{ 453 int i; 454 455 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 456 iowrite32(PCH_CMASK_RX_TX_GET, 457 &priv->regs->ifregs[0].cmask); 458 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 459 460 iowrite32(0x0, &priv->regs->ifregs[0].id1); 461 iowrite32(0x0, &priv->regs->ifregs[0].id2); 462 463 pch_can_bit_set(&priv->regs->ifregs[0].mcont, 464 PCH_IF_MCONT_UMASK); 465 466 /* Set FIFO mode set to 0 except last Rx Obj*/ 467 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 468 PCH_IF_MCONT_EOB); 469 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */ 470 if (i == PCH_RX_OBJ_END) 471 pch_can_bit_set(&priv->regs->ifregs[0].mcont, 472 PCH_IF_MCONT_EOB); 473 474 iowrite32(0, &priv->regs->ifregs[0].mask1); 475 pch_can_bit_clear(&priv->regs->ifregs[0].mask2, 476 0x1fff | PCH_MASK2_MDIR_MXTD); 477 478 /* Setting CMASK for writing */ 479 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 480 PCH_CMASK_ARB | PCH_CMASK_CTRL, 481 &priv->regs->ifregs[0].cmask); 482 483 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 484 } 485 486 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { 487 iowrite32(PCH_CMASK_RX_TX_GET, 488 &priv->regs->ifregs[1].cmask); 489 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 490 491 /* Resetting DIR bit for reception */ 492 iowrite32(0x0, &priv->regs->ifregs[1].id1); 493 iowrite32(0x0, &priv->regs->ifregs[1].id2); 494 pch_can_bit_set(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); 495 496 /* Setting EOB bit for transmitter */ 497 iowrite32(PCH_IF_MCONT_EOB, &priv->regs->ifregs[1].mcont); 498 499 pch_can_bit_set(&priv->regs->ifregs[1].mcont, 500 PCH_IF_MCONT_UMASK); 501 502 iowrite32(0, &priv->regs->ifregs[1].mask1); 503 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff); 504 505 /* Setting CMASK for writing */ 506 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 507 PCH_CMASK_ARB | PCH_CMASK_CTRL, 508 &priv->regs->ifregs[1].cmask); 509 510 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 511 } 512} 513 514static void pch_can_init(struct pch_can_priv *priv) 515{ 516 /* Stopping the Can device. */ 517 pch_can_set_run_mode(priv, PCH_CAN_STOP); 518 519 /* Clearing all the message object buffers. */ 520 pch_can_clear_buffers(priv); 521 522 /* Configuring the respective message object as either rx/tx object. */ 523 pch_can_config_rx_tx_buffers(priv); 524 525 /* Enabling the interrupts. */ 526 pch_can_set_int_enables(priv, PCH_CAN_ALL); 527} 528 529static void pch_can_release(struct pch_can_priv *priv) 530{ 531 /* Stooping the CAN device. */ 532 pch_can_set_run_mode(priv, PCH_CAN_STOP); 533 534 /* Disabling the interrupts. */ 535 pch_can_set_int_enables(priv, PCH_CAN_NONE); 536 537 /* Disabling all the receive object. */ 538 pch_can_set_rx_all(priv, 0); 539 540 /* Disabling all the transmit object. */ 541 pch_can_set_tx_all(priv, 0); 542} 543 544/* This function clears interrupt(s) from the CAN device. */ 545static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) 546{ 547 if (mask == PCH_STATUS_INT) { 548 ioread32(&priv->regs->stat); 549 return; 550 } 551 552 /* Clear interrupt for transmit object */ 553 if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) { 554 /* Setting CMASK for clearing the reception interrupts. */ 555 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, 556 &priv->regs->ifregs[0].cmask); 557 558 /* Clearing the Dir bit. */ 559 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); 560 561 /* Clearing NewDat & IntPnd */ 562 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 563 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND); 564 565 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, mask); 566 } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) { 567 /* Setting CMASK for clearing interrupts for 568 frame transmission. */ 569 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, 570 &priv->regs->ifregs[1].cmask); 571 572 /* Resetting the ID registers. */ 573 pch_can_bit_set(&priv->regs->ifregs[1].id2, 574 PCH_ID2_DIR | (0x7ff << 2)); 575 iowrite32(0x0, &priv->regs->ifregs[1].id1); 576 577 /* Claring NewDat, TxRqst & IntPnd */ 578 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 579 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | 580 PCH_IF_MCONT_TXRQXT); 581 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, mask); 582 } 583} 584 585static int pch_can_get_buffer_status(struct pch_can_priv *priv) 586{ 587 return (ioread32(&priv->regs->treq1) & 0xffff) | 588 ((ioread32(&priv->regs->treq2) & 0xffff) << 16); 589} 590 591static void pch_can_reset(struct pch_can_priv *priv) 592{ 593 /* write to sw reset register */ 594 iowrite32(1, &priv->regs->srst); 595 iowrite32(0, &priv->regs->srst); 596} 597 598static void pch_can_error(struct net_device *ndev, u32 status) 599{ 600 struct sk_buff *skb; 601 struct pch_can_priv *priv = netdev_priv(ndev); 602 struct can_frame *cf; 603 u32 errc, lec; 604 struct net_device_stats *stats = &(priv->ndev->stats); 605 enum can_state state = priv->can.state; 606 607 skb = alloc_can_err_skb(ndev, &cf); 608 if (!skb) 609 return; 610 611 if (status & PCH_BUS_OFF) { 612 pch_can_set_tx_all(priv, 0); 613 pch_can_set_rx_all(priv, 0); 614 state = CAN_STATE_BUS_OFF; 615 cf->can_id |= CAN_ERR_BUSOFF; 616 can_bus_off(ndev); 617 pch_can_set_run_mode(priv, PCH_CAN_RUN); 618 dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__); 619 } 620 621 /* Warning interrupt. */ 622 if (status & PCH_EWARN) { 623 state = CAN_STATE_ERROR_WARNING; 624 priv->can.can_stats.error_warning++; 625 cf->can_id |= CAN_ERR_CRTL; 626 errc = ioread32(&priv->regs->errc); 627 if (((errc & PCH_REC) >> 8) > 96) 628 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; 629 if ((errc & PCH_TEC) > 96) 630 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; 631 dev_warn(&ndev->dev, 632 "%s -> Error Counter is more than 96.\n", __func__); 633 } 634 /* Error passive interrupt. */ 635 if (status & PCH_EPASSIV) { 636 priv->can.can_stats.error_passive++; 637 state = CAN_STATE_ERROR_PASSIVE; 638 cf->can_id |= CAN_ERR_CRTL; 639 errc = ioread32(&priv->regs->errc); 640 if (((errc & PCH_REC) >> 8) > 127) 641 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 642 if ((errc & PCH_TEC) > 127) 643 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 644 dev_err(&ndev->dev, 645 "%s -> CAN controller is ERROR PASSIVE .\n", __func__); 646 } 647 648 lec = status & PCH_LEC_ALL; 649 switch (lec) { 650 case PCH_STUF_ERR: 651 cf->data[2] |= CAN_ERR_PROT_STUFF; 652 priv->can.can_stats.bus_error++; 653 stats->rx_errors++; 654 break; 655 case PCH_FORM_ERR: 656 cf->data[2] |= CAN_ERR_PROT_FORM; 657 priv->can.can_stats.bus_error++; 658 stats->rx_errors++; 659 break; 660 case PCH_ACK_ERR: 661 cf->can_id |= CAN_ERR_ACK; 662 priv->can.can_stats.bus_error++; 663 stats->rx_errors++; 664 break; 665 case PCH_BIT1_ERR: 666 case PCH_BIT0_ERR: 667 cf->data[2] |= CAN_ERR_PROT_BIT; 668 priv->can.can_stats.bus_error++; 669 stats->rx_errors++; 670 break; 671 case PCH_CRC_ERR: 672 cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ | 673 CAN_ERR_PROT_LOC_CRC_DEL; 674 priv->can.can_stats.bus_error++; 675 stats->rx_errors++; 676 break; 677 case PCH_LEC_ALL: /* Written by CPU. No error status */ 678 break; 679 } 680 681 priv->can.state = state; 682 netif_rx(skb); 683 684 stats->rx_packets++; 685 stats->rx_bytes += cf->can_dlc; 686} 687 688static irqreturn_t pch_can_interrupt(int irq, void *dev_id) 689{ 690 struct net_device *ndev = (struct net_device *)dev_id; 691 struct pch_can_priv *priv = netdev_priv(ndev); 692 693 pch_can_set_int_enables(priv, PCH_CAN_NONE); 694 695 napi_schedule(&priv->napi); 696 697 return IRQ_HANDLED; 698} 699 700static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat) 701{ 702 u32 reg; 703 canid_t id; 704 u32 ide; 705 u32 rtr; 706 int i, j, k; 707 int rcv_pkts = 0; 708 struct sk_buff *skb; 709 struct can_frame *cf; 710 struct pch_can_priv *priv = netdev_priv(ndev); 711 struct net_device_stats *stats = &(priv->ndev->stats); 712 713 /* Reading the messsage object from the Message RAM */ 714 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 715 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, int_stat); 716 717 /* Reading the MCONT register. */ 718 reg = ioread32(&priv->regs->ifregs[0].mcont); 719 reg &= 0xffff; 720 721 for (k = int_stat; !(reg & PCH_IF_MCONT_EOB); k++) { 722 /* If MsgLost bit set. */ 723 if (reg & PCH_IF_MCONT_MSGLOST) { 724 dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n"); 725 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 726 PCH_IF_MCONT_MSGLOST); 727 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, 728 &priv->regs->ifregs[0].cmask); 729 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 730 731 skb = alloc_can_err_skb(ndev, &cf); 732 if (!skb) 733 return -ENOMEM; 734 735 priv->can.can_stats.error_passive++; 736 priv->can.state = CAN_STATE_ERROR_PASSIVE; 737 cf->can_id |= CAN_ERR_CRTL; 738 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; 739 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 740 stats->rx_packets++; 741 stats->rx_bytes += cf->can_dlc; 742 743 netif_receive_skb(skb); 744 rcv_pkts++; 745 goto RX_NEXT; 746 } 747 if (!(reg & PCH_IF_MCONT_NEWDAT)) 748 goto RX_NEXT; 749 750 skb = alloc_can_skb(priv->ndev, &cf); 751 if (!skb) 752 return -ENOMEM; 753 754 /* Get Received data */ 755 ide = ((ioread32(&priv->regs->ifregs[0].id2)) & PCH_ID2_XTD) >> 756 14; 757 if (ide) { 758 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff); 759 id |= (((ioread32(&priv->regs->ifregs[0].id2)) & 760 0x1fff) << 16); 761 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; 762 } else { 763 id = (((ioread32(&priv->regs->ifregs[0].id2)) & 764 (CAN_SFF_MASK << 2)) >> 2); 765 cf->can_id = (id & CAN_SFF_MASK); 766 } 767 768 rtr = (ioread32(&priv->regs->ifregs[0].id2) & PCH_ID2_DIR); 769 if (rtr) { 770 cf->can_dlc = 0; 771 cf->can_id |= CAN_RTR_FLAG; 772 } else { 773 cf->can_dlc = 774 ((ioread32(&priv->regs->ifregs[0].mcont)) & 0x0f); 775 } 776 777 for (i = 0, j = 0; i < cf->can_dlc; j++) { 778 reg = ioread32(&priv->regs->ifregs[0].dataa1 + j*4); 779 cf->data[i++] = cpu_to_le32(reg & 0xff); 780 if (i == cf->can_dlc) 781 break; 782 cf->data[i++] = cpu_to_le32((reg >> 8) & 0xff); 783 } 784 785 netif_receive_skb(skb); 786 rcv_pkts++; 787 stats->rx_packets++; 788 stats->rx_bytes += cf->can_dlc; 789 790 if (k < PCH_FIFO_THRESH) { 791 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | 792 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask); 793 794 /* Clearing the Dir bit. */ 795 pch_can_bit_clear(&priv->regs->ifregs[0].id2, 796 PCH_ID2_DIR); 797 798 /* Clearing NewDat & IntPnd */ 799 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 800 PCH_IF_MCONT_INTPND); 801 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 802 } else if (k > PCH_FIFO_THRESH) { 803 pch_can_int_clr(priv, k); 804 } else if (k == PCH_FIFO_THRESH) { 805 int cnt; 806 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++) 807 pch_can_int_clr(priv, cnt+1); 808 } 809RX_NEXT: 810 /* Reading the messsage object from the Message RAM */ 811 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 812 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 813 reg = ioread32(&priv->regs->ifregs[0].mcont); 814 } 815 816 return rcv_pkts; 817} 818static int pch_can_rx_poll(struct napi_struct *napi, int quota) 819{ 820 struct net_device *ndev = napi->dev; 821 struct pch_can_priv *priv = netdev_priv(ndev); 822 struct net_device_stats *stats = &(priv->ndev->stats); 823 u32 dlc; 824 u32 int_stat; 825 int rcv_pkts = 0; 826 u32 reg_stat; 827 828 int_stat = pch_can_int_pending(priv); 829 if (!int_stat) 830 return 0; 831 832INT_STAT: 833 if (int_stat == PCH_STATUS_INT) { 834 reg_stat = ioread32(&priv->regs->stat); 835 if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) { 836 if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) 837 pch_can_error(ndev, reg_stat); 838 } 839 840 if (reg_stat & PCH_TX_OK) { 841 iowrite32(PCH_CMASK_RX_TX_GET, 842 &priv->regs->ifregs[1].cmask); 843 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, 844 ioread32(&priv->regs->intr)); 845 pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK); 846 } 847 848 if (reg_stat & PCH_RX_OK) 849 pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK); 850 851 int_stat = pch_can_int_pending(priv); 852 if (int_stat == PCH_STATUS_INT) 853 goto INT_STAT; 854 } 855 856MSG_OBJ: 857 if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) { 858 rcv_pkts = pch_can_rx_normal(ndev, int_stat); 859 if (rcv_pkts < 0) 860 return 0; 861 } else if ((int_stat >= PCH_TX_OBJ_START) && 862 (int_stat <= PCH_TX_OBJ_END)) { 863 /* Handle transmission interrupt */ 864 can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1); 865 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND, 866 &priv->regs->ifregs[1].cmask); 867 dlc = ioread32(&priv->regs->ifregs[1].mcont) & 868 PCH_IF_MCONT_DLC; 869 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat); 870 if (dlc > 8) 871 dlc = 8; 872 stats->tx_bytes += dlc; 873 stats->tx_packets++; 874 } 875 876 int_stat = pch_can_int_pending(priv); 877 if (int_stat == PCH_STATUS_INT) 878 goto INT_STAT; 879 else if (int_stat >= 1 && int_stat <= 32) 880 goto MSG_OBJ; 881 882 napi_complete(napi); 883 pch_can_set_int_enables(priv, PCH_CAN_ALL); 884 885 return rcv_pkts; 886} 887 888static int pch_set_bittiming(struct net_device *ndev) 889{ 890 struct pch_can_priv *priv = netdev_priv(ndev); 891 const struct can_bittiming *bt = &priv->can.bittiming; 892 u32 canbit; 893 u32 bepe; 894 u32 brp; 895 896 /* Setting the CCE bit for accessing the Can Timing register. */ 897 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE); 898 899 brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1; 900 canbit = brp & PCH_MSK_BITT_BRP; 901 canbit |= (bt->sjw - 1) << PCH_BIT_SJW; 902 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1; 903 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2; 904 bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE; 905 iowrite32(canbit, &priv->regs->bitt); 906 iowrite32(bepe, &priv->regs->brpe); 907 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE); 908 909 return 0; 910} 911 912static void pch_can_start(struct net_device *ndev) 913{ 914 struct pch_can_priv *priv = netdev_priv(ndev); 915 916 if (priv->can.state != CAN_STATE_STOPPED) 917 pch_can_reset(priv); 918 919 pch_set_bittiming(ndev); 920 pch_can_set_optmode(priv); 921 922 pch_can_set_tx_all(priv, 1); 923 pch_can_set_rx_all(priv, 1); 924 925 /* Setting the CAN to run mode. */ 926 pch_can_set_run_mode(priv, PCH_CAN_RUN); 927 928 priv->can.state = CAN_STATE_ERROR_ACTIVE; 929 930 return; 931} 932 933static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 934{ 935 int ret = 0; 936 937 switch (mode) { 938 case CAN_MODE_START: 939 pch_can_start(ndev); 940 netif_wake_queue(ndev); 941 break; 942 default: 943 ret = -EOPNOTSUPP; 944 break; 945 } 946 947 return ret; 948} 949 950static int pch_can_open(struct net_device *ndev) 951{ 952 struct pch_can_priv *priv = netdev_priv(ndev); 953 int retval; 954 955 retval = pci_enable_msi(priv->dev); 956 if (retval) { 957 dev_info(&ndev->dev, "PCH CAN opened without MSI\n"); 958 priv->use_msi = 0; 959 } else { 960 dev_info(&ndev->dev, "PCH CAN opened with MSI\n"); 961 priv->use_msi = 1; 962 } 963 964 /* Regsitering the interrupt. */ 965 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED, 966 ndev->name, ndev); 967 if (retval) { 968 dev_err(&ndev->dev, "request_irq failed.\n"); 969 goto req_irq_err; 970 } 971 972 /* Open common can device */ 973 retval = open_candev(ndev); 974 if (retval) { 975 dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval); 976 goto err_open_candev; 977 } 978 979 pch_can_init(priv); 980 pch_can_start(ndev); 981 napi_enable(&priv->napi); 982 netif_start_queue(ndev); 983 984 return 0; 985 986err_open_candev: 987 free_irq(priv->dev->irq, ndev); 988req_irq_err: 989 if (priv->use_msi) 990 pci_disable_msi(priv->dev); 991 992 pch_can_release(priv); 993 994 return retval; 995} 996 997static int pch_close(struct net_device *ndev) 998{ 999 struct pch_can_priv *priv = netdev_priv(ndev); 1000 1001 netif_stop_queue(ndev); 1002 napi_disable(&priv->napi); 1003 pch_can_release(priv); 1004 free_irq(priv->dev->irq, ndev); 1005 if (priv->use_msi) 1006 pci_disable_msi(priv->dev); 1007 close_candev(ndev); 1008 priv->can.state = CAN_STATE_STOPPED; 1009 return 0; 1010} 1011 1012static int pch_get_msg_obj_sts(struct net_device *ndev, u32 obj_id) 1013{ 1014 u32 buffer_status = 0; 1015 struct pch_can_priv *priv = netdev_priv(ndev); 1016 1017 /* Getting the message object status. */ 1018 buffer_status = (u32) pch_can_get_buffer_status(priv); 1019 1020 return buffer_status & obj_id; 1021} 1022 1023 1024static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) 1025{ 1026 int i, j; 1027 struct pch_can_priv *priv = netdev_priv(ndev); 1028 struct can_frame *cf = (struct can_frame *)skb->data; 1029 int tx_buffer_avail = 0; 1030 1031 if (can_dropped_invalid_skb(ndev, skb)) 1032 return NETDEV_TX_OK; 1033 1034 if (priv->tx_obj == PCH_TX_OBJ_END) { /* Point tail Obj */ 1035 while (pch_get_msg_obj_sts(ndev, (((1 << PCH_TX_OBJ_NUM)-1) << 1036 PCH_RX_OBJ_NUM))) 1037 udelay(500); 1038 1039 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj ID */ 1040 tx_buffer_avail = priv->tx_obj; /* Point Tail of Tx Obj */ 1041 } else { 1042 tx_buffer_avail = priv->tx_obj; 1043 } 1044 priv->tx_obj++; 1045 1046 /* Reading the Msg Obj from the Msg RAM to the Interface register. */ 1047 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); 1048 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); 1049 1050 /* Setting the CMASK register. */ 1051 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL); 1052 1053 /* If ID extended is set. */ 1054 pch_can_bit_clear(&priv->regs->ifregs[1].id1, 0xffff); 1055 pch_can_bit_clear(&priv->regs->ifregs[1].id2, 0x1fff | PCH_ID2_XTD); 1056 if (cf->can_id & CAN_EFF_FLAG) { 1057 pch_can_bit_set(&priv->regs->ifregs[1].id1, 1058 cf->can_id & 0xffff); 1059 pch_can_bit_set(&priv->regs->ifregs[1].id2, 1060 ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD); 1061 } else { 1062 pch_can_bit_set(&priv->regs->ifregs[1].id1, 0); 1063 pch_can_bit_set(&priv->regs->ifregs[1].id2, 1064 (cf->can_id & CAN_SFF_MASK) << 2); 1065 } 1066 1067 /* If remote frame has to be transmitted.. */ 1068 if (cf->can_id & CAN_RTR_FLAG) 1069 pch_can_bit_clear(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); 1070 1071 for (i = 0, j = 0; i < cf->can_dlc; j++) { 1072 iowrite32(le32_to_cpu(cf->data[i++]), 1073 (&priv->regs->ifregs[1].dataa1) + j*4); 1074 if (i == cf->can_dlc) 1075 break; 1076 iowrite32(le32_to_cpu(cf->data[i++] << 8), 1077 (&priv->regs->ifregs[1].dataa1) + j*4); 1078 } 1079 1080 can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_END - 1); 1081 1082 /* Updating the size of the data. */ 1083 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 0x0f); 1084 pch_can_bit_set(&priv->regs->ifregs[1].mcont, cf->can_dlc); 1085 1086 /* Clearing IntPend, NewDat & TxRqst */ 1087 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 1088 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | 1089 PCH_IF_MCONT_TXRQXT); 1090 1091 /* Setting NewDat, TxRqst bits */ 1092 pch_can_bit_set(&priv->regs->ifregs[1].mcont, 1093 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT); 1094 1095 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); 1096 1097 return NETDEV_TX_OK; 1098} 1099 1100static const struct net_device_ops pch_can_netdev_ops = { 1101 .ndo_open = pch_can_open, 1102 .ndo_stop = pch_close, 1103 .ndo_start_xmit = pch_xmit, 1104}; 1105 1106static void __devexit pch_can_remove(struct pci_dev *pdev) 1107{ 1108 struct net_device *ndev = pci_get_drvdata(pdev); 1109 struct pch_can_priv *priv = netdev_priv(ndev); 1110 1111 unregister_candev(priv->ndev); 1112 free_candev(priv->ndev); 1113 pci_iounmap(pdev, priv->regs); 1114 pci_release_regions(pdev); 1115 pci_disable_device(pdev); 1116 pci_set_drvdata(pdev, NULL); 1117 pch_can_reset(priv); 1118} 1119 1120#ifdef CONFIG_PM 1121static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state) 1122{ 1123 int i; /* Counter variable. */ 1124 int retval; /* Return value. */ 1125 u32 buf_stat; /* Variable for reading the transmit buffer status. */ 1126 u32 counter = 0xFFFFFF; 1127 1128 struct net_device *dev = pci_get_drvdata(pdev); 1129 struct pch_can_priv *priv = netdev_priv(dev); 1130 1131 /* Stop the CAN controller */ 1132 pch_can_set_run_mode(priv, PCH_CAN_STOP); 1133 1134 /* Indicate that we are aboutto/in suspend */ 1135 priv->can.state = CAN_STATE_SLEEPING; 1136 1137 /* Waiting for all transmission to complete. */ 1138 while (counter) { 1139 buf_stat = pch_can_get_buffer_status(priv); 1140 if (!buf_stat) 1141 break; 1142 counter--; 1143 udelay(1); 1144 } 1145 if (!counter) 1146 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__); 1147 1148 /* Save interrupt configuration and then disable them */ 1149 pch_can_get_int_enables(priv, &(priv->int_enables)); 1150 pch_can_set_int_enables(priv, PCH_CAN_DISABLE); 1151 1152 /* Save Tx buffer enable state */ 1153 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 1154 priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_TX_IFREG); 1155 1156 /* Disable all Transmit buffers */ 1157 pch_can_set_tx_all(priv, 0); 1158 1159 /* Save Rx buffer enable state */ 1160 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 1161 priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG); 1162 pch_can_get_rx_buffer_link(priv, i, &priv->rx_link[i]); 1163 } 1164 1165 /* Disable all Receive buffers */ 1166 pch_can_set_rx_all(priv, 0); 1167 retval = pci_save_state(pdev); 1168 if (retval) { 1169 dev_err(&pdev->dev, "pci_save_state failed.\n"); 1170 } else { 1171 pci_enable_wake(pdev, PCI_D3hot, 0); 1172 pci_disable_device(pdev); 1173 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1174 } 1175 1176 return retval; 1177} 1178 1179static int pch_can_resume(struct pci_dev *pdev) 1180{ 1181 int i; /* Counter variable. */ 1182 int retval; /* Return variable. */ 1183 struct net_device *dev = pci_get_drvdata(pdev); 1184 struct pch_can_priv *priv = netdev_priv(dev); 1185 1186 pci_set_power_state(pdev, PCI_D0); 1187 pci_restore_state(pdev); 1188 retval = pci_enable_device(pdev); 1189 if (retval) { 1190 dev_err(&pdev->dev, "pci_enable_device failed.\n"); 1191 return retval; 1192 } 1193 1194 pci_enable_wake(pdev, PCI_D3hot, 0); 1195 1196 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1197 1198 /* Disabling all interrupts. */ 1199 pch_can_set_int_enables(priv, PCH_CAN_DISABLE); 1200 1201 /* Setting the CAN device in Stop Mode. */ 1202 pch_can_set_run_mode(priv, PCH_CAN_STOP); 1203 1204 /* Configuring the transmit and receive buffers. */ 1205 pch_can_config_rx_tx_buffers(priv); 1206 1207 /* Restore the CAN state */ 1208 pch_set_bittiming(dev); 1209 1210 /* Listen/Active */ 1211 pch_can_set_optmode(priv); 1212 1213 /* Enabling the transmit buffer. */ 1214 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 1215 pch_can_set_rxtx(priv, i, priv->tx_enable[i], PCH_TX_IFREG); 1216 1217 /* Configuring the receive buffer and enabling them. */ 1218 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 1219 /* Restore buffer link */ 1220 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]); 1221 1222 /* Restore buffer enables */ 1223 pch_can_set_rxtx(priv, i, priv->rx_enable[i], PCH_RX_IFREG); 1224 } 1225 1226 /* Enable CAN Interrupts */ 1227 pch_can_set_int_custom(priv); 1228 1229 /* Restore Run Mode */ 1230 pch_can_set_run_mode(priv, PCH_CAN_RUN); 1231 1232 return retval; 1233} 1234#else 1235#define pch_can_suspend NULL 1236#define pch_can_resume NULL 1237#endif 1238 1239static int pch_can_get_berr_counter(const struct net_device *dev, 1240 struct can_berr_counter *bec) 1241{ 1242 struct pch_can_priv *priv = netdev_priv(dev); 1243 1244 bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC; 1245 bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8; 1246 1247 return 0; 1248} 1249 1250static int __devinit pch_can_probe(struct pci_dev *pdev, 1251 const struct pci_device_id *id) 1252{ 1253 struct net_device *ndev; 1254 struct pch_can_priv *priv; 1255 int rc; 1256 void __iomem *addr; 1257 1258 rc = pci_enable_device(pdev); 1259 if (rc) { 1260 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc); 1261 goto probe_exit_endev; 1262 } 1263 1264 rc = pci_request_regions(pdev, KBUILD_MODNAME); 1265 if (rc) { 1266 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc); 1267 goto probe_exit_pcireq; 1268 } 1269 1270 addr = pci_iomap(pdev, 1, 0); 1271 if (!addr) { 1272 rc = -EIO; 1273 dev_err(&pdev->dev, "Failed pci_iomap\n"); 1274 goto probe_exit_ipmap; 1275 } 1276 1277 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END); 1278 if (!ndev) { 1279 rc = -ENOMEM; 1280 dev_err(&pdev->dev, "Failed alloc_candev\n"); 1281 goto probe_exit_alloc_candev; 1282 } 1283 1284 priv = netdev_priv(ndev); 1285 priv->ndev = ndev; 1286 priv->regs = addr; 1287 priv->dev = pdev; 1288 priv->can.bittiming_const = &pch_can_bittiming_const; 1289 priv->can.do_set_mode = pch_can_do_set_mode; 1290 priv->can.do_get_berr_counter = pch_can_get_berr_counter; 1291 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | 1292 CAN_CTRLMODE_LOOPBACK; 1293 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */ 1294 1295 ndev->irq = pdev->irq; 1296 ndev->flags |= IFF_ECHO; 1297 1298 pci_set_drvdata(pdev, ndev); 1299 SET_NETDEV_DEV(ndev, &pdev->dev); 1300 ndev->netdev_ops = &pch_can_netdev_ops; 1301 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */ 1302 1303 netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_END); 1304 1305 rc = register_candev(ndev); 1306 if (rc) { 1307 dev_err(&pdev->dev, "Failed register_candev %d\n", rc); 1308 goto probe_exit_reg_candev; 1309 } 1310 1311 return 0; 1312 1313probe_exit_reg_candev: 1314 free_candev(ndev); 1315probe_exit_alloc_candev: 1316 pci_iounmap(pdev, addr); 1317probe_exit_ipmap: 1318 pci_release_regions(pdev); 1319probe_exit_pcireq: 1320 pci_disable_device(pdev); 1321probe_exit_endev: 1322 return rc; 1323} 1324 1325static struct pci_driver pch_can_pci_driver = { 1326 .name = "pch_can", 1327 .id_table = pch_pci_tbl, 1328 .probe = pch_can_probe, 1329 .remove = __devexit_p(pch_can_remove), 1330 .suspend = pch_can_suspend, 1331 .resume = pch_can_resume, 1332}; 1333 1334static int __init pch_can_pci_init(void) 1335{ 1336 return pci_register_driver(&pch_can_pci_driver); 1337} 1338module_init(pch_can_pci_init); 1339 1340static void __exit pch_can_pci_exit(void) 1341{ 1342 pci_unregister_driver(&pch_can_pci_driver); 1343} 1344module_exit(pch_can_pci_exit); 1345 1346MODULE_DESCRIPTION("Controller Area Network Driver"); 1347MODULE_LICENSE("GPL v2"); 1348MODULE_VERSION("0.94"); 1349