pch_can.c revision 8ac9702b9d5d81b819fc7d6b4f6abad22af01f3c
1/* 2 * Copyright (C) 1999 - 2010 Intel Corporation. 3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19#include <linux/interrupt.h> 20#include <linux/delay.h> 21#include <linux/io.h> 22#include <linux/module.h> 23#include <linux/sched.h> 24#include <linux/pci.h> 25#include <linux/init.h> 26#include <linux/kernel.h> 27#include <linux/types.h> 28#include <linux/errno.h> 29#include <linux/netdevice.h> 30#include <linux/skbuff.h> 31#include <linux/can.h> 32#include <linux/can/dev.h> 33#include <linux/can/error.h> 34 35#define PCH_ENABLE 1 /* The enable flag */ 36#define PCH_DISABLE 0 /* The disable flag */ 37#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */ 38#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */ 39#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1)) 40#define PCH_CTRL_CCE BIT(6) 41#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */ 42#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */ 43#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */ 44 45#define PCH_CMASK_RX_TX_SET 0x00f3 46#define PCH_CMASK_RX_TX_GET 0x0073 47#define PCH_CMASK_ALL 0xff 48#define PCH_CMASK_NEWDAT BIT(2) 49#define PCH_CMASK_CLRINTPND BIT(3) 50#define PCH_CMASK_CTRL BIT(4) 51#define PCH_CMASK_ARB BIT(5) 52#define PCH_CMASK_MASK BIT(6) 53#define PCH_CMASK_RDWR BIT(7) 54#define PCH_IF_MCONT_NEWDAT BIT(15) 55#define PCH_IF_MCONT_MSGLOST BIT(14) 56#define PCH_IF_MCONT_INTPND BIT(13) 57#define PCH_IF_MCONT_UMASK BIT(12) 58#define PCH_IF_MCONT_TXIE BIT(11) 59#define PCH_IF_MCONT_RXIE BIT(10) 60#define PCH_IF_MCONT_RMTEN BIT(9) 61#define PCH_IF_MCONT_TXRQXT BIT(8) 62#define PCH_IF_MCONT_EOB BIT(7) 63#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 64#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15)) 65#define PCH_ID2_DIR BIT(13) 66#define PCH_ID2_XTD BIT(14) 67#define PCH_ID_MSGVAL BIT(15) 68#define PCH_IF_CREQ_BUSY BIT(15) 69 70#define PCH_STATUS_INT 0x8000 71#define PCH_REC 0x00007f00 72#define PCH_TEC 0x000000ff 73 74#define PCH_TX_OK BIT(3) 75#define PCH_RX_OK BIT(4) 76#define PCH_EPASSIV BIT(5) 77#define PCH_EWARN BIT(6) 78#define PCH_BUS_OFF BIT(7) 79 80/* bit position of certain controller bits. */ 81#define PCH_BIT_BRP 0 82#define PCH_BIT_SJW 6 83#define PCH_BIT_TSEG1 8 84#define PCH_BIT_TSEG2 12 85#define PCH_BIT_BRPE_BRPE 6 86#define PCH_MSK_BITT_BRP 0x3f 87#define PCH_MSK_BRPE_BRPE 0x3c0 88#define PCH_MSK_CTRL_IE_SIE_EIE 0x07 89#define PCH_COUNTER_LIMIT 10 90 91#define PCH_CAN_CLK 50000000 /* 50MHz */ 92 93/* Define the number of message object. 94 * PCH CAN communications are done via Message RAM. 95 * The Message RAM consists of 32 message objects. */ 96#define PCH_RX_OBJ_NUM 26 97#define PCH_TX_OBJ_NUM 6 98#define PCH_RX_OBJ_START 1 99#define PCH_RX_OBJ_END PCH_RX_OBJ_NUM 100#define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1) 101#define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM) 102 103#define PCH_FIFO_THRESH 16 104 105/* TxRqst2 show status of MsgObjNo.17~32 */ 106#define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\ 107 (PCH_RX_OBJ_END - 16)) 108 109enum pch_ifreg { 110 PCH_RX_IFREG, 111 PCH_TX_IFREG, 112}; 113 114enum pch_can_err { 115 PCH_STUF_ERR = 1, 116 PCH_FORM_ERR, 117 PCH_ACK_ERR, 118 PCH_BIT1_ERR, 119 PCH_BIT0_ERR, 120 PCH_CRC_ERR, 121 PCH_LEC_ALL, 122}; 123 124enum pch_can_mode { 125 PCH_CAN_ENABLE, 126 PCH_CAN_DISABLE, 127 PCH_CAN_ALL, 128 PCH_CAN_NONE, 129 PCH_CAN_STOP, 130 PCH_CAN_RUN 131}; 132 133struct pch_can_if_regs { 134 u32 creq; 135 u32 cmask; 136 u32 mask1; 137 u32 mask2; 138 u32 id1; 139 u32 id2; 140 u32 mcont; 141 u32 data[4]; 142 u32 rsv[13]; 143}; 144 145struct pch_can_regs { 146 u32 cont; 147 u32 stat; 148 u32 errc; 149 u32 bitt; 150 u32 intr; 151 u32 opt; 152 u32 brpe; 153 u32 reserve; 154 struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */ 155 u32 reserve1[8]; 156 u32 treq1; 157 u32 treq2; 158 u32 reserve2[6]; 159 u32 data1; 160 u32 data2; 161 u32 reserve3[6]; 162 u32 canipend1; 163 u32 canipend2; 164 u32 reserve4[6]; 165 u32 canmval1; 166 u32 canmval2; 167 u32 reserve5[37]; 168 u32 srst; 169}; 170 171struct pch_can_priv { 172 struct can_priv can; 173 unsigned int can_num; 174 struct pci_dev *dev; 175 int tx_enable[PCH_TX_OBJ_END]; 176 int rx_enable[PCH_TX_OBJ_END]; 177 int rx_link[PCH_TX_OBJ_END]; 178 unsigned int int_enables; 179 unsigned int int_stat; 180 struct net_device *ndev; 181 unsigned int msg_obj[PCH_TX_OBJ_END]; 182 struct pch_can_regs __iomem *regs; 183 struct napi_struct napi; 184 unsigned int tx_obj; /* Point next Tx Obj index */ 185 unsigned int use_msi; 186}; 187 188static struct can_bittiming_const pch_can_bittiming_const = { 189 .name = KBUILD_MODNAME, 190 .tseg1_min = 1, 191 .tseg1_max = 16, 192 .tseg2_min = 1, 193 .tseg2_max = 8, 194 .sjw_max = 4, 195 .brp_min = 1, 196 .brp_max = 1024, /* 6bit + extended 4bit */ 197 .brp_inc = 1, 198}; 199 200static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = { 201 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,}, 202 {0,} 203}; 204MODULE_DEVICE_TABLE(pci, pch_pci_tbl); 205 206static inline void pch_can_bit_set(void __iomem *addr, u32 mask) 207{ 208 iowrite32(ioread32(addr) | mask, addr); 209} 210 211static inline void pch_can_bit_clear(void __iomem *addr, u32 mask) 212{ 213 iowrite32(ioread32(addr) & ~mask, addr); 214} 215 216static void pch_can_set_run_mode(struct pch_can_priv *priv, 217 enum pch_can_mode mode) 218{ 219 switch (mode) { 220 case PCH_CAN_RUN: 221 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT); 222 break; 223 224 case PCH_CAN_STOP: 225 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT); 226 break; 227 228 default: 229 dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__); 230 break; 231 } 232} 233 234static void pch_can_set_optmode(struct pch_can_priv *priv) 235{ 236 u32 reg_val = ioread32(&priv->regs->opt); 237 238 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 239 reg_val |= PCH_OPT_SILENT; 240 241 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 242 reg_val |= PCH_OPT_LBACK; 243 244 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT); 245 iowrite32(reg_val, &priv->regs->opt); 246} 247 248static void pch_can_set_int_custom(struct pch_can_priv *priv) 249{ 250 /* Clearing the IE, SIE and EIE bits of Can control register. */ 251 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 252 253 /* Appropriately setting them. */ 254 pch_can_bit_set(&priv->regs->cont, 255 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1)); 256} 257 258/* This function retrieves interrupt enabled for the CAN device. */ 259static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables) 260{ 261 /* Obtaining the status of IE, SIE and EIE interrupt bits. */ 262 *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1); 263} 264 265static void pch_can_set_int_enables(struct pch_can_priv *priv, 266 enum pch_can_mode interrupt_no) 267{ 268 switch (interrupt_no) { 269 case PCH_CAN_ENABLE: 270 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE); 271 break; 272 273 case PCH_CAN_DISABLE: 274 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE); 275 break; 276 277 case PCH_CAN_ALL: 278 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 279 break; 280 281 case PCH_CAN_NONE: 282 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 283 break; 284 285 default: 286 dev_err(&priv->ndev->dev, "Invalid interrupt number.\n"); 287 break; 288 } 289} 290 291static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num) 292{ 293 u32 counter = PCH_COUNTER_LIMIT; 294 u32 ifx_creq; 295 296 iowrite32(num, creq_addr); 297 while (counter) { 298 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY; 299 if (!ifx_creq) 300 break; 301 counter--; 302 udelay(1); 303 } 304 if (!counter) 305 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__); 306} 307 308static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, 309 u32 set, enum pch_ifreg dir) 310{ 311 u32 ie; 312 313 if (dir) 314 ie = PCH_IF_MCONT_TXIE; 315 else 316 ie = PCH_IF_MCONT_RXIE; 317 318 /* Reading the receive buffer data from RAM to Interface1 registers */ 319 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); 320 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 321 322 /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */ 323 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL, 324 &priv->regs->ifregs[dir].cmask); 325 326 if (set == PCH_ENABLE) { 327 /* Setting the MsgVal and RxIE bits */ 328 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie); 329 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); 330 331 } else if (set == PCH_DISABLE) { 332 /* Resetting the MsgVal and RxIE bits */ 333 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie); 334 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); 335 } 336 337 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 338} 339 340static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set) 341{ 342 int i; 343 344 /* Traversing to obtain the object configured as receivers. */ 345 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) 346 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG); 347} 348 349static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set) 350{ 351 int i; 352 353 /* Traversing to obtain the object configured as transmit object. */ 354 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 355 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG); 356} 357 358static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, 359 enum pch_ifreg dir) 360{ 361 u32 ie, enable; 362 363 if (dir) 364 ie = PCH_IF_MCONT_RXIE; 365 else 366 ie = PCH_IF_MCONT_TXIE; 367 368 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); 369 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 370 371 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) && 372 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) { 373 enable = 1; 374 } else { 375 enable = 0; 376 } 377 return enable; 378} 379 380static int pch_can_int_pending(struct pch_can_priv *priv) 381{ 382 return ioread32(&priv->regs->intr) & 0xffff; 383} 384 385static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, 386 u32 buffer_num, u32 set) 387{ 388 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 389 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 390 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, 391 &priv->regs->ifregs[0].cmask); 392 if (set == PCH_ENABLE) 393 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 394 PCH_IF_MCONT_EOB); 395 else 396 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB); 397 398 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 399} 400 401static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv, 402 u32 buffer_num, u32 *link) 403{ 404 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 405 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 406 407 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB) 408 *link = PCH_DISABLE; 409 else 410 *link = PCH_ENABLE; 411} 412 413static void pch_can_clear_buffers(struct pch_can_priv *priv) 414{ 415 int i; 416 417 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 418 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask); 419 iowrite32(0xffff, &priv->regs->ifregs[0].mask1); 420 iowrite32(0xffff, &priv->regs->ifregs[0].mask2); 421 iowrite32(0x0, &priv->regs->ifregs[0].id1); 422 iowrite32(0x0, &priv->regs->ifregs[0].id2); 423 iowrite32(0x0, &priv->regs->ifregs[0].mcont); 424 iowrite32(0x0, &priv->regs->ifregs[0].data[0]); 425 iowrite32(0x0, &priv->regs->ifregs[0].data[1]); 426 iowrite32(0x0, &priv->regs->ifregs[0].data[2]); 427 iowrite32(0x0, &priv->regs->ifregs[0].data[3]); 428 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 429 PCH_CMASK_ARB | PCH_CMASK_CTRL, 430 &priv->regs->ifregs[0].cmask); 431 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 432 } 433 434 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { 435 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[1].cmask); 436 iowrite32(0xffff, &priv->regs->ifregs[1].mask1); 437 iowrite32(0xffff, &priv->regs->ifregs[1].mask2); 438 iowrite32(0x0, &priv->regs->ifregs[1].id1); 439 iowrite32(0x0, &priv->regs->ifregs[1].id2); 440 iowrite32(0x0, &priv->regs->ifregs[1].mcont); 441 iowrite32(0x0, &priv->regs->ifregs[1].data[0]); 442 iowrite32(0x0, &priv->regs->ifregs[1].data[1]); 443 iowrite32(0x0, &priv->regs->ifregs[1].data[2]); 444 iowrite32(0x0, &priv->regs->ifregs[1].data[3]); 445 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 446 PCH_CMASK_ARB | PCH_CMASK_CTRL, 447 &priv->regs->ifregs[1].cmask); 448 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 449 } 450} 451 452static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) 453{ 454 int i; 455 456 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 457 iowrite32(PCH_CMASK_RX_TX_GET, 458 &priv->regs->ifregs[0].cmask); 459 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 460 461 iowrite32(0x0, &priv->regs->ifregs[0].id1); 462 iowrite32(0x0, &priv->regs->ifregs[0].id2); 463 464 pch_can_bit_set(&priv->regs->ifregs[0].mcont, 465 PCH_IF_MCONT_UMASK); 466 467 /* Set FIFO mode set to 0 except last Rx Obj*/ 468 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 469 PCH_IF_MCONT_EOB); 470 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */ 471 if (i == PCH_RX_OBJ_END) 472 pch_can_bit_set(&priv->regs->ifregs[0].mcont, 473 PCH_IF_MCONT_EOB); 474 475 iowrite32(0, &priv->regs->ifregs[0].mask1); 476 pch_can_bit_clear(&priv->regs->ifregs[0].mask2, 477 0x1fff | PCH_MASK2_MDIR_MXTD); 478 479 /* Setting CMASK for writing */ 480 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 481 PCH_CMASK_ARB | PCH_CMASK_CTRL, 482 &priv->regs->ifregs[0].cmask); 483 484 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 485 } 486 487 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { 488 iowrite32(PCH_CMASK_RX_TX_GET, 489 &priv->regs->ifregs[1].cmask); 490 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 491 492 /* Resetting DIR bit for reception */ 493 iowrite32(0x0, &priv->regs->ifregs[1].id1); 494 iowrite32(0x0, &priv->regs->ifregs[1].id2); 495 pch_can_bit_set(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); 496 497 /* Setting EOB bit for transmitter */ 498 iowrite32(PCH_IF_MCONT_EOB, &priv->regs->ifregs[1].mcont); 499 500 pch_can_bit_set(&priv->regs->ifregs[1].mcont, 501 PCH_IF_MCONT_UMASK); 502 503 iowrite32(0, &priv->regs->ifregs[1].mask1); 504 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff); 505 506 /* Setting CMASK for writing */ 507 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 508 PCH_CMASK_ARB | PCH_CMASK_CTRL, 509 &priv->regs->ifregs[1].cmask); 510 511 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 512 } 513} 514 515static void pch_can_init(struct pch_can_priv *priv) 516{ 517 /* Stopping the Can device. */ 518 pch_can_set_run_mode(priv, PCH_CAN_STOP); 519 520 /* Clearing all the message object buffers. */ 521 pch_can_clear_buffers(priv); 522 523 /* Configuring the respective message object as either rx/tx object. */ 524 pch_can_config_rx_tx_buffers(priv); 525 526 /* Enabling the interrupts. */ 527 pch_can_set_int_enables(priv, PCH_CAN_ALL); 528} 529 530static void pch_can_release(struct pch_can_priv *priv) 531{ 532 /* Stooping the CAN device. */ 533 pch_can_set_run_mode(priv, PCH_CAN_STOP); 534 535 /* Disabling the interrupts. */ 536 pch_can_set_int_enables(priv, PCH_CAN_NONE); 537 538 /* Disabling all the receive object. */ 539 pch_can_set_rx_all(priv, 0); 540 541 /* Disabling all the transmit object. */ 542 pch_can_set_tx_all(priv, 0); 543} 544 545/* This function clears interrupt(s) from the CAN device. */ 546static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) 547{ 548 if (mask == PCH_STATUS_INT) { 549 ioread32(&priv->regs->stat); 550 return; 551 } 552 553 /* Clear interrupt for transmit object */ 554 if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) { 555 /* Setting CMASK for clearing the reception interrupts. */ 556 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, 557 &priv->regs->ifregs[0].cmask); 558 559 /* Clearing the Dir bit. */ 560 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); 561 562 /* Clearing NewDat & IntPnd */ 563 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 564 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND); 565 566 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, mask); 567 } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) { 568 /* Setting CMASK for clearing interrupts for 569 frame transmission. */ 570 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, 571 &priv->regs->ifregs[1].cmask); 572 573 /* Resetting the ID registers. */ 574 pch_can_bit_set(&priv->regs->ifregs[1].id2, 575 PCH_ID2_DIR | (0x7ff << 2)); 576 iowrite32(0x0, &priv->regs->ifregs[1].id1); 577 578 /* Claring NewDat, TxRqst & IntPnd */ 579 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 580 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | 581 PCH_IF_MCONT_TXRQXT); 582 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, mask); 583 } 584} 585 586static int pch_can_get_buffer_status(struct pch_can_priv *priv) 587{ 588 return (ioread32(&priv->regs->treq1) & 0xffff) | 589 ((ioread32(&priv->regs->treq2) & 0xffff) << 16); 590} 591 592static void pch_can_reset(struct pch_can_priv *priv) 593{ 594 /* write to sw reset register */ 595 iowrite32(1, &priv->regs->srst); 596 iowrite32(0, &priv->regs->srst); 597} 598 599static void pch_can_error(struct net_device *ndev, u32 status) 600{ 601 struct sk_buff *skb; 602 struct pch_can_priv *priv = netdev_priv(ndev); 603 struct can_frame *cf; 604 u32 errc, lec; 605 struct net_device_stats *stats = &(priv->ndev->stats); 606 enum can_state state = priv->can.state; 607 608 skb = alloc_can_err_skb(ndev, &cf); 609 if (!skb) 610 return; 611 612 if (status & PCH_BUS_OFF) { 613 pch_can_set_tx_all(priv, 0); 614 pch_can_set_rx_all(priv, 0); 615 state = CAN_STATE_BUS_OFF; 616 cf->can_id |= CAN_ERR_BUSOFF; 617 can_bus_off(ndev); 618 pch_can_set_run_mode(priv, PCH_CAN_RUN); 619 dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__); 620 } 621 622 /* Warning interrupt. */ 623 if (status & PCH_EWARN) { 624 state = CAN_STATE_ERROR_WARNING; 625 priv->can.can_stats.error_warning++; 626 cf->can_id |= CAN_ERR_CRTL; 627 errc = ioread32(&priv->regs->errc); 628 if (((errc & PCH_REC) >> 8) > 96) 629 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; 630 if ((errc & PCH_TEC) > 96) 631 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; 632 dev_warn(&ndev->dev, 633 "%s -> Error Counter is more than 96.\n", __func__); 634 } 635 /* Error passive interrupt. */ 636 if (status & PCH_EPASSIV) { 637 priv->can.can_stats.error_passive++; 638 state = CAN_STATE_ERROR_PASSIVE; 639 cf->can_id |= CAN_ERR_CRTL; 640 errc = ioread32(&priv->regs->errc); 641 if (((errc & PCH_REC) >> 8) > 127) 642 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 643 if ((errc & PCH_TEC) > 127) 644 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 645 dev_err(&ndev->dev, 646 "%s -> CAN controller is ERROR PASSIVE .\n", __func__); 647 } 648 649 lec = status & PCH_LEC_ALL; 650 switch (lec) { 651 case PCH_STUF_ERR: 652 cf->data[2] |= CAN_ERR_PROT_STUFF; 653 priv->can.can_stats.bus_error++; 654 stats->rx_errors++; 655 break; 656 case PCH_FORM_ERR: 657 cf->data[2] |= CAN_ERR_PROT_FORM; 658 priv->can.can_stats.bus_error++; 659 stats->rx_errors++; 660 break; 661 case PCH_ACK_ERR: 662 cf->can_id |= CAN_ERR_ACK; 663 priv->can.can_stats.bus_error++; 664 stats->rx_errors++; 665 break; 666 case PCH_BIT1_ERR: 667 case PCH_BIT0_ERR: 668 cf->data[2] |= CAN_ERR_PROT_BIT; 669 priv->can.can_stats.bus_error++; 670 stats->rx_errors++; 671 break; 672 case PCH_CRC_ERR: 673 cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ | 674 CAN_ERR_PROT_LOC_CRC_DEL; 675 priv->can.can_stats.bus_error++; 676 stats->rx_errors++; 677 break; 678 case PCH_LEC_ALL: /* Written by CPU. No error status */ 679 break; 680 } 681 682 priv->can.state = state; 683 netif_rx(skb); 684 685 stats->rx_packets++; 686 stats->rx_bytes += cf->can_dlc; 687} 688 689static irqreturn_t pch_can_interrupt(int irq, void *dev_id) 690{ 691 struct net_device *ndev = (struct net_device *)dev_id; 692 struct pch_can_priv *priv = netdev_priv(ndev); 693 694 pch_can_set_int_enables(priv, PCH_CAN_NONE); 695 696 napi_schedule(&priv->napi); 697 698 return IRQ_HANDLED; 699} 700 701static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat) 702{ 703 u32 reg; 704 canid_t id; 705 u32 ide; 706 u32 rtr; 707 int i, k; 708 int rcv_pkts = 0; 709 struct sk_buff *skb; 710 struct can_frame *cf; 711 struct pch_can_priv *priv = netdev_priv(ndev); 712 struct net_device_stats *stats = &(priv->ndev->stats); 713 u16 data_reg; 714 715 /* Reading the messsage object from the Message RAM */ 716 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 717 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, int_stat); 718 719 /* Reading the MCONT register. */ 720 reg = ioread32(&priv->regs->ifregs[0].mcont); 721 reg &= 0xffff; 722 723 for (k = int_stat; !(reg & PCH_IF_MCONT_EOB); k++) { 724 /* If MsgLost bit set. */ 725 if (reg & PCH_IF_MCONT_MSGLOST) { 726 dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n"); 727 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 728 PCH_IF_MCONT_MSGLOST); 729 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, 730 &priv->regs->ifregs[0].cmask); 731 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 732 733 skb = alloc_can_err_skb(ndev, &cf); 734 if (!skb) 735 return -ENOMEM; 736 737 priv->can.can_stats.error_passive++; 738 priv->can.state = CAN_STATE_ERROR_PASSIVE; 739 cf->can_id |= CAN_ERR_CRTL; 740 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; 741 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 742 stats->rx_packets++; 743 stats->rx_bytes += cf->can_dlc; 744 745 netif_receive_skb(skb); 746 rcv_pkts++; 747 goto RX_NEXT; 748 } 749 if (!(reg & PCH_IF_MCONT_NEWDAT)) 750 goto RX_NEXT; 751 752 skb = alloc_can_skb(priv->ndev, &cf); 753 if (!skb) 754 return -ENOMEM; 755 756 /* Get Received data */ 757 ide = ((ioread32(&priv->regs->ifregs[0].id2)) & PCH_ID2_XTD) >> 758 14; 759 if (ide) { 760 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff); 761 id |= (((ioread32(&priv->regs->ifregs[0].id2)) & 762 0x1fff) << 16); 763 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; 764 } else { 765 id = (((ioread32(&priv->regs->ifregs[0].id2)) & 766 (CAN_SFF_MASK << 2)) >> 2); 767 cf->can_id = (id & CAN_SFF_MASK); 768 } 769 770 rtr = (ioread32(&priv->regs->ifregs[0].id2) & PCH_ID2_DIR); 771 if (rtr) { 772 cf->can_dlc = 0; 773 cf->can_id |= CAN_RTR_FLAG; 774 } else { 775 cf->can_dlc = 776 ((ioread32(&priv->regs->ifregs[0].mcont)) & 0x0f); 777 } 778 779 for (i = 0; i < cf->can_dlc; i += 2) { 780 data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]); 781 cf->data[i] = data_reg; 782 cf->data[i + 1] = data_reg >> 8; 783 } 784 785 netif_receive_skb(skb); 786 rcv_pkts++; 787 stats->rx_packets++; 788 stats->rx_bytes += cf->can_dlc; 789 790 if (k < PCH_FIFO_THRESH) { 791 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | 792 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask); 793 794 /* Clearing the Dir bit. */ 795 pch_can_bit_clear(&priv->regs->ifregs[0].id2, 796 PCH_ID2_DIR); 797 798 /* Clearing NewDat & IntPnd */ 799 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 800 PCH_IF_MCONT_INTPND); 801 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 802 } else if (k > PCH_FIFO_THRESH) { 803 pch_can_int_clr(priv, k); 804 } else if (k == PCH_FIFO_THRESH) { 805 int cnt; 806 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++) 807 pch_can_int_clr(priv, cnt+1); 808 } 809RX_NEXT: 810 /* Reading the messsage object from the Message RAM */ 811 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 812 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 813 reg = ioread32(&priv->regs->ifregs[0].mcont); 814 } 815 816 return rcv_pkts; 817} 818 819static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat) 820{ 821 struct pch_can_priv *priv = netdev_priv(ndev); 822 struct net_device_stats *stats = &(priv->ndev->stats); 823 u32 dlc; 824 825 can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1); 826 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND, 827 &priv->regs->ifregs[1].cmask); 828 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat); 829 dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) & 830 PCH_IF_MCONT_DLC); 831 stats->tx_bytes += dlc; 832 stats->tx_packets++; 833 if (int_stat == PCH_TX_OBJ_END) 834 netif_wake_queue(ndev); 835} 836 837static int pch_can_rx_poll(struct napi_struct *napi, int quota) 838{ 839 struct net_device *ndev = napi->dev; 840 struct pch_can_priv *priv = netdev_priv(ndev); 841 u32 int_stat; 842 int rcv_pkts = 0; 843 u32 reg_stat; 844 845 int_stat = pch_can_int_pending(priv); 846 if (!int_stat) 847 goto end; 848 849 if ((int_stat == PCH_STATUS_INT) && (quota > 0)) { 850 reg_stat = ioread32(&priv->regs->stat); 851 if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) { 852 if (reg_stat & PCH_BUS_OFF || 853 (reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) { 854 pch_can_error(ndev, reg_stat); 855 quota--; 856 } 857 } 858 859 if (reg_stat & PCH_TX_OK) 860 pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK); 861 862 if (reg_stat & PCH_RX_OK) 863 pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK); 864 865 int_stat = pch_can_int_pending(priv); 866 } 867 868 if (quota == 0) 869 goto end; 870 871 if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) { 872 rcv_pkts += pch_can_rx_normal(ndev, int_stat); 873 quota -= rcv_pkts; 874 if (quota < 0) 875 goto end; 876 } else if ((int_stat >= PCH_TX_OBJ_START) && 877 (int_stat <= PCH_TX_OBJ_END)) { 878 /* Handle transmission interrupt */ 879 pch_can_tx_complete(ndev, int_stat); 880 } 881 882end: 883 napi_complete(napi); 884 pch_can_set_int_enables(priv, PCH_CAN_ALL); 885 886 return rcv_pkts; 887} 888 889static int pch_set_bittiming(struct net_device *ndev) 890{ 891 struct pch_can_priv *priv = netdev_priv(ndev); 892 const struct can_bittiming *bt = &priv->can.bittiming; 893 u32 canbit; 894 u32 bepe; 895 u32 brp; 896 897 /* Setting the CCE bit for accessing the Can Timing register. */ 898 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE); 899 900 brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1; 901 canbit = brp & PCH_MSK_BITT_BRP; 902 canbit |= (bt->sjw - 1) << PCH_BIT_SJW; 903 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1; 904 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2; 905 bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE; 906 iowrite32(canbit, &priv->regs->bitt); 907 iowrite32(bepe, &priv->regs->brpe); 908 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE); 909 910 return 0; 911} 912 913static void pch_can_start(struct net_device *ndev) 914{ 915 struct pch_can_priv *priv = netdev_priv(ndev); 916 917 if (priv->can.state != CAN_STATE_STOPPED) 918 pch_can_reset(priv); 919 920 pch_set_bittiming(ndev); 921 pch_can_set_optmode(priv); 922 923 pch_can_set_tx_all(priv, 1); 924 pch_can_set_rx_all(priv, 1); 925 926 /* Setting the CAN to run mode. */ 927 pch_can_set_run_mode(priv, PCH_CAN_RUN); 928 929 priv->can.state = CAN_STATE_ERROR_ACTIVE; 930 931 return; 932} 933 934static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 935{ 936 int ret = 0; 937 938 switch (mode) { 939 case CAN_MODE_START: 940 pch_can_start(ndev); 941 netif_wake_queue(ndev); 942 break; 943 default: 944 ret = -EOPNOTSUPP; 945 break; 946 } 947 948 return ret; 949} 950 951static int pch_can_open(struct net_device *ndev) 952{ 953 struct pch_can_priv *priv = netdev_priv(ndev); 954 int retval; 955 956 retval = pci_enable_msi(priv->dev); 957 if (retval) { 958 dev_info(&ndev->dev, "PCH CAN opened without MSI\n"); 959 priv->use_msi = 0; 960 } else { 961 dev_info(&ndev->dev, "PCH CAN opened with MSI\n"); 962 priv->use_msi = 1; 963 } 964 965 /* Regsitering the interrupt. */ 966 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED, 967 ndev->name, ndev); 968 if (retval) { 969 dev_err(&ndev->dev, "request_irq failed.\n"); 970 goto req_irq_err; 971 } 972 973 /* Open common can device */ 974 retval = open_candev(ndev); 975 if (retval) { 976 dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval); 977 goto err_open_candev; 978 } 979 980 pch_can_init(priv); 981 pch_can_start(ndev); 982 napi_enable(&priv->napi); 983 netif_start_queue(ndev); 984 985 return 0; 986 987err_open_candev: 988 free_irq(priv->dev->irq, ndev); 989req_irq_err: 990 if (priv->use_msi) 991 pci_disable_msi(priv->dev); 992 993 pch_can_release(priv); 994 995 return retval; 996} 997 998static int pch_close(struct net_device *ndev) 999{ 1000 struct pch_can_priv *priv = netdev_priv(ndev); 1001 1002 netif_stop_queue(ndev); 1003 napi_disable(&priv->napi); 1004 pch_can_release(priv); 1005 free_irq(priv->dev->irq, ndev); 1006 if (priv->use_msi) 1007 pci_disable_msi(priv->dev); 1008 close_candev(ndev); 1009 priv->can.state = CAN_STATE_STOPPED; 1010 return 0; 1011} 1012 1013static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) 1014{ 1015 struct pch_can_priv *priv = netdev_priv(ndev); 1016 struct can_frame *cf = (struct can_frame *)skb->data; 1017 int tx_buffer_avail = 0; 1018 int i; 1019 1020 if (can_dropped_invalid_skb(ndev, skb)) 1021 return NETDEV_TX_OK; 1022 1023 if (priv->tx_obj == PCH_TX_OBJ_END) { 1024 if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK) 1025 netif_stop_queue(ndev); 1026 1027 tx_buffer_avail = priv->tx_obj; 1028 priv->tx_obj = PCH_TX_OBJ_START; 1029 } else { 1030 tx_buffer_avail = priv->tx_obj; 1031 priv->tx_obj++; 1032 } 1033 1034 /* Reading the Msg Obj from the Msg RAM to the Interface register. */ 1035 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); 1036 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); 1037 1038 /* Setting the CMASK register. */ 1039 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL); 1040 1041 /* If ID extended is set. */ 1042 pch_can_bit_clear(&priv->regs->ifregs[1].id1, 0xffff); 1043 pch_can_bit_clear(&priv->regs->ifregs[1].id2, 0x1fff | PCH_ID2_XTD); 1044 if (cf->can_id & CAN_EFF_FLAG) { 1045 pch_can_bit_set(&priv->regs->ifregs[1].id1, 1046 cf->can_id & 0xffff); 1047 pch_can_bit_set(&priv->regs->ifregs[1].id2, 1048 ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD); 1049 } else { 1050 pch_can_bit_set(&priv->regs->ifregs[1].id1, 0); 1051 pch_can_bit_set(&priv->regs->ifregs[1].id2, 1052 (cf->can_id & CAN_SFF_MASK) << 2); 1053 } 1054 1055 /* If remote frame has to be transmitted.. */ 1056 if (cf->can_id & CAN_RTR_FLAG) 1057 pch_can_bit_clear(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); 1058 1059 /* Copy data to register */ 1060 for (i = 0; i < cf->can_dlc; i += 2) { 1061 iowrite16(cf->data[i] | (cf->data[i + 1] << 8), 1062 &priv->regs->ifregs[1].data[i / 2]); 1063 } 1064 1065 can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_END - 1); 1066 1067 /* Updating the size of the data. */ 1068 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 0x0f); 1069 pch_can_bit_set(&priv->regs->ifregs[1].mcont, cf->can_dlc); 1070 1071 /* Clearing IntPend, NewDat & TxRqst */ 1072 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 1073 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | 1074 PCH_IF_MCONT_TXRQXT); 1075 1076 /* Setting NewDat, TxRqst bits */ 1077 pch_can_bit_set(&priv->regs->ifregs[1].mcont, 1078 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT); 1079 1080 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); 1081 1082 return NETDEV_TX_OK; 1083} 1084 1085static const struct net_device_ops pch_can_netdev_ops = { 1086 .ndo_open = pch_can_open, 1087 .ndo_stop = pch_close, 1088 .ndo_start_xmit = pch_xmit, 1089}; 1090 1091static void __devexit pch_can_remove(struct pci_dev *pdev) 1092{ 1093 struct net_device *ndev = pci_get_drvdata(pdev); 1094 struct pch_can_priv *priv = netdev_priv(ndev); 1095 1096 unregister_candev(priv->ndev); 1097 free_candev(priv->ndev); 1098 pci_iounmap(pdev, priv->regs); 1099 pci_release_regions(pdev); 1100 pci_disable_device(pdev); 1101 pci_set_drvdata(pdev, NULL); 1102 pch_can_reset(priv); 1103} 1104 1105#ifdef CONFIG_PM 1106static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state) 1107{ 1108 int i; /* Counter variable. */ 1109 int retval; /* Return value. */ 1110 u32 buf_stat; /* Variable for reading the transmit buffer status. */ 1111 u32 counter = 0xFFFFFF; 1112 1113 struct net_device *dev = pci_get_drvdata(pdev); 1114 struct pch_can_priv *priv = netdev_priv(dev); 1115 1116 /* Stop the CAN controller */ 1117 pch_can_set_run_mode(priv, PCH_CAN_STOP); 1118 1119 /* Indicate that we are aboutto/in suspend */ 1120 priv->can.state = CAN_STATE_SLEEPING; 1121 1122 /* Waiting for all transmission to complete. */ 1123 while (counter) { 1124 buf_stat = pch_can_get_buffer_status(priv); 1125 if (!buf_stat) 1126 break; 1127 counter--; 1128 udelay(1); 1129 } 1130 if (!counter) 1131 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__); 1132 1133 /* Save interrupt configuration and then disable them */ 1134 pch_can_get_int_enables(priv, &(priv->int_enables)); 1135 pch_can_set_int_enables(priv, PCH_CAN_DISABLE); 1136 1137 /* Save Tx buffer enable state */ 1138 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 1139 priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_TX_IFREG); 1140 1141 /* Disable all Transmit buffers */ 1142 pch_can_set_tx_all(priv, 0); 1143 1144 /* Save Rx buffer enable state */ 1145 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 1146 priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG); 1147 pch_can_get_rx_buffer_link(priv, i, &priv->rx_link[i]); 1148 } 1149 1150 /* Disable all Receive buffers */ 1151 pch_can_set_rx_all(priv, 0); 1152 retval = pci_save_state(pdev); 1153 if (retval) { 1154 dev_err(&pdev->dev, "pci_save_state failed.\n"); 1155 } else { 1156 pci_enable_wake(pdev, PCI_D3hot, 0); 1157 pci_disable_device(pdev); 1158 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1159 } 1160 1161 return retval; 1162} 1163 1164static int pch_can_resume(struct pci_dev *pdev) 1165{ 1166 int i; /* Counter variable. */ 1167 int retval; /* Return variable. */ 1168 struct net_device *dev = pci_get_drvdata(pdev); 1169 struct pch_can_priv *priv = netdev_priv(dev); 1170 1171 pci_set_power_state(pdev, PCI_D0); 1172 pci_restore_state(pdev); 1173 retval = pci_enable_device(pdev); 1174 if (retval) { 1175 dev_err(&pdev->dev, "pci_enable_device failed.\n"); 1176 return retval; 1177 } 1178 1179 pci_enable_wake(pdev, PCI_D3hot, 0); 1180 1181 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1182 1183 /* Disabling all interrupts. */ 1184 pch_can_set_int_enables(priv, PCH_CAN_DISABLE); 1185 1186 /* Setting the CAN device in Stop Mode. */ 1187 pch_can_set_run_mode(priv, PCH_CAN_STOP); 1188 1189 /* Configuring the transmit and receive buffers. */ 1190 pch_can_config_rx_tx_buffers(priv); 1191 1192 /* Restore the CAN state */ 1193 pch_set_bittiming(dev); 1194 1195 /* Listen/Active */ 1196 pch_can_set_optmode(priv); 1197 1198 /* Enabling the transmit buffer. */ 1199 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 1200 pch_can_set_rxtx(priv, i, priv->tx_enable[i], PCH_TX_IFREG); 1201 1202 /* Configuring the receive buffer and enabling them. */ 1203 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 1204 /* Restore buffer link */ 1205 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]); 1206 1207 /* Restore buffer enables */ 1208 pch_can_set_rxtx(priv, i, priv->rx_enable[i], PCH_RX_IFREG); 1209 } 1210 1211 /* Enable CAN Interrupts */ 1212 pch_can_set_int_custom(priv); 1213 1214 /* Restore Run Mode */ 1215 pch_can_set_run_mode(priv, PCH_CAN_RUN); 1216 1217 return retval; 1218} 1219#else 1220#define pch_can_suspend NULL 1221#define pch_can_resume NULL 1222#endif 1223 1224static int pch_can_get_berr_counter(const struct net_device *dev, 1225 struct can_berr_counter *bec) 1226{ 1227 struct pch_can_priv *priv = netdev_priv(dev); 1228 1229 bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC; 1230 bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8; 1231 1232 return 0; 1233} 1234 1235static int __devinit pch_can_probe(struct pci_dev *pdev, 1236 const struct pci_device_id *id) 1237{ 1238 struct net_device *ndev; 1239 struct pch_can_priv *priv; 1240 int rc; 1241 void __iomem *addr; 1242 1243 rc = pci_enable_device(pdev); 1244 if (rc) { 1245 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc); 1246 goto probe_exit_endev; 1247 } 1248 1249 rc = pci_request_regions(pdev, KBUILD_MODNAME); 1250 if (rc) { 1251 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc); 1252 goto probe_exit_pcireq; 1253 } 1254 1255 addr = pci_iomap(pdev, 1, 0); 1256 if (!addr) { 1257 rc = -EIO; 1258 dev_err(&pdev->dev, "Failed pci_iomap\n"); 1259 goto probe_exit_ipmap; 1260 } 1261 1262 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END); 1263 if (!ndev) { 1264 rc = -ENOMEM; 1265 dev_err(&pdev->dev, "Failed alloc_candev\n"); 1266 goto probe_exit_alloc_candev; 1267 } 1268 1269 priv = netdev_priv(ndev); 1270 priv->ndev = ndev; 1271 priv->regs = addr; 1272 priv->dev = pdev; 1273 priv->can.bittiming_const = &pch_can_bittiming_const; 1274 priv->can.do_set_mode = pch_can_do_set_mode; 1275 priv->can.do_get_berr_counter = pch_can_get_berr_counter; 1276 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | 1277 CAN_CTRLMODE_LOOPBACK; 1278 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */ 1279 1280 ndev->irq = pdev->irq; 1281 ndev->flags |= IFF_ECHO; 1282 1283 pci_set_drvdata(pdev, ndev); 1284 SET_NETDEV_DEV(ndev, &pdev->dev); 1285 ndev->netdev_ops = &pch_can_netdev_ops; 1286 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */ 1287 1288 netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_END); 1289 1290 rc = register_candev(ndev); 1291 if (rc) { 1292 dev_err(&pdev->dev, "Failed register_candev %d\n", rc); 1293 goto probe_exit_reg_candev; 1294 } 1295 1296 return 0; 1297 1298probe_exit_reg_candev: 1299 free_candev(ndev); 1300probe_exit_alloc_candev: 1301 pci_iounmap(pdev, addr); 1302probe_exit_ipmap: 1303 pci_release_regions(pdev); 1304probe_exit_pcireq: 1305 pci_disable_device(pdev); 1306probe_exit_endev: 1307 return rc; 1308} 1309 1310static struct pci_driver pch_can_pci_driver = { 1311 .name = "pch_can", 1312 .id_table = pch_pci_tbl, 1313 .probe = pch_can_probe, 1314 .remove = __devexit_p(pch_can_remove), 1315 .suspend = pch_can_suspend, 1316 .resume = pch_can_resume, 1317}; 1318 1319static int __init pch_can_pci_init(void) 1320{ 1321 return pci_register_driver(&pch_can_pci_driver); 1322} 1323module_init(pch_can_pci_init); 1324 1325static void __exit pch_can_pci_exit(void) 1326{ 1327 pci_unregister_driver(&pch_can_pci_driver); 1328} 1329module_exit(pch_can_pci_exit); 1330 1331MODULE_DESCRIPTION("Controller Area Network Driver"); 1332MODULE_LICENSE("GPL v2"); 1333MODULE_VERSION("0.94"); 1334