pch_can.c revision d68f6837c4972b0433e41f8bee4b2b8205610f31
1/* 2 * Copyright (C) 1999 - 2010 Intel Corporation. 3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19#include <linux/interrupt.h> 20#include <linux/delay.h> 21#include <linux/io.h> 22#include <linux/module.h> 23#include <linux/sched.h> 24#include <linux/pci.h> 25#include <linux/init.h> 26#include <linux/kernel.h> 27#include <linux/types.h> 28#include <linux/errno.h> 29#include <linux/netdevice.h> 30#include <linux/skbuff.h> 31#include <linux/can.h> 32#include <linux/can/dev.h> 33#include <linux/can/error.h> 34 35#define PCH_ENABLE 1 /* The enable flag */ 36#define PCH_DISABLE 0 /* The disable flag */ 37#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */ 38#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */ 39#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1)) 40#define PCH_CTRL_CCE BIT(6) 41#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */ 42#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */ 43#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */ 44 45#define PCH_CMASK_RX_TX_SET 0x00f3 46#define PCH_CMASK_RX_TX_GET 0x0073 47#define PCH_CMASK_ALL 0xff 48#define PCH_CMASK_NEWDAT BIT(2) 49#define PCH_CMASK_CLRINTPND BIT(3) 50#define PCH_CMASK_CTRL BIT(4) 51#define PCH_CMASK_ARB BIT(5) 52#define PCH_CMASK_MASK BIT(6) 53#define PCH_CMASK_RDWR BIT(7) 54#define PCH_IF_MCONT_NEWDAT BIT(15) 55#define PCH_IF_MCONT_MSGLOST BIT(14) 56#define PCH_IF_MCONT_INTPND BIT(13) 57#define PCH_IF_MCONT_UMASK BIT(12) 58#define PCH_IF_MCONT_TXIE BIT(11) 59#define PCH_IF_MCONT_RXIE BIT(10) 60#define PCH_IF_MCONT_RMTEN BIT(9) 61#define PCH_IF_MCONT_TXRQXT BIT(8) 62#define PCH_IF_MCONT_EOB BIT(7) 63#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 64#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15)) 65#define PCH_ID2_DIR BIT(13) 66#define PCH_ID2_XTD BIT(14) 67#define PCH_ID_MSGVAL BIT(15) 68#define PCH_IF_CREQ_BUSY BIT(15) 69 70#define PCH_STATUS_INT 0x8000 71#define PCH_REC 0x00007f00 72#define PCH_TEC 0x000000ff 73 74 75#define PCH_TX_OK BIT(3) 76#define PCH_RX_OK BIT(4) 77#define PCH_EPASSIV BIT(5) 78#define PCH_EWARN BIT(6) 79#define PCH_BUS_OFF BIT(7) 80 81/* bit position of certain controller bits. */ 82#define PCH_BIT_BRP 0 83#define PCH_BIT_SJW 6 84#define PCH_BIT_TSEG1 8 85#define PCH_BIT_TSEG2 12 86#define PCH_BIT_BRPE_BRPE 6 87#define PCH_MSK_BITT_BRP 0x3f 88#define PCH_MSK_BRPE_BRPE 0x3c0 89#define PCH_MSK_CTRL_IE_SIE_EIE 0x07 90#define PCH_COUNTER_LIMIT 10 91 92#define PCH_CAN_CLK 50000000 /* 50MHz */ 93 94/* Define the number of message object. 95 * PCH CAN communications are done via Message RAM. 96 * The Message RAM consists of 32 message objects. */ 97#define PCH_RX_OBJ_NUM 26 98#define PCH_TX_OBJ_NUM 6 99#define PCH_RX_OBJ_START 1 100#define PCH_RX_OBJ_END PCH_RX_OBJ_NUM 101#define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1) 102#define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM) 103 104#define PCH_FIFO_THRESH 16 105 106enum pch_ifreg { 107 PCH_RX_IFREG, 108 PCH_TX_IFREG, 109}; 110 111enum pch_can_err { 112 PCH_STUF_ERR = 1, 113 PCH_FORM_ERR, 114 PCH_ACK_ERR, 115 PCH_BIT1_ERR, 116 PCH_BIT0_ERR, 117 PCH_CRC_ERR, 118 PCH_LEC_ALL, 119}; 120 121enum pch_can_mode { 122 PCH_CAN_ENABLE, 123 PCH_CAN_DISABLE, 124 PCH_CAN_ALL, 125 PCH_CAN_NONE, 126 PCH_CAN_STOP, 127 PCH_CAN_RUN 128}; 129 130struct pch_can_if_regs { 131 u32 creq; 132 u32 cmask; 133 u32 mask1; 134 u32 mask2; 135 u32 id1; 136 u32 id2; 137 u32 mcont; 138 u32 dataa1; 139 u32 dataa2; 140 u32 datab1; 141 u32 datab2; 142 u32 rsv[13]; 143}; 144 145struct pch_can_regs { 146 u32 cont; 147 u32 stat; 148 u32 errc; 149 u32 bitt; 150 u32 intr; 151 u32 opt; 152 u32 brpe; 153 u32 reserve; 154 struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */ 155 u32 reserve1[8]; 156 u32 treq1; 157 u32 treq2; 158 u32 reserve2[6]; 159 u32 data1; 160 u32 data2; 161 u32 reserve3[6]; 162 u32 canipend1; 163 u32 canipend2; 164 u32 reserve4[6]; 165 u32 canmval1; 166 u32 canmval2; 167 u32 reserve5[37]; 168 u32 srst; 169}; 170 171struct pch_can_priv { 172 struct can_priv can; 173 unsigned int can_num; 174 struct pci_dev *dev; 175 int tx_enable[PCH_TX_OBJ_END]; 176 int rx_enable[PCH_TX_OBJ_END]; 177 int rx_link[PCH_TX_OBJ_END]; 178 unsigned int int_enables; 179 unsigned int int_stat; 180 struct net_device *ndev; 181 spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/ 182 unsigned int msg_obj[PCH_TX_OBJ_END]; 183 struct pch_can_regs __iomem *regs; 184 struct napi_struct napi; 185 unsigned int tx_obj; /* Point next Tx Obj index */ 186 unsigned int use_msi; 187}; 188 189static struct can_bittiming_const pch_can_bittiming_const = { 190 .name = KBUILD_MODNAME, 191 .tseg1_min = 1, 192 .tseg1_max = 16, 193 .tseg2_min = 1, 194 .tseg2_max = 8, 195 .sjw_max = 4, 196 .brp_min = 1, 197 .brp_max = 1024, /* 6bit + extended 4bit */ 198 .brp_inc = 1, 199}; 200 201static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = { 202 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,}, 203 {0,} 204}; 205MODULE_DEVICE_TABLE(pci, pch_pci_tbl); 206 207static inline void pch_can_bit_set(void __iomem *addr, u32 mask) 208{ 209 iowrite32(ioread32(addr) | mask, addr); 210} 211 212static inline void pch_can_bit_clear(void __iomem *addr, u32 mask) 213{ 214 iowrite32(ioread32(addr) & ~mask, addr); 215} 216 217static void pch_can_set_run_mode(struct pch_can_priv *priv, 218 enum pch_can_mode mode) 219{ 220 switch (mode) { 221 case PCH_CAN_RUN: 222 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT); 223 break; 224 225 case PCH_CAN_STOP: 226 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT); 227 break; 228 229 default: 230 dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__); 231 break; 232 } 233} 234 235static void pch_can_set_optmode(struct pch_can_priv *priv) 236{ 237 u32 reg_val = ioread32(&priv->regs->opt); 238 239 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 240 reg_val |= PCH_OPT_SILENT; 241 242 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 243 reg_val |= PCH_OPT_LBACK; 244 245 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT); 246 iowrite32(reg_val, &priv->regs->opt); 247} 248 249static void pch_can_set_int_custom(struct pch_can_priv *priv) 250{ 251 /* Clearing the IE, SIE and EIE bits of Can control register. */ 252 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 253 254 /* Appropriately setting them. */ 255 pch_can_bit_set(&priv->regs->cont, 256 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1)); 257} 258 259/* This function retrieves interrupt enabled for the CAN device. */ 260static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables) 261{ 262 /* Obtaining the status of IE, SIE and EIE interrupt bits. */ 263 *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1); 264} 265 266static void pch_can_set_int_enables(struct pch_can_priv *priv, 267 enum pch_can_mode interrupt_no) 268{ 269 switch (interrupt_no) { 270 case PCH_CAN_ENABLE: 271 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE); 272 break; 273 274 case PCH_CAN_DISABLE: 275 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE); 276 break; 277 278 case PCH_CAN_ALL: 279 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 280 break; 281 282 case PCH_CAN_NONE: 283 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 284 break; 285 286 default: 287 dev_err(&priv->ndev->dev, "Invalid interrupt number.\n"); 288 break; 289 } 290} 291 292static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num) 293{ 294 u32 counter = PCH_COUNTER_LIMIT; 295 u32 ifx_creq; 296 297 iowrite32(num, creq_addr); 298 while (counter) { 299 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY; 300 if (!ifx_creq) 301 break; 302 counter--; 303 udelay(1); 304 } 305 if (!counter) 306 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__); 307} 308 309static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, 310 u32 set, enum pch_ifreg dir) 311{ 312 unsigned long flags; 313 u32 ie; 314 315 if (dir) 316 ie = PCH_IF_MCONT_TXIE; 317 else 318 ie = PCH_IF_MCONT_RXIE; 319 320 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 321 /* Reading the receive buffer data from RAM to Interface1 registers */ 322 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); 323 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 324 325 /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */ 326 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL, 327 &priv->regs->ifregs[dir].cmask); 328 329 if (set == PCH_ENABLE) { 330 /* Setting the MsgVal and RxIE bits */ 331 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie); 332 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); 333 334 } else if (set == PCH_DISABLE) { 335 /* Resetting the MsgVal and RxIE bits */ 336 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie); 337 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); 338 } 339 340 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 341 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 342} 343 344 345static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set) 346{ 347 int i; 348 349 /* Traversing to obtain the object configured as receivers. */ 350 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) 351 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG); 352} 353 354static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set) 355{ 356 int i; 357 358 /* Traversing to obtain the object configured as transmit object. */ 359 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 360 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG); 361} 362 363static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, 364 enum pch_ifreg dir) 365{ 366 unsigned long flags; 367 u32 ie, enable; 368 369 if (dir) 370 ie = PCH_IF_MCONT_RXIE; 371 else 372 ie = PCH_IF_MCONT_TXIE; 373 374 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 375 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); 376 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 377 378 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) && 379 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) { 380 enable = 1; 381 } else { 382 enable = 0; 383 } 384 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 385 return enable; 386} 387 388static int pch_can_int_pending(struct pch_can_priv *priv) 389{ 390 return ioread32(&priv->regs->intr) & 0xffff; 391} 392 393static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, 394 u32 buffer_num, u32 set) 395{ 396 unsigned long flags; 397 398 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 399 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 400 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 401 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, 402 &priv->regs->ifregs[0].cmask); 403 if (set == PCH_ENABLE) 404 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 405 PCH_IF_MCONT_EOB); 406 else 407 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB); 408 409 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 410 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 411} 412 413static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv, 414 u32 buffer_num, u32 *link) 415{ 416 unsigned long flags; 417 418 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 419 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 420 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 421 422 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB) 423 *link = PCH_DISABLE; 424 else 425 *link = PCH_ENABLE; 426 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 427} 428 429static void pch_can_clear_buffers(struct pch_can_priv *priv) 430{ 431 int i; 432 433 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 434 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask); 435 iowrite32(0xffff, &priv->regs->ifregs[0].mask1); 436 iowrite32(0xffff, &priv->regs->ifregs[0].mask2); 437 iowrite32(0x0, &priv->regs->ifregs[0].id1); 438 iowrite32(0x0, &priv->regs->ifregs[0].id2); 439 iowrite32(0x0, &priv->regs->ifregs[0].mcont); 440 iowrite32(0x0, &priv->regs->ifregs[0].dataa1); 441 iowrite32(0x0, &priv->regs->ifregs[0].dataa2); 442 iowrite32(0x0, &priv->regs->ifregs[0].datab1); 443 iowrite32(0x0, &priv->regs->ifregs[0].datab2); 444 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 445 PCH_CMASK_ARB | PCH_CMASK_CTRL, 446 &priv->regs->ifregs[0].cmask); 447 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 448 } 449 450 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { 451 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[1].cmask); 452 iowrite32(0xffff, &priv->regs->ifregs[1].mask1); 453 iowrite32(0xffff, &priv->regs->ifregs[1].mask2); 454 iowrite32(0x0, &priv->regs->ifregs[1].id1); 455 iowrite32(0x0, &priv->regs->ifregs[1].id2); 456 iowrite32(0x0, &priv->regs->ifregs[1].mcont); 457 iowrite32(0x0, &priv->regs->ifregs[1].dataa1); 458 iowrite32(0x0, &priv->regs->ifregs[1].dataa2); 459 iowrite32(0x0, &priv->regs->ifregs[1].datab1); 460 iowrite32(0x0, &priv->regs->ifregs[1].datab2); 461 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 462 PCH_CMASK_ARB | PCH_CMASK_CTRL, 463 &priv->regs->ifregs[1].cmask); 464 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 465 } 466} 467 468static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) 469{ 470 int i; 471 unsigned long flags; 472 473 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 474 475 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 476 iowrite32(PCH_CMASK_RX_TX_GET, 477 &priv->regs->ifregs[0].cmask); 478 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 479 480 iowrite32(0x0, &priv->regs->ifregs[0].id1); 481 iowrite32(0x0, &priv->regs->ifregs[0].id2); 482 483 pch_can_bit_set(&priv->regs->ifregs[0].mcont, 484 PCH_IF_MCONT_UMASK); 485 486 /* Set FIFO mode set to 0 except last Rx Obj*/ 487 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 488 PCH_IF_MCONT_EOB); 489 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */ 490 if (i == PCH_RX_OBJ_END) 491 pch_can_bit_set(&priv->regs->ifregs[0].mcont, 492 PCH_IF_MCONT_EOB); 493 494 iowrite32(0, &priv->regs->ifregs[0].mask1); 495 pch_can_bit_clear(&priv->regs->ifregs[0].mask2, 496 0x1fff | PCH_MASK2_MDIR_MXTD); 497 498 /* Setting CMASK for writing */ 499 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 500 PCH_CMASK_ARB | PCH_CMASK_CTRL, 501 &priv->regs->ifregs[0].cmask); 502 503 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 504 } 505 506 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { 507 iowrite32(PCH_CMASK_RX_TX_GET, 508 &priv->regs->ifregs[1].cmask); 509 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 510 511 /* Resetting DIR bit for reception */ 512 iowrite32(0x0, &priv->regs->ifregs[1].id1); 513 iowrite32(0x0, &priv->regs->ifregs[1].id2); 514 pch_can_bit_set(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); 515 516 /* Setting EOB bit for transmitter */ 517 iowrite32(PCH_IF_MCONT_EOB, &priv->regs->ifregs[1].mcont); 518 519 pch_can_bit_set(&priv->regs->ifregs[1].mcont, 520 PCH_IF_MCONT_UMASK); 521 522 iowrite32(0, &priv->regs->ifregs[1].mask1); 523 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff); 524 525 /* Setting CMASK for writing */ 526 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 527 PCH_CMASK_ARB | PCH_CMASK_CTRL, 528 &priv->regs->ifregs[1].cmask); 529 530 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 531 } 532 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 533} 534 535static void pch_can_init(struct pch_can_priv *priv) 536{ 537 /* Stopping the Can device. */ 538 pch_can_set_run_mode(priv, PCH_CAN_STOP); 539 540 /* Clearing all the message object buffers. */ 541 pch_can_clear_buffers(priv); 542 543 /* Configuring the respective message object as either rx/tx object. */ 544 pch_can_config_rx_tx_buffers(priv); 545 546 /* Enabling the interrupts. */ 547 pch_can_set_int_enables(priv, PCH_CAN_ALL); 548} 549 550static void pch_can_release(struct pch_can_priv *priv) 551{ 552 /* Stooping the CAN device. */ 553 pch_can_set_run_mode(priv, PCH_CAN_STOP); 554 555 /* Disabling the interrupts. */ 556 pch_can_set_int_enables(priv, PCH_CAN_NONE); 557 558 /* Disabling all the receive object. */ 559 pch_can_set_rx_all(priv, 0); 560 561 /* Disabling all the transmit object. */ 562 pch_can_set_tx_all(priv, 0); 563} 564 565/* This function clears interrupt(s) from the CAN device. */ 566static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) 567{ 568 if (mask == PCH_STATUS_INT) { 569 ioread32(&priv->regs->stat); 570 return; 571 } 572 573 /* Clear interrupt for transmit object */ 574 if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) { 575 /* Setting CMASK for clearing the reception interrupts. */ 576 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, 577 &priv->regs->ifregs[0].cmask); 578 579 /* Clearing the Dir bit. */ 580 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); 581 582 /* Clearing NewDat & IntPnd */ 583 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 584 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND); 585 586 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, mask); 587 } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) { 588 /* Setting CMASK for clearing interrupts for 589 frame transmission. */ 590 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, 591 &priv->regs->ifregs[1].cmask); 592 593 /* Resetting the ID registers. */ 594 pch_can_bit_set(&priv->regs->ifregs[1].id2, 595 PCH_ID2_DIR | (0x7ff << 2)); 596 iowrite32(0x0, &priv->regs->ifregs[1].id1); 597 598 /* Claring NewDat, TxRqst & IntPnd */ 599 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 600 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | 601 PCH_IF_MCONT_TXRQXT); 602 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, mask); 603 } 604} 605 606static int pch_can_get_buffer_status(struct pch_can_priv *priv) 607{ 608 return (ioread32(&priv->regs->treq1) & 0xffff) | 609 ((ioread32(&priv->regs->treq2) & 0xffff) << 16); 610} 611 612static void pch_can_reset(struct pch_can_priv *priv) 613{ 614 /* write to sw reset register */ 615 iowrite32(1, &priv->regs->srst); 616 iowrite32(0, &priv->regs->srst); 617} 618 619static void pch_can_error(struct net_device *ndev, u32 status) 620{ 621 struct sk_buff *skb; 622 struct pch_can_priv *priv = netdev_priv(ndev); 623 struct can_frame *cf; 624 u32 errc, lec; 625 struct net_device_stats *stats = &(priv->ndev->stats); 626 enum can_state state = priv->can.state; 627 628 skb = alloc_can_err_skb(ndev, &cf); 629 if (!skb) 630 return; 631 632 if (status & PCH_BUS_OFF) { 633 pch_can_set_tx_all(priv, 0); 634 pch_can_set_rx_all(priv, 0); 635 state = CAN_STATE_BUS_OFF; 636 cf->can_id |= CAN_ERR_BUSOFF; 637 can_bus_off(ndev); 638 pch_can_set_run_mode(priv, PCH_CAN_RUN); 639 dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__); 640 } 641 642 /* Warning interrupt. */ 643 if (status & PCH_EWARN) { 644 state = CAN_STATE_ERROR_WARNING; 645 priv->can.can_stats.error_warning++; 646 cf->can_id |= CAN_ERR_CRTL; 647 errc = ioread32(&priv->regs->errc); 648 if (((errc & PCH_REC) >> 8) > 96) 649 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; 650 if ((errc & PCH_TEC) > 96) 651 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; 652 dev_warn(&ndev->dev, 653 "%s -> Error Counter is more than 96.\n", __func__); 654 } 655 /* Error passive interrupt. */ 656 if (status & PCH_EPASSIV) { 657 priv->can.can_stats.error_passive++; 658 state = CAN_STATE_ERROR_PASSIVE; 659 cf->can_id |= CAN_ERR_CRTL; 660 errc = ioread32(&priv->regs->errc); 661 if (((errc & PCH_REC) >> 8) > 127) 662 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 663 if ((errc & PCH_TEC) > 127) 664 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 665 dev_err(&ndev->dev, 666 "%s -> CAN controller is ERROR PASSIVE .\n", __func__); 667 } 668 669 lec = status & PCH_LEC_ALL; 670 switch (lec) { 671 case PCH_STUF_ERR: 672 cf->data[2] |= CAN_ERR_PROT_STUFF; 673 priv->can.can_stats.bus_error++; 674 stats->rx_errors++; 675 break; 676 case PCH_FORM_ERR: 677 cf->data[2] |= CAN_ERR_PROT_FORM; 678 priv->can.can_stats.bus_error++; 679 stats->rx_errors++; 680 break; 681 case PCH_ACK_ERR: 682 cf->can_id |= CAN_ERR_ACK; 683 priv->can.can_stats.bus_error++; 684 stats->rx_errors++; 685 break; 686 case PCH_BIT1_ERR: 687 case PCH_BIT0_ERR: 688 cf->data[2] |= CAN_ERR_PROT_BIT; 689 priv->can.can_stats.bus_error++; 690 stats->rx_errors++; 691 break; 692 case PCH_CRC_ERR: 693 cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ | 694 CAN_ERR_PROT_LOC_CRC_DEL; 695 priv->can.can_stats.bus_error++; 696 stats->rx_errors++; 697 break; 698 case PCH_LEC_ALL: /* Written by CPU. No error status */ 699 break; 700 } 701 702 priv->can.state = state; 703 netif_rx(skb); 704 705 stats->rx_packets++; 706 stats->rx_bytes += cf->can_dlc; 707} 708 709static irqreturn_t pch_can_interrupt(int irq, void *dev_id) 710{ 711 struct net_device *ndev = (struct net_device *)dev_id; 712 struct pch_can_priv *priv = netdev_priv(ndev); 713 714 pch_can_set_int_enables(priv, PCH_CAN_NONE); 715 716 napi_schedule(&priv->napi); 717 718 return IRQ_HANDLED; 719} 720 721static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat) 722{ 723 u32 reg; 724 canid_t id; 725 u32 ide; 726 u32 rtr; 727 int i, j, k; 728 int rcv_pkts = 0; 729 struct sk_buff *skb; 730 struct can_frame *cf; 731 struct pch_can_priv *priv = netdev_priv(ndev); 732 struct net_device_stats *stats = &(priv->ndev->stats); 733 734 /* Reading the messsage object from the Message RAM */ 735 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 736 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, int_stat); 737 738 /* Reading the MCONT register. */ 739 reg = ioread32(&priv->regs->ifregs[0].mcont); 740 reg &= 0xffff; 741 742 for (k = int_stat; !(reg & PCH_IF_MCONT_EOB); k++) { 743 /* If MsgLost bit set. */ 744 if (reg & PCH_IF_MCONT_MSGLOST) { 745 dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n"); 746 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 747 PCH_IF_MCONT_MSGLOST); 748 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, 749 &priv->regs->ifregs[0].cmask); 750 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 751 752 skb = alloc_can_err_skb(ndev, &cf); 753 if (!skb) 754 return -ENOMEM; 755 756 priv->can.can_stats.error_passive++; 757 priv->can.state = CAN_STATE_ERROR_PASSIVE; 758 cf->can_id |= CAN_ERR_CRTL; 759 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; 760 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 761 stats->rx_packets++; 762 stats->rx_bytes += cf->can_dlc; 763 764 netif_receive_skb(skb); 765 rcv_pkts++; 766 goto RX_NEXT; 767 } 768 if (!(reg & PCH_IF_MCONT_NEWDAT)) 769 goto RX_NEXT; 770 771 skb = alloc_can_skb(priv->ndev, &cf); 772 if (!skb) 773 return -ENOMEM; 774 775 /* Get Received data */ 776 ide = ((ioread32(&priv->regs->ifregs[0].id2)) & PCH_ID2_XTD) >> 777 14; 778 if (ide) { 779 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff); 780 id |= (((ioread32(&priv->regs->ifregs[0].id2)) & 781 0x1fff) << 16); 782 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; 783 } else { 784 id = (((ioread32(&priv->regs->ifregs[0].id2)) & 785 (CAN_SFF_MASK << 2)) >> 2); 786 cf->can_id = (id & CAN_SFF_MASK); 787 } 788 789 rtr = (ioread32(&priv->regs->ifregs[0].id2) & PCH_ID2_DIR); 790 if (rtr) { 791 cf->can_dlc = 0; 792 cf->can_id |= CAN_RTR_FLAG; 793 } else { 794 cf->can_dlc = 795 ((ioread32(&priv->regs->ifregs[0].mcont)) & 0x0f); 796 } 797 798 for (i = 0, j = 0; i < cf->can_dlc; j++) { 799 reg = ioread32(&priv->regs->ifregs[0].dataa1 + j*4); 800 cf->data[i++] = cpu_to_le32(reg & 0xff); 801 if (i == cf->can_dlc) 802 break; 803 cf->data[i++] = cpu_to_le32((reg >> 8) & 0xff); 804 } 805 806 netif_receive_skb(skb); 807 rcv_pkts++; 808 stats->rx_packets++; 809 stats->rx_bytes += cf->can_dlc; 810 811 if (k < PCH_FIFO_THRESH) { 812 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | 813 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask); 814 815 /* Clearing the Dir bit. */ 816 pch_can_bit_clear(&priv->regs->ifregs[0].id2, 817 PCH_ID2_DIR); 818 819 /* Clearing NewDat & IntPnd */ 820 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 821 PCH_IF_MCONT_INTPND); 822 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 823 } else if (k > PCH_FIFO_THRESH) { 824 pch_can_int_clr(priv, k); 825 } else if (k == PCH_FIFO_THRESH) { 826 int cnt; 827 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++) 828 pch_can_int_clr(priv, cnt+1); 829 } 830RX_NEXT: 831 /* Reading the messsage object from the Message RAM */ 832 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 833 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 834 reg = ioread32(&priv->regs->ifregs[0].mcont); 835 } 836 837 return rcv_pkts; 838} 839static int pch_can_rx_poll(struct napi_struct *napi, int quota) 840{ 841 struct net_device *ndev = napi->dev; 842 struct pch_can_priv *priv = netdev_priv(ndev); 843 struct net_device_stats *stats = &(priv->ndev->stats); 844 u32 dlc; 845 u32 int_stat; 846 int rcv_pkts = 0; 847 u32 reg_stat; 848 unsigned long flags; 849 850 int_stat = pch_can_int_pending(priv); 851 if (!int_stat) 852 return 0; 853 854INT_STAT: 855 if (int_stat == PCH_STATUS_INT) { 856 reg_stat = ioread32(&priv->regs->stat); 857 if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) { 858 if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) 859 pch_can_error(ndev, reg_stat); 860 } 861 862 if (reg_stat & PCH_TX_OK) { 863 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 864 iowrite32(PCH_CMASK_RX_TX_GET, 865 &priv->regs->ifregs[1].cmask); 866 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, 867 ioread32(&priv->regs->intr)); 868 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 869 pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK); 870 } 871 872 if (reg_stat & PCH_RX_OK) 873 pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK); 874 875 int_stat = pch_can_int_pending(priv); 876 if (int_stat == PCH_STATUS_INT) 877 goto INT_STAT; 878 } 879 880MSG_OBJ: 881 if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) { 882 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 883 rcv_pkts = pch_can_rx_normal(ndev, int_stat); 884 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 885 if (rcv_pkts < 0) 886 return 0; 887 } else if ((int_stat >= PCH_TX_OBJ_START) && 888 (int_stat <= PCH_TX_OBJ_END)) { 889 /* Handle transmission interrupt */ 890 can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1); 891 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 892 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND, 893 &priv->regs->ifregs[1].cmask); 894 dlc = ioread32(&priv->regs->ifregs[1].mcont) & 895 PCH_IF_MCONT_DLC; 896 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat); 897 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 898 if (dlc > 8) 899 dlc = 8; 900 stats->tx_bytes += dlc; 901 stats->tx_packets++; 902 } 903 904 int_stat = pch_can_int_pending(priv); 905 if (int_stat == PCH_STATUS_INT) 906 goto INT_STAT; 907 else if (int_stat >= 1 && int_stat <= 32) 908 goto MSG_OBJ; 909 910 napi_complete(napi); 911 pch_can_set_int_enables(priv, PCH_CAN_ALL); 912 913 return rcv_pkts; 914} 915 916static int pch_set_bittiming(struct net_device *ndev) 917{ 918 struct pch_can_priv *priv = netdev_priv(ndev); 919 const struct can_bittiming *bt = &priv->can.bittiming; 920 u32 canbit; 921 u32 bepe; 922 u32 brp; 923 924 /* Setting the CCE bit for accessing the Can Timing register. */ 925 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE); 926 927 brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1; 928 canbit = brp & PCH_MSK_BITT_BRP; 929 canbit |= (bt->sjw - 1) << PCH_BIT_SJW; 930 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1; 931 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2; 932 bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE; 933 iowrite32(canbit, &priv->regs->bitt); 934 iowrite32(bepe, &priv->regs->brpe); 935 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE); 936 937 return 0; 938} 939 940static void pch_can_start(struct net_device *ndev) 941{ 942 struct pch_can_priv *priv = netdev_priv(ndev); 943 944 if (priv->can.state != CAN_STATE_STOPPED) 945 pch_can_reset(priv); 946 947 pch_set_bittiming(ndev); 948 pch_can_set_optmode(priv); 949 950 pch_can_set_tx_all(priv, 1); 951 pch_can_set_rx_all(priv, 1); 952 953 /* Setting the CAN to run mode. */ 954 pch_can_set_run_mode(priv, PCH_CAN_RUN); 955 956 priv->can.state = CAN_STATE_ERROR_ACTIVE; 957 958 return; 959} 960 961static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 962{ 963 int ret = 0; 964 965 switch (mode) { 966 case CAN_MODE_START: 967 pch_can_start(ndev); 968 netif_wake_queue(ndev); 969 break; 970 default: 971 ret = -EOPNOTSUPP; 972 break; 973 } 974 975 return ret; 976} 977 978static int pch_can_open(struct net_device *ndev) 979{ 980 struct pch_can_priv *priv = netdev_priv(ndev); 981 int retval; 982 983 retval = pci_enable_msi(priv->dev); 984 if (retval) { 985 dev_info(&ndev->dev, "PCH CAN opened without MSI\n"); 986 priv->use_msi = 0; 987 } else { 988 dev_info(&ndev->dev, "PCH CAN opened with MSI\n"); 989 priv->use_msi = 1; 990 } 991 992 /* Regsitering the interrupt. */ 993 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED, 994 ndev->name, ndev); 995 if (retval) { 996 dev_err(&ndev->dev, "request_irq failed.\n"); 997 goto req_irq_err; 998 } 999 1000 /* Open common can device */ 1001 retval = open_candev(ndev); 1002 if (retval) { 1003 dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval); 1004 goto err_open_candev; 1005 } 1006 1007 pch_can_init(priv); 1008 pch_can_start(ndev); 1009 napi_enable(&priv->napi); 1010 netif_start_queue(ndev); 1011 1012 return 0; 1013 1014err_open_candev: 1015 free_irq(priv->dev->irq, ndev); 1016req_irq_err: 1017 if (priv->use_msi) 1018 pci_disable_msi(priv->dev); 1019 1020 pch_can_release(priv); 1021 1022 return retval; 1023} 1024 1025static int pch_close(struct net_device *ndev) 1026{ 1027 struct pch_can_priv *priv = netdev_priv(ndev); 1028 1029 netif_stop_queue(ndev); 1030 napi_disable(&priv->napi); 1031 pch_can_release(priv); 1032 free_irq(priv->dev->irq, ndev); 1033 if (priv->use_msi) 1034 pci_disable_msi(priv->dev); 1035 close_candev(ndev); 1036 priv->can.state = CAN_STATE_STOPPED; 1037 return 0; 1038} 1039 1040static int pch_get_msg_obj_sts(struct net_device *ndev, u32 obj_id) 1041{ 1042 u32 buffer_status = 0; 1043 struct pch_can_priv *priv = netdev_priv(ndev); 1044 1045 /* Getting the message object status. */ 1046 buffer_status = (u32) pch_can_get_buffer_status(priv); 1047 1048 return buffer_status & obj_id; 1049} 1050 1051 1052static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) 1053{ 1054 int i, j; 1055 unsigned long flags; 1056 struct pch_can_priv *priv = netdev_priv(ndev); 1057 struct can_frame *cf = (struct can_frame *)skb->data; 1058 int tx_buffer_avail = 0; 1059 1060 if (can_dropped_invalid_skb(ndev, skb)) 1061 return NETDEV_TX_OK; 1062 1063 if (priv->tx_obj == PCH_TX_OBJ_END) { /* Point tail Obj */ 1064 while (pch_get_msg_obj_sts(ndev, (((1 << PCH_TX_OBJ_NUM)-1) << 1065 PCH_RX_OBJ_NUM))) 1066 udelay(500); 1067 1068 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj ID */ 1069 tx_buffer_avail = priv->tx_obj; /* Point Tail of Tx Obj */ 1070 } else { 1071 tx_buffer_avail = priv->tx_obj; 1072 } 1073 priv->tx_obj++; 1074 1075 /* Attaining the lock. */ 1076 spin_lock_irqsave(&priv->msgif_reg_lock, flags); 1077 1078 /* Reading the Msg Obj from the Msg RAM to the Interface register. */ 1079 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); 1080 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); 1081 1082 /* Setting the CMASK register. */ 1083 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL); 1084 1085 /* If ID extended is set. */ 1086 pch_can_bit_clear(&priv->regs->ifregs[1].id1, 0xffff); 1087 pch_can_bit_clear(&priv->regs->ifregs[1].id2, 0x1fff | PCH_ID2_XTD); 1088 if (cf->can_id & CAN_EFF_FLAG) { 1089 pch_can_bit_set(&priv->regs->ifregs[1].id1, 1090 cf->can_id & 0xffff); 1091 pch_can_bit_set(&priv->regs->ifregs[1].id2, 1092 ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD); 1093 } else { 1094 pch_can_bit_set(&priv->regs->ifregs[1].id1, 0); 1095 pch_can_bit_set(&priv->regs->ifregs[1].id2, 1096 (cf->can_id & CAN_SFF_MASK) << 2); 1097 } 1098 1099 /* If remote frame has to be transmitted.. */ 1100 if (cf->can_id & CAN_RTR_FLAG) 1101 pch_can_bit_clear(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); 1102 1103 for (i = 0, j = 0; i < cf->can_dlc; j++) { 1104 iowrite32(le32_to_cpu(cf->data[i++]), 1105 (&priv->regs->ifregs[1].dataa1) + j*4); 1106 if (i == cf->can_dlc) 1107 break; 1108 iowrite32(le32_to_cpu(cf->data[i++] << 8), 1109 (&priv->regs->ifregs[1].dataa1) + j*4); 1110 } 1111 1112 can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_END - 1); 1113 1114 /* Updating the size of the data. */ 1115 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 0x0f); 1116 pch_can_bit_set(&priv->regs->ifregs[1].mcont, cf->can_dlc); 1117 1118 /* Clearing IntPend, NewDat & TxRqst */ 1119 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 1120 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | 1121 PCH_IF_MCONT_TXRQXT); 1122 1123 /* Setting NewDat, TxRqst bits */ 1124 pch_can_bit_set(&priv->regs->ifregs[1].mcont, 1125 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT); 1126 1127 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); 1128 1129 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); 1130 1131 return NETDEV_TX_OK; 1132} 1133 1134static const struct net_device_ops pch_can_netdev_ops = { 1135 .ndo_open = pch_can_open, 1136 .ndo_stop = pch_close, 1137 .ndo_start_xmit = pch_xmit, 1138}; 1139 1140static void __devexit pch_can_remove(struct pci_dev *pdev) 1141{ 1142 struct net_device *ndev = pci_get_drvdata(pdev); 1143 struct pch_can_priv *priv = netdev_priv(ndev); 1144 1145 unregister_candev(priv->ndev); 1146 free_candev(priv->ndev); 1147 pci_iounmap(pdev, priv->regs); 1148 pci_release_regions(pdev); 1149 pci_disable_device(pdev); 1150 pci_set_drvdata(pdev, NULL); 1151 pch_can_reset(priv); 1152} 1153 1154#ifdef CONFIG_PM 1155static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state) 1156{ 1157 int i; /* Counter variable. */ 1158 int retval; /* Return value. */ 1159 u32 buf_stat; /* Variable for reading the transmit buffer status. */ 1160 u32 counter = 0xFFFFFF; 1161 1162 struct net_device *dev = pci_get_drvdata(pdev); 1163 struct pch_can_priv *priv = netdev_priv(dev); 1164 1165 /* Stop the CAN controller */ 1166 pch_can_set_run_mode(priv, PCH_CAN_STOP); 1167 1168 /* Indicate that we are aboutto/in suspend */ 1169 priv->can.state = CAN_STATE_SLEEPING; 1170 1171 /* Waiting for all transmission to complete. */ 1172 while (counter) { 1173 buf_stat = pch_can_get_buffer_status(priv); 1174 if (!buf_stat) 1175 break; 1176 counter--; 1177 udelay(1); 1178 } 1179 if (!counter) 1180 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__); 1181 1182 /* Save interrupt configuration and then disable them */ 1183 pch_can_get_int_enables(priv, &(priv->int_enables)); 1184 pch_can_set_int_enables(priv, PCH_CAN_DISABLE); 1185 1186 /* Save Tx buffer enable state */ 1187 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 1188 priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_TX_IFREG); 1189 1190 /* Disable all Transmit buffers */ 1191 pch_can_set_tx_all(priv, 0); 1192 1193 /* Save Rx buffer enable state */ 1194 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 1195 priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG); 1196 pch_can_get_rx_buffer_link(priv, i, &priv->rx_link[i]); 1197 } 1198 1199 /* Disable all Receive buffers */ 1200 pch_can_set_rx_all(priv, 0); 1201 retval = pci_save_state(pdev); 1202 if (retval) { 1203 dev_err(&pdev->dev, "pci_save_state failed.\n"); 1204 } else { 1205 pci_enable_wake(pdev, PCI_D3hot, 0); 1206 pci_disable_device(pdev); 1207 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1208 } 1209 1210 return retval; 1211} 1212 1213static int pch_can_resume(struct pci_dev *pdev) 1214{ 1215 int i; /* Counter variable. */ 1216 int retval; /* Return variable. */ 1217 struct net_device *dev = pci_get_drvdata(pdev); 1218 struct pch_can_priv *priv = netdev_priv(dev); 1219 1220 pci_set_power_state(pdev, PCI_D0); 1221 pci_restore_state(pdev); 1222 retval = pci_enable_device(pdev); 1223 if (retval) { 1224 dev_err(&pdev->dev, "pci_enable_device failed.\n"); 1225 return retval; 1226 } 1227 1228 pci_enable_wake(pdev, PCI_D3hot, 0); 1229 1230 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1231 1232 /* Disabling all interrupts. */ 1233 pch_can_set_int_enables(priv, PCH_CAN_DISABLE); 1234 1235 /* Setting the CAN device in Stop Mode. */ 1236 pch_can_set_run_mode(priv, PCH_CAN_STOP); 1237 1238 /* Configuring the transmit and receive buffers. */ 1239 pch_can_config_rx_tx_buffers(priv); 1240 1241 /* Restore the CAN state */ 1242 pch_set_bittiming(dev); 1243 1244 /* Listen/Active */ 1245 pch_can_set_optmode(priv); 1246 1247 /* Enabling the transmit buffer. */ 1248 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 1249 pch_can_set_rxtx(priv, i, priv->tx_enable[i], PCH_TX_IFREG); 1250 1251 /* Configuring the receive buffer and enabling them. */ 1252 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 1253 /* Restore buffer link */ 1254 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]); 1255 1256 /* Restore buffer enables */ 1257 pch_can_set_rxtx(priv, i, priv->rx_enable[i], PCH_RX_IFREG); 1258 } 1259 1260 /* Enable CAN Interrupts */ 1261 pch_can_set_int_custom(priv); 1262 1263 /* Restore Run Mode */ 1264 pch_can_set_run_mode(priv, PCH_CAN_RUN); 1265 1266 return retval; 1267} 1268#else 1269#define pch_can_suspend NULL 1270#define pch_can_resume NULL 1271#endif 1272 1273static int pch_can_get_berr_counter(const struct net_device *dev, 1274 struct can_berr_counter *bec) 1275{ 1276 struct pch_can_priv *priv = netdev_priv(dev); 1277 1278 bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC; 1279 bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8; 1280 1281 return 0; 1282} 1283 1284static int __devinit pch_can_probe(struct pci_dev *pdev, 1285 const struct pci_device_id *id) 1286{ 1287 struct net_device *ndev; 1288 struct pch_can_priv *priv; 1289 int rc; 1290 void __iomem *addr; 1291 1292 rc = pci_enable_device(pdev); 1293 if (rc) { 1294 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc); 1295 goto probe_exit_endev; 1296 } 1297 1298 rc = pci_request_regions(pdev, KBUILD_MODNAME); 1299 if (rc) { 1300 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc); 1301 goto probe_exit_pcireq; 1302 } 1303 1304 addr = pci_iomap(pdev, 1, 0); 1305 if (!addr) { 1306 rc = -EIO; 1307 dev_err(&pdev->dev, "Failed pci_iomap\n"); 1308 goto probe_exit_ipmap; 1309 } 1310 1311 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END); 1312 if (!ndev) { 1313 rc = -ENOMEM; 1314 dev_err(&pdev->dev, "Failed alloc_candev\n"); 1315 goto probe_exit_alloc_candev; 1316 } 1317 1318 priv = netdev_priv(ndev); 1319 priv->ndev = ndev; 1320 priv->regs = addr; 1321 priv->dev = pdev; 1322 priv->can.bittiming_const = &pch_can_bittiming_const; 1323 priv->can.do_set_mode = pch_can_do_set_mode; 1324 priv->can.do_get_berr_counter = pch_can_get_berr_counter; 1325 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | 1326 CAN_CTRLMODE_LOOPBACK; 1327 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */ 1328 1329 ndev->irq = pdev->irq; 1330 ndev->flags |= IFF_ECHO; 1331 1332 pci_set_drvdata(pdev, ndev); 1333 SET_NETDEV_DEV(ndev, &pdev->dev); 1334 ndev->netdev_ops = &pch_can_netdev_ops; 1335 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */ 1336 1337 netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_END); 1338 1339 rc = register_candev(ndev); 1340 if (rc) { 1341 dev_err(&pdev->dev, "Failed register_candev %d\n", rc); 1342 goto probe_exit_reg_candev; 1343 } 1344 1345 return 0; 1346 1347probe_exit_reg_candev: 1348 free_candev(ndev); 1349probe_exit_alloc_candev: 1350 pci_iounmap(pdev, addr); 1351probe_exit_ipmap: 1352 pci_release_regions(pdev); 1353probe_exit_pcireq: 1354 pci_disable_device(pdev); 1355probe_exit_endev: 1356 return rc; 1357} 1358 1359static struct pci_driver pch_can_pci_driver = { 1360 .name = "pch_can", 1361 .id_table = pch_pci_tbl, 1362 .probe = pch_can_probe, 1363 .remove = __devexit_p(pch_can_remove), 1364 .suspend = pch_can_suspend, 1365 .resume = pch_can_resume, 1366}; 1367 1368static int __init pch_can_pci_init(void) 1369{ 1370 return pci_register_driver(&pch_can_pci_driver); 1371} 1372module_init(pch_can_pci_init); 1373 1374static void __exit pch_can_pci_exit(void) 1375{ 1376 pci_unregister_driver(&pch_can_pci_driver); 1377} 1378module_exit(pch_can_pci_exit); 1379 1380MODULE_DESCRIPTION("Controller Area Network Driver"); 1381MODULE_LICENSE("GPL v2"); 1382MODULE_VERSION("0.94"); 1383