pch_can.c revision e489ccebf14657774fd877dc841b458703730586
1/* 2 * Copyright (C) 1999 - 2010 Intel Corporation. 3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19#include <linux/interrupt.h> 20#include <linux/delay.h> 21#include <linux/io.h> 22#include <linux/module.h> 23#include <linux/sched.h> 24#include <linux/pci.h> 25#include <linux/init.h> 26#include <linux/kernel.h> 27#include <linux/types.h> 28#include <linux/errno.h> 29#include <linux/netdevice.h> 30#include <linux/skbuff.h> 31#include <linux/can.h> 32#include <linux/can/dev.h> 33#include <linux/can/error.h> 34 35#define PCH_ENABLE 1 /* The enable flag */ 36#define PCH_DISABLE 0 /* The disable flag */ 37#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */ 38#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */ 39#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1)) 40#define PCH_CTRL_CCE BIT(6) 41#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */ 42#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */ 43#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */ 44 45#define PCH_CMASK_RX_TX_SET 0x00f3 46#define PCH_CMASK_RX_TX_GET 0x0073 47#define PCH_CMASK_ALL 0xff 48#define PCH_CMASK_NEWDAT BIT(2) 49#define PCH_CMASK_CLRINTPND BIT(3) 50#define PCH_CMASK_CTRL BIT(4) 51#define PCH_CMASK_ARB BIT(5) 52#define PCH_CMASK_MASK BIT(6) 53#define PCH_CMASK_RDWR BIT(7) 54#define PCH_IF_MCONT_NEWDAT BIT(15) 55#define PCH_IF_MCONT_MSGLOST BIT(14) 56#define PCH_IF_MCONT_INTPND BIT(13) 57#define PCH_IF_MCONT_UMASK BIT(12) 58#define PCH_IF_MCONT_TXIE BIT(11) 59#define PCH_IF_MCONT_RXIE BIT(10) 60#define PCH_IF_MCONT_RMTEN BIT(9) 61#define PCH_IF_MCONT_TXRQXT BIT(8) 62#define PCH_IF_MCONT_EOB BIT(7) 63#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 64#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15)) 65#define PCH_ID2_DIR BIT(13) 66#define PCH_ID2_XTD BIT(14) 67#define PCH_ID_MSGVAL BIT(15) 68#define PCH_IF_CREQ_BUSY BIT(15) 69 70#define PCH_STATUS_INT 0x8000 71#define PCH_REC 0x00007f00 72#define PCH_TEC 0x000000ff 73 74#define PCH_TX_OK BIT(3) 75#define PCH_RX_OK BIT(4) 76#define PCH_EPASSIV BIT(5) 77#define PCH_EWARN BIT(6) 78#define PCH_BUS_OFF BIT(7) 79 80/* bit position of certain controller bits. */ 81#define PCH_BIT_BRP 0 82#define PCH_BIT_SJW 6 83#define PCH_BIT_TSEG1 8 84#define PCH_BIT_TSEG2 12 85#define PCH_BIT_BRPE_BRPE 6 86#define PCH_MSK_BITT_BRP 0x3f 87#define PCH_MSK_BRPE_BRPE 0x3c0 88#define PCH_MSK_CTRL_IE_SIE_EIE 0x07 89#define PCH_COUNTER_LIMIT 10 90 91#define PCH_CAN_CLK 50000000 /* 50MHz */ 92 93/* Define the number of message object. 94 * PCH CAN communications are done via Message RAM. 95 * The Message RAM consists of 32 message objects. */ 96#define PCH_RX_OBJ_NUM 26 97#define PCH_TX_OBJ_NUM 6 98#define PCH_RX_OBJ_START 1 99#define PCH_RX_OBJ_END PCH_RX_OBJ_NUM 100#define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1) 101#define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM) 102 103#define PCH_FIFO_THRESH 16 104 105/* TxRqst2 show status of MsgObjNo.17~32 */ 106#define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\ 107 (PCH_RX_OBJ_END - 16)) 108 109enum pch_ifreg { 110 PCH_RX_IFREG, 111 PCH_TX_IFREG, 112}; 113 114enum pch_can_err { 115 PCH_STUF_ERR = 1, 116 PCH_FORM_ERR, 117 PCH_ACK_ERR, 118 PCH_BIT1_ERR, 119 PCH_BIT0_ERR, 120 PCH_CRC_ERR, 121 PCH_LEC_ALL, 122}; 123 124enum pch_can_mode { 125 PCH_CAN_ENABLE, 126 PCH_CAN_DISABLE, 127 PCH_CAN_ALL, 128 PCH_CAN_NONE, 129 PCH_CAN_STOP, 130 PCH_CAN_RUN 131}; 132 133struct pch_can_if_regs { 134 u32 creq; 135 u32 cmask; 136 u32 mask1; 137 u32 mask2; 138 u32 id1; 139 u32 id2; 140 u32 mcont; 141 u32 dataa1; 142 u32 dataa2; 143 u32 datab1; 144 u32 datab2; 145 u32 rsv[13]; 146}; 147 148struct pch_can_regs { 149 u32 cont; 150 u32 stat; 151 u32 errc; 152 u32 bitt; 153 u32 intr; 154 u32 opt; 155 u32 brpe; 156 u32 reserve; 157 struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */ 158 u32 reserve1[8]; 159 u32 treq1; 160 u32 treq2; 161 u32 reserve2[6]; 162 u32 data1; 163 u32 data2; 164 u32 reserve3[6]; 165 u32 canipend1; 166 u32 canipend2; 167 u32 reserve4[6]; 168 u32 canmval1; 169 u32 canmval2; 170 u32 reserve5[37]; 171 u32 srst; 172}; 173 174struct pch_can_priv { 175 struct can_priv can; 176 unsigned int can_num; 177 struct pci_dev *dev; 178 int tx_enable[PCH_TX_OBJ_END]; 179 int rx_enable[PCH_TX_OBJ_END]; 180 int rx_link[PCH_TX_OBJ_END]; 181 unsigned int int_enables; 182 unsigned int int_stat; 183 struct net_device *ndev; 184 unsigned int msg_obj[PCH_TX_OBJ_END]; 185 struct pch_can_regs __iomem *regs; 186 struct napi_struct napi; 187 unsigned int tx_obj; /* Point next Tx Obj index */ 188 unsigned int use_msi; 189}; 190 191static struct can_bittiming_const pch_can_bittiming_const = { 192 .name = KBUILD_MODNAME, 193 .tseg1_min = 1, 194 .tseg1_max = 16, 195 .tseg2_min = 1, 196 .tseg2_max = 8, 197 .sjw_max = 4, 198 .brp_min = 1, 199 .brp_max = 1024, /* 6bit + extended 4bit */ 200 .brp_inc = 1, 201}; 202 203static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = { 204 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,}, 205 {0,} 206}; 207MODULE_DEVICE_TABLE(pci, pch_pci_tbl); 208 209static inline void pch_can_bit_set(void __iomem *addr, u32 mask) 210{ 211 iowrite32(ioread32(addr) | mask, addr); 212} 213 214static inline void pch_can_bit_clear(void __iomem *addr, u32 mask) 215{ 216 iowrite32(ioread32(addr) & ~mask, addr); 217} 218 219static void pch_can_set_run_mode(struct pch_can_priv *priv, 220 enum pch_can_mode mode) 221{ 222 switch (mode) { 223 case PCH_CAN_RUN: 224 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT); 225 break; 226 227 case PCH_CAN_STOP: 228 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT); 229 break; 230 231 default: 232 dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__); 233 break; 234 } 235} 236 237static void pch_can_set_optmode(struct pch_can_priv *priv) 238{ 239 u32 reg_val = ioread32(&priv->regs->opt); 240 241 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 242 reg_val |= PCH_OPT_SILENT; 243 244 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 245 reg_val |= PCH_OPT_LBACK; 246 247 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT); 248 iowrite32(reg_val, &priv->regs->opt); 249} 250 251static void pch_can_set_int_custom(struct pch_can_priv *priv) 252{ 253 /* Clearing the IE, SIE and EIE bits of Can control register. */ 254 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 255 256 /* Appropriately setting them. */ 257 pch_can_bit_set(&priv->regs->cont, 258 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1)); 259} 260 261/* This function retrieves interrupt enabled for the CAN device. */ 262static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables) 263{ 264 /* Obtaining the status of IE, SIE and EIE interrupt bits. */ 265 *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1); 266} 267 268static void pch_can_set_int_enables(struct pch_can_priv *priv, 269 enum pch_can_mode interrupt_no) 270{ 271 switch (interrupt_no) { 272 case PCH_CAN_ENABLE: 273 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE); 274 break; 275 276 case PCH_CAN_DISABLE: 277 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE); 278 break; 279 280 case PCH_CAN_ALL: 281 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 282 break; 283 284 case PCH_CAN_NONE: 285 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 286 break; 287 288 default: 289 dev_err(&priv->ndev->dev, "Invalid interrupt number.\n"); 290 break; 291 } 292} 293 294static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num) 295{ 296 u32 counter = PCH_COUNTER_LIMIT; 297 u32 ifx_creq; 298 299 iowrite32(num, creq_addr); 300 while (counter) { 301 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY; 302 if (!ifx_creq) 303 break; 304 counter--; 305 udelay(1); 306 } 307 if (!counter) 308 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__); 309} 310 311static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, 312 u32 set, enum pch_ifreg dir) 313{ 314 u32 ie; 315 316 if (dir) 317 ie = PCH_IF_MCONT_TXIE; 318 else 319 ie = PCH_IF_MCONT_RXIE; 320 321 /* Reading the receive buffer data from RAM to Interface1 registers */ 322 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); 323 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 324 325 /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */ 326 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL, 327 &priv->regs->ifregs[dir].cmask); 328 329 if (set == PCH_ENABLE) { 330 /* Setting the MsgVal and RxIE bits */ 331 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie); 332 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); 333 334 } else if (set == PCH_DISABLE) { 335 /* Resetting the MsgVal and RxIE bits */ 336 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie); 337 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); 338 } 339 340 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 341} 342 343static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set) 344{ 345 int i; 346 347 /* Traversing to obtain the object configured as receivers. */ 348 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) 349 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG); 350} 351 352static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set) 353{ 354 int i; 355 356 /* Traversing to obtain the object configured as transmit object. */ 357 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 358 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG); 359} 360 361static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, 362 enum pch_ifreg dir) 363{ 364 u32 ie, enable; 365 366 if (dir) 367 ie = PCH_IF_MCONT_RXIE; 368 else 369 ie = PCH_IF_MCONT_TXIE; 370 371 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); 372 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num); 373 374 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) && 375 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) { 376 enable = 1; 377 } else { 378 enable = 0; 379 } 380 return enable; 381} 382 383static int pch_can_int_pending(struct pch_can_priv *priv) 384{ 385 return ioread32(&priv->regs->intr) & 0xffff; 386} 387 388static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, 389 u32 buffer_num, u32 set) 390{ 391 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 392 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 393 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, 394 &priv->regs->ifregs[0].cmask); 395 if (set == PCH_ENABLE) 396 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 397 PCH_IF_MCONT_EOB); 398 else 399 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB); 400 401 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 402} 403 404static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv, 405 u32 buffer_num, u32 *link) 406{ 407 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 408 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num); 409 410 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB) 411 *link = PCH_DISABLE; 412 else 413 *link = PCH_ENABLE; 414} 415 416static void pch_can_clear_buffers(struct pch_can_priv *priv) 417{ 418 int i; 419 420 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 421 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask); 422 iowrite32(0xffff, &priv->regs->ifregs[0].mask1); 423 iowrite32(0xffff, &priv->regs->ifregs[0].mask2); 424 iowrite32(0x0, &priv->regs->ifregs[0].id1); 425 iowrite32(0x0, &priv->regs->ifregs[0].id2); 426 iowrite32(0x0, &priv->regs->ifregs[0].mcont); 427 iowrite32(0x0, &priv->regs->ifregs[0].dataa1); 428 iowrite32(0x0, &priv->regs->ifregs[0].dataa2); 429 iowrite32(0x0, &priv->regs->ifregs[0].datab1); 430 iowrite32(0x0, &priv->regs->ifregs[0].datab2); 431 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 432 PCH_CMASK_ARB | PCH_CMASK_CTRL, 433 &priv->regs->ifregs[0].cmask); 434 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 435 } 436 437 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { 438 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[1].cmask); 439 iowrite32(0xffff, &priv->regs->ifregs[1].mask1); 440 iowrite32(0xffff, &priv->regs->ifregs[1].mask2); 441 iowrite32(0x0, &priv->regs->ifregs[1].id1); 442 iowrite32(0x0, &priv->regs->ifregs[1].id2); 443 iowrite32(0x0, &priv->regs->ifregs[1].mcont); 444 iowrite32(0x0, &priv->regs->ifregs[1].dataa1); 445 iowrite32(0x0, &priv->regs->ifregs[1].dataa2); 446 iowrite32(0x0, &priv->regs->ifregs[1].datab1); 447 iowrite32(0x0, &priv->regs->ifregs[1].datab2); 448 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 449 PCH_CMASK_ARB | PCH_CMASK_CTRL, 450 &priv->regs->ifregs[1].cmask); 451 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 452 } 453} 454 455static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) 456{ 457 int i; 458 459 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 460 iowrite32(PCH_CMASK_RX_TX_GET, 461 &priv->regs->ifregs[0].cmask); 462 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 463 464 iowrite32(0x0, &priv->regs->ifregs[0].id1); 465 iowrite32(0x0, &priv->regs->ifregs[0].id2); 466 467 pch_can_bit_set(&priv->regs->ifregs[0].mcont, 468 PCH_IF_MCONT_UMASK); 469 470 /* Set FIFO mode set to 0 except last Rx Obj*/ 471 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 472 PCH_IF_MCONT_EOB); 473 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */ 474 if (i == PCH_RX_OBJ_END) 475 pch_can_bit_set(&priv->regs->ifregs[0].mcont, 476 PCH_IF_MCONT_EOB); 477 478 iowrite32(0, &priv->regs->ifregs[0].mask1); 479 pch_can_bit_clear(&priv->regs->ifregs[0].mask2, 480 0x1fff | PCH_MASK2_MDIR_MXTD); 481 482 /* Setting CMASK for writing */ 483 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 484 PCH_CMASK_ARB | PCH_CMASK_CTRL, 485 &priv->regs->ifregs[0].cmask); 486 487 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i); 488 } 489 490 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { 491 iowrite32(PCH_CMASK_RX_TX_GET, 492 &priv->regs->ifregs[1].cmask); 493 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 494 495 /* Resetting DIR bit for reception */ 496 iowrite32(0x0, &priv->regs->ifregs[1].id1); 497 iowrite32(0x0, &priv->regs->ifregs[1].id2); 498 pch_can_bit_set(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); 499 500 /* Setting EOB bit for transmitter */ 501 iowrite32(PCH_IF_MCONT_EOB, &priv->regs->ifregs[1].mcont); 502 503 pch_can_bit_set(&priv->regs->ifregs[1].mcont, 504 PCH_IF_MCONT_UMASK); 505 506 iowrite32(0, &priv->regs->ifregs[1].mask1); 507 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff); 508 509 /* Setting CMASK for writing */ 510 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 511 PCH_CMASK_ARB | PCH_CMASK_CTRL, 512 &priv->regs->ifregs[1].cmask); 513 514 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i); 515 } 516} 517 518static void pch_can_init(struct pch_can_priv *priv) 519{ 520 /* Stopping the Can device. */ 521 pch_can_set_run_mode(priv, PCH_CAN_STOP); 522 523 /* Clearing all the message object buffers. */ 524 pch_can_clear_buffers(priv); 525 526 /* Configuring the respective message object as either rx/tx object. */ 527 pch_can_config_rx_tx_buffers(priv); 528 529 /* Enabling the interrupts. */ 530 pch_can_set_int_enables(priv, PCH_CAN_ALL); 531} 532 533static void pch_can_release(struct pch_can_priv *priv) 534{ 535 /* Stooping the CAN device. */ 536 pch_can_set_run_mode(priv, PCH_CAN_STOP); 537 538 /* Disabling the interrupts. */ 539 pch_can_set_int_enables(priv, PCH_CAN_NONE); 540 541 /* Disabling all the receive object. */ 542 pch_can_set_rx_all(priv, 0); 543 544 /* Disabling all the transmit object. */ 545 pch_can_set_tx_all(priv, 0); 546} 547 548/* This function clears interrupt(s) from the CAN device. */ 549static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) 550{ 551 if (mask == PCH_STATUS_INT) { 552 ioread32(&priv->regs->stat); 553 return; 554 } 555 556 /* Clear interrupt for transmit object */ 557 if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) { 558 /* Setting CMASK for clearing the reception interrupts. */ 559 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, 560 &priv->regs->ifregs[0].cmask); 561 562 /* Clearing the Dir bit. */ 563 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); 564 565 /* Clearing NewDat & IntPnd */ 566 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 567 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND); 568 569 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, mask); 570 } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) { 571 /* Setting CMASK for clearing interrupts for 572 frame transmission. */ 573 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, 574 &priv->regs->ifregs[1].cmask); 575 576 /* Resetting the ID registers. */ 577 pch_can_bit_set(&priv->regs->ifregs[1].id2, 578 PCH_ID2_DIR | (0x7ff << 2)); 579 iowrite32(0x0, &priv->regs->ifregs[1].id1); 580 581 /* Claring NewDat, TxRqst & IntPnd */ 582 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 583 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | 584 PCH_IF_MCONT_TXRQXT); 585 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, mask); 586 } 587} 588 589static int pch_can_get_buffer_status(struct pch_can_priv *priv) 590{ 591 return (ioread32(&priv->regs->treq1) & 0xffff) | 592 ((ioread32(&priv->regs->treq2) & 0xffff) << 16); 593} 594 595static void pch_can_reset(struct pch_can_priv *priv) 596{ 597 /* write to sw reset register */ 598 iowrite32(1, &priv->regs->srst); 599 iowrite32(0, &priv->regs->srst); 600} 601 602static void pch_can_error(struct net_device *ndev, u32 status) 603{ 604 struct sk_buff *skb; 605 struct pch_can_priv *priv = netdev_priv(ndev); 606 struct can_frame *cf; 607 u32 errc, lec; 608 struct net_device_stats *stats = &(priv->ndev->stats); 609 enum can_state state = priv->can.state; 610 611 skb = alloc_can_err_skb(ndev, &cf); 612 if (!skb) 613 return; 614 615 if (status & PCH_BUS_OFF) { 616 pch_can_set_tx_all(priv, 0); 617 pch_can_set_rx_all(priv, 0); 618 state = CAN_STATE_BUS_OFF; 619 cf->can_id |= CAN_ERR_BUSOFF; 620 can_bus_off(ndev); 621 pch_can_set_run_mode(priv, PCH_CAN_RUN); 622 dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__); 623 } 624 625 /* Warning interrupt. */ 626 if (status & PCH_EWARN) { 627 state = CAN_STATE_ERROR_WARNING; 628 priv->can.can_stats.error_warning++; 629 cf->can_id |= CAN_ERR_CRTL; 630 errc = ioread32(&priv->regs->errc); 631 if (((errc & PCH_REC) >> 8) > 96) 632 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; 633 if ((errc & PCH_TEC) > 96) 634 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; 635 dev_warn(&ndev->dev, 636 "%s -> Error Counter is more than 96.\n", __func__); 637 } 638 /* Error passive interrupt. */ 639 if (status & PCH_EPASSIV) { 640 priv->can.can_stats.error_passive++; 641 state = CAN_STATE_ERROR_PASSIVE; 642 cf->can_id |= CAN_ERR_CRTL; 643 errc = ioread32(&priv->regs->errc); 644 if (((errc & PCH_REC) >> 8) > 127) 645 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 646 if ((errc & PCH_TEC) > 127) 647 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 648 dev_err(&ndev->dev, 649 "%s -> CAN controller is ERROR PASSIVE .\n", __func__); 650 } 651 652 lec = status & PCH_LEC_ALL; 653 switch (lec) { 654 case PCH_STUF_ERR: 655 cf->data[2] |= CAN_ERR_PROT_STUFF; 656 priv->can.can_stats.bus_error++; 657 stats->rx_errors++; 658 break; 659 case PCH_FORM_ERR: 660 cf->data[2] |= CAN_ERR_PROT_FORM; 661 priv->can.can_stats.bus_error++; 662 stats->rx_errors++; 663 break; 664 case PCH_ACK_ERR: 665 cf->can_id |= CAN_ERR_ACK; 666 priv->can.can_stats.bus_error++; 667 stats->rx_errors++; 668 break; 669 case PCH_BIT1_ERR: 670 case PCH_BIT0_ERR: 671 cf->data[2] |= CAN_ERR_PROT_BIT; 672 priv->can.can_stats.bus_error++; 673 stats->rx_errors++; 674 break; 675 case PCH_CRC_ERR: 676 cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ | 677 CAN_ERR_PROT_LOC_CRC_DEL; 678 priv->can.can_stats.bus_error++; 679 stats->rx_errors++; 680 break; 681 case PCH_LEC_ALL: /* Written by CPU. No error status */ 682 break; 683 } 684 685 priv->can.state = state; 686 netif_rx(skb); 687 688 stats->rx_packets++; 689 stats->rx_bytes += cf->can_dlc; 690} 691 692static irqreturn_t pch_can_interrupt(int irq, void *dev_id) 693{ 694 struct net_device *ndev = (struct net_device *)dev_id; 695 struct pch_can_priv *priv = netdev_priv(ndev); 696 697 pch_can_set_int_enables(priv, PCH_CAN_NONE); 698 699 napi_schedule(&priv->napi); 700 701 return IRQ_HANDLED; 702} 703 704static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat) 705{ 706 u32 reg; 707 canid_t id; 708 u32 ide; 709 u32 rtr; 710 int i, j, k; 711 int rcv_pkts = 0; 712 struct sk_buff *skb; 713 struct can_frame *cf; 714 struct pch_can_priv *priv = netdev_priv(ndev); 715 struct net_device_stats *stats = &(priv->ndev->stats); 716 717 /* Reading the messsage object from the Message RAM */ 718 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 719 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, int_stat); 720 721 /* Reading the MCONT register. */ 722 reg = ioread32(&priv->regs->ifregs[0].mcont); 723 reg &= 0xffff; 724 725 for (k = int_stat; !(reg & PCH_IF_MCONT_EOB); k++) { 726 /* If MsgLost bit set. */ 727 if (reg & PCH_IF_MCONT_MSGLOST) { 728 dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n"); 729 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 730 PCH_IF_MCONT_MSGLOST); 731 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, 732 &priv->regs->ifregs[0].cmask); 733 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 734 735 skb = alloc_can_err_skb(ndev, &cf); 736 if (!skb) 737 return -ENOMEM; 738 739 priv->can.can_stats.error_passive++; 740 priv->can.state = CAN_STATE_ERROR_PASSIVE; 741 cf->can_id |= CAN_ERR_CRTL; 742 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; 743 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 744 stats->rx_packets++; 745 stats->rx_bytes += cf->can_dlc; 746 747 netif_receive_skb(skb); 748 rcv_pkts++; 749 goto RX_NEXT; 750 } 751 if (!(reg & PCH_IF_MCONT_NEWDAT)) 752 goto RX_NEXT; 753 754 skb = alloc_can_skb(priv->ndev, &cf); 755 if (!skb) 756 return -ENOMEM; 757 758 /* Get Received data */ 759 ide = ((ioread32(&priv->regs->ifregs[0].id2)) & PCH_ID2_XTD) >> 760 14; 761 if (ide) { 762 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff); 763 id |= (((ioread32(&priv->regs->ifregs[0].id2)) & 764 0x1fff) << 16); 765 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; 766 } else { 767 id = (((ioread32(&priv->regs->ifregs[0].id2)) & 768 (CAN_SFF_MASK << 2)) >> 2); 769 cf->can_id = (id & CAN_SFF_MASK); 770 } 771 772 rtr = (ioread32(&priv->regs->ifregs[0].id2) & PCH_ID2_DIR); 773 if (rtr) { 774 cf->can_dlc = 0; 775 cf->can_id |= CAN_RTR_FLAG; 776 } else { 777 cf->can_dlc = 778 ((ioread32(&priv->regs->ifregs[0].mcont)) & 0x0f); 779 } 780 781 for (i = 0, j = 0; i < cf->can_dlc; j++) { 782 reg = ioread32(&priv->regs->ifregs[0].dataa1 + j*4); 783 cf->data[i++] = cpu_to_le32(reg & 0xff); 784 if (i == cf->can_dlc) 785 break; 786 cf->data[i++] = cpu_to_le32((reg >> 8) & 0xff); 787 } 788 789 netif_receive_skb(skb); 790 rcv_pkts++; 791 stats->rx_packets++; 792 stats->rx_bytes += cf->can_dlc; 793 794 if (k < PCH_FIFO_THRESH) { 795 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | 796 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask); 797 798 /* Clearing the Dir bit. */ 799 pch_can_bit_clear(&priv->regs->ifregs[0].id2, 800 PCH_ID2_DIR); 801 802 /* Clearing NewDat & IntPnd */ 803 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 804 PCH_IF_MCONT_INTPND); 805 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 806 } else if (k > PCH_FIFO_THRESH) { 807 pch_can_int_clr(priv, k); 808 } else if (k == PCH_FIFO_THRESH) { 809 int cnt; 810 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++) 811 pch_can_int_clr(priv, cnt+1); 812 } 813RX_NEXT: 814 /* Reading the messsage object from the Message RAM */ 815 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 816 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k); 817 reg = ioread32(&priv->regs->ifregs[0].mcont); 818 } 819 820 return rcv_pkts; 821} 822 823static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat) 824{ 825 struct pch_can_priv *priv = netdev_priv(ndev); 826 struct net_device_stats *stats = &(priv->ndev->stats); 827 u32 dlc; 828 829 can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1); 830 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND, 831 &priv->regs->ifregs[1].cmask); 832 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat); 833 dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) & 834 PCH_IF_MCONT_DLC); 835 stats->tx_bytes += dlc; 836 stats->tx_packets++; 837 if (int_stat == PCH_TX_OBJ_END) 838 netif_wake_queue(ndev); 839} 840 841static int pch_can_rx_poll(struct napi_struct *napi, int quota) 842{ 843 struct net_device *ndev = napi->dev; 844 struct pch_can_priv *priv = netdev_priv(ndev); 845 u32 int_stat; 846 int rcv_pkts = 0; 847 u32 reg_stat; 848 849 int_stat = pch_can_int_pending(priv); 850 if (!int_stat) 851 goto end; 852 853 if ((int_stat == PCH_STATUS_INT) && (quota > 0)) { 854 reg_stat = ioread32(&priv->regs->stat); 855 if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) { 856 if (reg_stat & PCH_BUS_OFF || 857 (reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) { 858 pch_can_error(ndev, reg_stat); 859 quota--; 860 } 861 } 862 863 if (reg_stat & PCH_TX_OK) 864 pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK); 865 866 if (reg_stat & PCH_RX_OK) 867 pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK); 868 869 int_stat = pch_can_int_pending(priv); 870 } 871 872 if (quota == 0) 873 goto end; 874 875 if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) { 876 rcv_pkts += pch_can_rx_normal(ndev, int_stat); 877 quota -= rcv_pkts; 878 if (quota < 0) 879 goto end; 880 } else if ((int_stat >= PCH_TX_OBJ_START) && 881 (int_stat <= PCH_TX_OBJ_END)) { 882 /* Handle transmission interrupt */ 883 pch_can_tx_complete(ndev, int_stat); 884 } 885 886end: 887 napi_complete(napi); 888 pch_can_set_int_enables(priv, PCH_CAN_ALL); 889 890 return rcv_pkts; 891} 892 893static int pch_set_bittiming(struct net_device *ndev) 894{ 895 struct pch_can_priv *priv = netdev_priv(ndev); 896 const struct can_bittiming *bt = &priv->can.bittiming; 897 u32 canbit; 898 u32 bepe; 899 u32 brp; 900 901 /* Setting the CCE bit for accessing the Can Timing register. */ 902 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE); 903 904 brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1; 905 canbit = brp & PCH_MSK_BITT_BRP; 906 canbit |= (bt->sjw - 1) << PCH_BIT_SJW; 907 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1; 908 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2; 909 bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE; 910 iowrite32(canbit, &priv->regs->bitt); 911 iowrite32(bepe, &priv->regs->brpe); 912 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE); 913 914 return 0; 915} 916 917static void pch_can_start(struct net_device *ndev) 918{ 919 struct pch_can_priv *priv = netdev_priv(ndev); 920 921 if (priv->can.state != CAN_STATE_STOPPED) 922 pch_can_reset(priv); 923 924 pch_set_bittiming(ndev); 925 pch_can_set_optmode(priv); 926 927 pch_can_set_tx_all(priv, 1); 928 pch_can_set_rx_all(priv, 1); 929 930 /* Setting the CAN to run mode. */ 931 pch_can_set_run_mode(priv, PCH_CAN_RUN); 932 933 priv->can.state = CAN_STATE_ERROR_ACTIVE; 934 935 return; 936} 937 938static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 939{ 940 int ret = 0; 941 942 switch (mode) { 943 case CAN_MODE_START: 944 pch_can_start(ndev); 945 netif_wake_queue(ndev); 946 break; 947 default: 948 ret = -EOPNOTSUPP; 949 break; 950 } 951 952 return ret; 953} 954 955static int pch_can_open(struct net_device *ndev) 956{ 957 struct pch_can_priv *priv = netdev_priv(ndev); 958 int retval; 959 960 retval = pci_enable_msi(priv->dev); 961 if (retval) { 962 dev_info(&ndev->dev, "PCH CAN opened without MSI\n"); 963 priv->use_msi = 0; 964 } else { 965 dev_info(&ndev->dev, "PCH CAN opened with MSI\n"); 966 priv->use_msi = 1; 967 } 968 969 /* Regsitering the interrupt. */ 970 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED, 971 ndev->name, ndev); 972 if (retval) { 973 dev_err(&ndev->dev, "request_irq failed.\n"); 974 goto req_irq_err; 975 } 976 977 /* Open common can device */ 978 retval = open_candev(ndev); 979 if (retval) { 980 dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval); 981 goto err_open_candev; 982 } 983 984 pch_can_init(priv); 985 pch_can_start(ndev); 986 napi_enable(&priv->napi); 987 netif_start_queue(ndev); 988 989 return 0; 990 991err_open_candev: 992 free_irq(priv->dev->irq, ndev); 993req_irq_err: 994 if (priv->use_msi) 995 pci_disable_msi(priv->dev); 996 997 pch_can_release(priv); 998 999 return retval; 1000} 1001 1002static int pch_close(struct net_device *ndev) 1003{ 1004 struct pch_can_priv *priv = netdev_priv(ndev); 1005 1006 netif_stop_queue(ndev); 1007 napi_disable(&priv->napi); 1008 pch_can_release(priv); 1009 free_irq(priv->dev->irq, ndev); 1010 if (priv->use_msi) 1011 pci_disable_msi(priv->dev); 1012 close_candev(ndev); 1013 priv->can.state = CAN_STATE_STOPPED; 1014 return 0; 1015} 1016 1017static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) 1018{ 1019 int i, j; 1020 struct pch_can_priv *priv = netdev_priv(ndev); 1021 struct can_frame *cf = (struct can_frame *)skb->data; 1022 int tx_buffer_avail = 0; 1023 1024 if (can_dropped_invalid_skb(ndev, skb)) 1025 return NETDEV_TX_OK; 1026 1027 if (priv->tx_obj == PCH_TX_OBJ_END) { 1028 if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK) 1029 netif_stop_queue(ndev); 1030 1031 tx_buffer_avail = priv->tx_obj; 1032 priv->tx_obj = PCH_TX_OBJ_START; 1033 } else { 1034 tx_buffer_avail = priv->tx_obj; 1035 priv->tx_obj++; 1036 } 1037 1038 /* Reading the Msg Obj from the Msg RAM to the Interface register. */ 1039 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); 1040 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); 1041 1042 /* Setting the CMASK register. */ 1043 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL); 1044 1045 /* If ID extended is set. */ 1046 pch_can_bit_clear(&priv->regs->ifregs[1].id1, 0xffff); 1047 pch_can_bit_clear(&priv->regs->ifregs[1].id2, 0x1fff | PCH_ID2_XTD); 1048 if (cf->can_id & CAN_EFF_FLAG) { 1049 pch_can_bit_set(&priv->regs->ifregs[1].id1, 1050 cf->can_id & 0xffff); 1051 pch_can_bit_set(&priv->regs->ifregs[1].id2, 1052 ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD); 1053 } else { 1054 pch_can_bit_set(&priv->regs->ifregs[1].id1, 0); 1055 pch_can_bit_set(&priv->regs->ifregs[1].id2, 1056 (cf->can_id & CAN_SFF_MASK) << 2); 1057 } 1058 1059 /* If remote frame has to be transmitted.. */ 1060 if (cf->can_id & CAN_RTR_FLAG) 1061 pch_can_bit_clear(&priv->regs->ifregs[1].id2, PCH_ID2_DIR); 1062 1063 for (i = 0, j = 0; i < cf->can_dlc; j++) { 1064 iowrite32(le32_to_cpu(cf->data[i++]), 1065 (&priv->regs->ifregs[1].dataa1) + j*4); 1066 if (i == cf->can_dlc) 1067 break; 1068 iowrite32(le32_to_cpu(cf->data[i++] << 8), 1069 (&priv->regs->ifregs[1].dataa1) + j*4); 1070 } 1071 1072 can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_END - 1); 1073 1074 /* Updating the size of the data. */ 1075 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 0x0f); 1076 pch_can_bit_set(&priv->regs->ifregs[1].mcont, cf->can_dlc); 1077 1078 /* Clearing IntPend, NewDat & TxRqst */ 1079 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 1080 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | 1081 PCH_IF_MCONT_TXRQXT); 1082 1083 /* Setting NewDat, TxRqst bits */ 1084 pch_can_bit_set(&priv->regs->ifregs[1].mcont, 1085 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT); 1086 1087 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail); 1088 1089 return NETDEV_TX_OK; 1090} 1091 1092static const struct net_device_ops pch_can_netdev_ops = { 1093 .ndo_open = pch_can_open, 1094 .ndo_stop = pch_close, 1095 .ndo_start_xmit = pch_xmit, 1096}; 1097 1098static void __devexit pch_can_remove(struct pci_dev *pdev) 1099{ 1100 struct net_device *ndev = pci_get_drvdata(pdev); 1101 struct pch_can_priv *priv = netdev_priv(ndev); 1102 1103 unregister_candev(priv->ndev); 1104 free_candev(priv->ndev); 1105 pci_iounmap(pdev, priv->regs); 1106 pci_release_regions(pdev); 1107 pci_disable_device(pdev); 1108 pci_set_drvdata(pdev, NULL); 1109 pch_can_reset(priv); 1110} 1111 1112#ifdef CONFIG_PM 1113static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state) 1114{ 1115 int i; /* Counter variable. */ 1116 int retval; /* Return value. */ 1117 u32 buf_stat; /* Variable for reading the transmit buffer status. */ 1118 u32 counter = 0xFFFFFF; 1119 1120 struct net_device *dev = pci_get_drvdata(pdev); 1121 struct pch_can_priv *priv = netdev_priv(dev); 1122 1123 /* Stop the CAN controller */ 1124 pch_can_set_run_mode(priv, PCH_CAN_STOP); 1125 1126 /* Indicate that we are aboutto/in suspend */ 1127 priv->can.state = CAN_STATE_SLEEPING; 1128 1129 /* Waiting for all transmission to complete. */ 1130 while (counter) { 1131 buf_stat = pch_can_get_buffer_status(priv); 1132 if (!buf_stat) 1133 break; 1134 counter--; 1135 udelay(1); 1136 } 1137 if (!counter) 1138 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__); 1139 1140 /* Save interrupt configuration and then disable them */ 1141 pch_can_get_int_enables(priv, &(priv->int_enables)); 1142 pch_can_set_int_enables(priv, PCH_CAN_DISABLE); 1143 1144 /* Save Tx buffer enable state */ 1145 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 1146 priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_TX_IFREG); 1147 1148 /* Disable all Transmit buffers */ 1149 pch_can_set_tx_all(priv, 0); 1150 1151 /* Save Rx buffer enable state */ 1152 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 1153 priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG); 1154 pch_can_get_rx_buffer_link(priv, i, &priv->rx_link[i]); 1155 } 1156 1157 /* Disable all Receive buffers */ 1158 pch_can_set_rx_all(priv, 0); 1159 retval = pci_save_state(pdev); 1160 if (retval) { 1161 dev_err(&pdev->dev, "pci_save_state failed.\n"); 1162 } else { 1163 pci_enable_wake(pdev, PCI_D3hot, 0); 1164 pci_disable_device(pdev); 1165 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1166 } 1167 1168 return retval; 1169} 1170 1171static int pch_can_resume(struct pci_dev *pdev) 1172{ 1173 int i; /* Counter variable. */ 1174 int retval; /* Return variable. */ 1175 struct net_device *dev = pci_get_drvdata(pdev); 1176 struct pch_can_priv *priv = netdev_priv(dev); 1177 1178 pci_set_power_state(pdev, PCI_D0); 1179 pci_restore_state(pdev); 1180 retval = pci_enable_device(pdev); 1181 if (retval) { 1182 dev_err(&pdev->dev, "pci_enable_device failed.\n"); 1183 return retval; 1184 } 1185 1186 pci_enable_wake(pdev, PCI_D3hot, 0); 1187 1188 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1189 1190 /* Disabling all interrupts. */ 1191 pch_can_set_int_enables(priv, PCH_CAN_DISABLE); 1192 1193 /* Setting the CAN device in Stop Mode. */ 1194 pch_can_set_run_mode(priv, PCH_CAN_STOP); 1195 1196 /* Configuring the transmit and receive buffers. */ 1197 pch_can_config_rx_tx_buffers(priv); 1198 1199 /* Restore the CAN state */ 1200 pch_set_bittiming(dev); 1201 1202 /* Listen/Active */ 1203 pch_can_set_optmode(priv); 1204 1205 /* Enabling the transmit buffer. */ 1206 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 1207 pch_can_set_rxtx(priv, i, priv->tx_enable[i], PCH_TX_IFREG); 1208 1209 /* Configuring the receive buffer and enabling them. */ 1210 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 1211 /* Restore buffer link */ 1212 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]); 1213 1214 /* Restore buffer enables */ 1215 pch_can_set_rxtx(priv, i, priv->rx_enable[i], PCH_RX_IFREG); 1216 } 1217 1218 /* Enable CAN Interrupts */ 1219 pch_can_set_int_custom(priv); 1220 1221 /* Restore Run Mode */ 1222 pch_can_set_run_mode(priv, PCH_CAN_RUN); 1223 1224 return retval; 1225} 1226#else 1227#define pch_can_suspend NULL 1228#define pch_can_resume NULL 1229#endif 1230 1231static int pch_can_get_berr_counter(const struct net_device *dev, 1232 struct can_berr_counter *bec) 1233{ 1234 struct pch_can_priv *priv = netdev_priv(dev); 1235 1236 bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC; 1237 bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8; 1238 1239 return 0; 1240} 1241 1242static int __devinit pch_can_probe(struct pci_dev *pdev, 1243 const struct pci_device_id *id) 1244{ 1245 struct net_device *ndev; 1246 struct pch_can_priv *priv; 1247 int rc; 1248 void __iomem *addr; 1249 1250 rc = pci_enable_device(pdev); 1251 if (rc) { 1252 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc); 1253 goto probe_exit_endev; 1254 } 1255 1256 rc = pci_request_regions(pdev, KBUILD_MODNAME); 1257 if (rc) { 1258 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc); 1259 goto probe_exit_pcireq; 1260 } 1261 1262 addr = pci_iomap(pdev, 1, 0); 1263 if (!addr) { 1264 rc = -EIO; 1265 dev_err(&pdev->dev, "Failed pci_iomap\n"); 1266 goto probe_exit_ipmap; 1267 } 1268 1269 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END); 1270 if (!ndev) { 1271 rc = -ENOMEM; 1272 dev_err(&pdev->dev, "Failed alloc_candev\n"); 1273 goto probe_exit_alloc_candev; 1274 } 1275 1276 priv = netdev_priv(ndev); 1277 priv->ndev = ndev; 1278 priv->regs = addr; 1279 priv->dev = pdev; 1280 priv->can.bittiming_const = &pch_can_bittiming_const; 1281 priv->can.do_set_mode = pch_can_do_set_mode; 1282 priv->can.do_get_berr_counter = pch_can_get_berr_counter; 1283 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | 1284 CAN_CTRLMODE_LOOPBACK; 1285 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */ 1286 1287 ndev->irq = pdev->irq; 1288 ndev->flags |= IFF_ECHO; 1289 1290 pci_set_drvdata(pdev, ndev); 1291 SET_NETDEV_DEV(ndev, &pdev->dev); 1292 ndev->netdev_ops = &pch_can_netdev_ops; 1293 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */ 1294 1295 netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_END); 1296 1297 rc = register_candev(ndev); 1298 if (rc) { 1299 dev_err(&pdev->dev, "Failed register_candev %d\n", rc); 1300 goto probe_exit_reg_candev; 1301 } 1302 1303 return 0; 1304 1305probe_exit_reg_candev: 1306 free_candev(ndev); 1307probe_exit_alloc_candev: 1308 pci_iounmap(pdev, addr); 1309probe_exit_ipmap: 1310 pci_release_regions(pdev); 1311probe_exit_pcireq: 1312 pci_disable_device(pdev); 1313probe_exit_endev: 1314 return rc; 1315} 1316 1317static struct pci_driver pch_can_pci_driver = { 1318 .name = "pch_can", 1319 .id_table = pch_pci_tbl, 1320 .probe = pch_can_probe, 1321 .remove = __devexit_p(pch_can_remove), 1322 .suspend = pch_can_suspend, 1323 .resume = pch_can_resume, 1324}; 1325 1326static int __init pch_can_pci_init(void) 1327{ 1328 return pci_register_driver(&pch_can_pci_driver); 1329} 1330module_init(pch_can_pci_init); 1331 1332static void __exit pch_can_pci_exit(void) 1333{ 1334 pci_unregister_driver(&pch_can_pci_driver); 1335} 1336module_exit(pch_can_pci_exit); 1337 1338MODULE_DESCRIPTION("Controller Area Network Driver"); 1339MODULE_LICENSE("GPL v2"); 1340MODULE_VERSION("0.94"); 1341