pch_can.c revision ee50e135aeb048b90fab662e661c58b67341830b
1/* 2 * Copyright (C) 1999 - 2010 Intel Corporation. 3 * Copyright (C) 2010 LAPIS SEMICONDUCTOR CO., LTD. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19#include <linux/interrupt.h> 20#include <linux/delay.h> 21#include <linux/io.h> 22#include <linux/module.h> 23#include <linux/sched.h> 24#include <linux/pci.h> 25#include <linux/init.h> 26#include <linux/kernel.h> 27#include <linux/types.h> 28#include <linux/errno.h> 29#include <linux/netdevice.h> 30#include <linux/skbuff.h> 31#include <linux/can.h> 32#include <linux/can/dev.h> 33#include <linux/can/error.h> 34 35#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */ 36#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */ 37#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1)) 38#define PCH_CTRL_CCE BIT(6) 39#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */ 40#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */ 41#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */ 42 43#define PCH_CMASK_RX_TX_SET 0x00f3 44#define PCH_CMASK_RX_TX_GET 0x0073 45#define PCH_CMASK_ALL 0xff 46#define PCH_CMASK_NEWDAT BIT(2) 47#define PCH_CMASK_CLRINTPND BIT(3) 48#define PCH_CMASK_CTRL BIT(4) 49#define PCH_CMASK_ARB BIT(5) 50#define PCH_CMASK_MASK BIT(6) 51#define PCH_CMASK_RDWR BIT(7) 52#define PCH_IF_MCONT_NEWDAT BIT(15) 53#define PCH_IF_MCONT_MSGLOST BIT(14) 54#define PCH_IF_MCONT_INTPND BIT(13) 55#define PCH_IF_MCONT_UMASK BIT(12) 56#define PCH_IF_MCONT_TXIE BIT(11) 57#define PCH_IF_MCONT_RXIE BIT(10) 58#define PCH_IF_MCONT_RMTEN BIT(9) 59#define PCH_IF_MCONT_TXRQXT BIT(8) 60#define PCH_IF_MCONT_EOB BIT(7) 61#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 62#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15)) 63#define PCH_ID2_DIR BIT(13) 64#define PCH_ID2_XTD BIT(14) 65#define PCH_ID_MSGVAL BIT(15) 66#define PCH_IF_CREQ_BUSY BIT(15) 67 68#define PCH_STATUS_INT 0x8000 69#define PCH_RP 0x00008000 70#define PCH_REC 0x00007f00 71#define PCH_TEC 0x000000ff 72 73#define PCH_TX_OK BIT(3) 74#define PCH_RX_OK BIT(4) 75#define PCH_EPASSIV BIT(5) 76#define PCH_EWARN BIT(6) 77#define PCH_BUS_OFF BIT(7) 78 79/* bit position of certain controller bits. */ 80#define PCH_BIT_BRP_SHIFT 0 81#define PCH_BIT_SJW_SHIFT 6 82#define PCH_BIT_TSEG1_SHIFT 8 83#define PCH_BIT_TSEG2_SHIFT 12 84#define PCH_BIT_BRPE_BRPE_SHIFT 6 85 86#define PCH_MSK_BITT_BRP 0x3f 87#define PCH_MSK_BRPE_BRPE 0x3c0 88#define PCH_MSK_CTRL_IE_SIE_EIE 0x07 89#define PCH_COUNTER_LIMIT 10 90 91#define PCH_CAN_CLK 50000000 /* 50MHz */ 92 93/* 94 * Define the number of message object. 95 * PCH CAN communications are done via Message RAM. 96 * The Message RAM consists of 32 message objects. 97 */ 98#define PCH_RX_OBJ_NUM 26 99#define PCH_TX_OBJ_NUM 6 100#define PCH_RX_OBJ_START 1 101#define PCH_RX_OBJ_END PCH_RX_OBJ_NUM 102#define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1) 103#define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM) 104 105#define PCH_FIFO_THRESH 16 106 107/* TxRqst2 show status of MsgObjNo.17~32 */ 108#define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\ 109 (PCH_RX_OBJ_END - 16)) 110 111enum pch_ifreg { 112 PCH_RX_IFREG, 113 PCH_TX_IFREG, 114}; 115 116enum pch_can_err { 117 PCH_STUF_ERR = 1, 118 PCH_FORM_ERR, 119 PCH_ACK_ERR, 120 PCH_BIT1_ERR, 121 PCH_BIT0_ERR, 122 PCH_CRC_ERR, 123 PCH_LEC_ALL, 124}; 125 126enum pch_can_mode { 127 PCH_CAN_ENABLE, 128 PCH_CAN_DISABLE, 129 PCH_CAN_ALL, 130 PCH_CAN_NONE, 131 PCH_CAN_STOP, 132 PCH_CAN_RUN, 133}; 134 135struct pch_can_if_regs { 136 u32 creq; 137 u32 cmask; 138 u32 mask1; 139 u32 mask2; 140 u32 id1; 141 u32 id2; 142 u32 mcont; 143 u32 data[4]; 144 u32 rsv[13]; 145}; 146 147struct pch_can_regs { 148 u32 cont; 149 u32 stat; 150 u32 errc; 151 u32 bitt; 152 u32 intr; 153 u32 opt; 154 u32 brpe; 155 u32 reserve; 156 struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */ 157 u32 reserve1[8]; 158 u32 treq1; 159 u32 treq2; 160 u32 reserve2[6]; 161 u32 data1; 162 u32 data2; 163 u32 reserve3[6]; 164 u32 canipend1; 165 u32 canipend2; 166 u32 reserve4[6]; 167 u32 canmval1; 168 u32 canmval2; 169 u32 reserve5[37]; 170 u32 srst; 171}; 172 173struct pch_can_priv { 174 struct can_priv can; 175 struct pci_dev *dev; 176 u32 tx_enable[PCH_TX_OBJ_END]; 177 u32 rx_enable[PCH_TX_OBJ_END]; 178 u32 rx_link[PCH_TX_OBJ_END]; 179 u32 int_enables; 180 struct net_device *ndev; 181 struct pch_can_regs __iomem *regs; 182 struct napi_struct napi; 183 int tx_obj; /* Point next Tx Obj index */ 184 int use_msi; 185}; 186 187static const struct can_bittiming_const pch_can_bittiming_const = { 188 .name = KBUILD_MODNAME, 189 .tseg1_min = 2, 190 .tseg1_max = 16, 191 .tseg2_min = 1, 192 .tseg2_max = 8, 193 .sjw_max = 4, 194 .brp_min = 1, 195 .brp_max = 1024, /* 6bit + extended 4bit */ 196 .brp_inc = 1, 197}; 198 199static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = { 200 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,}, 201 {0,} 202}; 203MODULE_DEVICE_TABLE(pci, pch_pci_tbl); 204 205static inline void pch_can_bit_set(void __iomem *addr, u32 mask) 206{ 207 iowrite32(ioread32(addr) | mask, addr); 208} 209 210static inline void pch_can_bit_clear(void __iomem *addr, u32 mask) 211{ 212 iowrite32(ioread32(addr) & ~mask, addr); 213} 214 215static void pch_can_set_run_mode(struct pch_can_priv *priv, 216 enum pch_can_mode mode) 217{ 218 switch (mode) { 219 case PCH_CAN_RUN: 220 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT); 221 break; 222 223 case PCH_CAN_STOP: 224 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT); 225 break; 226 227 default: 228 netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__); 229 break; 230 } 231} 232 233static void pch_can_set_optmode(struct pch_can_priv *priv) 234{ 235 u32 reg_val = ioread32(&priv->regs->opt); 236 237 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 238 reg_val |= PCH_OPT_SILENT; 239 240 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 241 reg_val |= PCH_OPT_LBACK; 242 243 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT); 244 iowrite32(reg_val, &priv->regs->opt); 245} 246 247static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num) 248{ 249 int counter = PCH_COUNTER_LIMIT; 250 u32 ifx_creq; 251 252 iowrite32(num, creq_addr); 253 while (counter) { 254 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY; 255 if (!ifx_creq) 256 break; 257 counter--; 258 udelay(1); 259 } 260 if (!counter) 261 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__); 262} 263 264static void pch_can_set_int_enables(struct pch_can_priv *priv, 265 enum pch_can_mode interrupt_no) 266{ 267 switch (interrupt_no) { 268 case PCH_CAN_DISABLE: 269 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE); 270 break; 271 272 case PCH_CAN_ALL: 273 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 274 break; 275 276 case PCH_CAN_NONE: 277 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 278 break; 279 280 default: 281 netdev_err(priv->ndev, "Invalid interrupt number.\n"); 282 break; 283 } 284} 285 286static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num, 287 int set, enum pch_ifreg dir) 288{ 289 u32 ie; 290 291 if (dir) 292 ie = PCH_IF_MCONT_TXIE; 293 else 294 ie = PCH_IF_MCONT_RXIE; 295 296 /* Reading the Msg buffer from Message RAM to IF1/2 registers. */ 297 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); 298 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num); 299 300 /* Setting the IF1/2MASK1 register to access MsgVal and RxIE bits */ 301 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL, 302 &priv->regs->ifregs[dir].cmask); 303 304 if (set) { 305 /* Setting the MsgVal and RxIE/TxIE bits */ 306 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie); 307 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); 308 } else { 309 /* Clearing the MsgVal and RxIE/TxIE bits */ 310 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie); 311 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL); 312 } 313 314 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num); 315} 316 317static void pch_can_set_rx_all(struct pch_can_priv *priv, int set) 318{ 319 int i; 320 321 /* Traversing to obtain the object configured as receivers. */ 322 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) 323 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG); 324} 325 326static void pch_can_set_tx_all(struct pch_can_priv *priv, int set) 327{ 328 int i; 329 330 /* Traversing to obtain the object configured as transmit object. */ 331 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 332 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG); 333} 334 335static u32 pch_can_int_pending(struct pch_can_priv *priv) 336{ 337 return ioread32(&priv->regs->intr) & 0xffff; 338} 339 340static void pch_can_clear_if_buffers(struct pch_can_priv *priv) 341{ 342 int i; /* Msg Obj ID (1~32) */ 343 344 for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { 345 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask); 346 iowrite32(0xffff, &priv->regs->ifregs[0].mask1); 347 iowrite32(0xffff, &priv->regs->ifregs[0].mask2); 348 iowrite32(0x0, &priv->regs->ifregs[0].id1); 349 iowrite32(0x0, &priv->regs->ifregs[0].id2); 350 iowrite32(0x0, &priv->regs->ifregs[0].mcont); 351 iowrite32(0x0, &priv->regs->ifregs[0].data[0]); 352 iowrite32(0x0, &priv->regs->ifregs[0].data[1]); 353 iowrite32(0x0, &priv->regs->ifregs[0].data[2]); 354 iowrite32(0x0, &priv->regs->ifregs[0].data[3]); 355 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | 356 PCH_CMASK_ARB | PCH_CMASK_CTRL, 357 &priv->regs->ifregs[0].cmask); 358 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i); 359 } 360} 361 362static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) 363{ 364 int i; 365 366 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 367 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 368 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i); 369 370 iowrite32(0x0, &priv->regs->ifregs[0].id1); 371 iowrite32(0x0, &priv->regs->ifregs[0].id2); 372 373 pch_can_bit_set(&priv->regs->ifregs[0].mcont, 374 PCH_IF_MCONT_UMASK); 375 376 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */ 377 if (i == PCH_RX_OBJ_END) 378 pch_can_bit_set(&priv->regs->ifregs[0].mcont, 379 PCH_IF_MCONT_EOB); 380 else 381 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 382 PCH_IF_MCONT_EOB); 383 384 iowrite32(0, &priv->regs->ifregs[0].mask1); 385 pch_can_bit_clear(&priv->regs->ifregs[0].mask2, 386 0x1fff | PCH_MASK2_MDIR_MXTD); 387 388 /* Setting CMASK for writing */ 389 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB | 390 PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask); 391 392 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i); 393 } 394 395 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) { 396 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); 397 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i); 398 399 /* Resetting DIR bit for reception */ 400 iowrite32(0x0, &priv->regs->ifregs[1].id1); 401 iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2); 402 403 /* Setting EOB bit for transmitter */ 404 iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK, 405 &priv->regs->ifregs[1].mcont); 406 407 iowrite32(0, &priv->regs->ifregs[1].mask1); 408 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff); 409 410 /* Setting CMASK for writing */ 411 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB | 412 PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask); 413 414 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i); 415 } 416} 417 418static void pch_can_init(struct pch_can_priv *priv) 419{ 420 /* Stopping the Can device. */ 421 pch_can_set_run_mode(priv, PCH_CAN_STOP); 422 423 /* Clearing all the message object buffers. */ 424 pch_can_clear_if_buffers(priv); 425 426 /* Configuring the respective message object as either rx/tx object. */ 427 pch_can_config_rx_tx_buffers(priv); 428 429 /* Enabling the interrupts. */ 430 pch_can_set_int_enables(priv, PCH_CAN_ALL); 431} 432 433static void pch_can_release(struct pch_can_priv *priv) 434{ 435 /* Stooping the CAN device. */ 436 pch_can_set_run_mode(priv, PCH_CAN_STOP); 437 438 /* Disabling the interrupts. */ 439 pch_can_set_int_enables(priv, PCH_CAN_NONE); 440 441 /* Disabling all the receive object. */ 442 pch_can_set_rx_all(priv, 0); 443 444 /* Disabling all the transmit object. */ 445 pch_can_set_tx_all(priv, 0); 446} 447 448/* This function clears interrupt(s) from the CAN device. */ 449static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) 450{ 451 /* Clear interrupt for transmit object */ 452 if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) { 453 /* Setting CMASK for clearing the reception interrupts. */ 454 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, 455 &priv->regs->ifregs[0].cmask); 456 457 /* Clearing the Dir bit. */ 458 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); 459 460 /* Clearing NewDat & IntPnd */ 461 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 462 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND); 463 464 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask); 465 } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) { 466 /* 467 * Setting CMASK for clearing interrupts for frame transmission. 468 */ 469 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB, 470 &priv->regs->ifregs[1].cmask); 471 472 /* Resetting the ID registers. */ 473 pch_can_bit_set(&priv->regs->ifregs[1].id2, 474 PCH_ID2_DIR | (0x7ff << 2)); 475 iowrite32(0x0, &priv->regs->ifregs[1].id1); 476 477 /* Claring NewDat, TxRqst & IntPnd */ 478 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 479 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND | 480 PCH_IF_MCONT_TXRQXT); 481 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask); 482 } 483} 484 485static void pch_can_reset(struct pch_can_priv *priv) 486{ 487 /* write to sw reset register */ 488 iowrite32(1, &priv->regs->srst); 489 iowrite32(0, &priv->regs->srst); 490} 491 492static void pch_can_error(struct net_device *ndev, u32 status) 493{ 494 struct sk_buff *skb; 495 struct pch_can_priv *priv = netdev_priv(ndev); 496 struct can_frame *cf; 497 u32 errc, lec; 498 struct net_device_stats *stats = &(priv->ndev->stats); 499 enum can_state state = priv->can.state; 500 501 skb = alloc_can_err_skb(ndev, &cf); 502 if (!skb) 503 return; 504 505 if (status & PCH_BUS_OFF) { 506 pch_can_set_tx_all(priv, 0); 507 pch_can_set_rx_all(priv, 0); 508 state = CAN_STATE_BUS_OFF; 509 cf->can_id |= CAN_ERR_BUSOFF; 510 can_bus_off(ndev); 511 } 512 513 errc = ioread32(&priv->regs->errc); 514 /* Warning interrupt. */ 515 if (status & PCH_EWARN) { 516 state = CAN_STATE_ERROR_WARNING; 517 priv->can.can_stats.error_warning++; 518 cf->can_id |= CAN_ERR_CRTL; 519 if (((errc & PCH_REC) >> 8) > 96) 520 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; 521 if ((errc & PCH_TEC) > 96) 522 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; 523 netdev_dbg(ndev, 524 "%s -> Error Counter is more than 96.\n", __func__); 525 } 526 /* Error passive interrupt. */ 527 if (status & PCH_EPASSIV) { 528 priv->can.can_stats.error_passive++; 529 state = CAN_STATE_ERROR_PASSIVE; 530 cf->can_id |= CAN_ERR_CRTL; 531 if (errc & PCH_RP) 532 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 533 if ((errc & PCH_TEC) > 127) 534 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 535 netdev_dbg(ndev, 536 "%s -> CAN controller is ERROR PASSIVE .\n", __func__); 537 } 538 539 lec = status & PCH_LEC_ALL; 540 switch (lec) { 541 case PCH_STUF_ERR: 542 cf->data[2] |= CAN_ERR_PROT_STUFF; 543 priv->can.can_stats.bus_error++; 544 stats->rx_errors++; 545 break; 546 case PCH_FORM_ERR: 547 cf->data[2] |= CAN_ERR_PROT_FORM; 548 priv->can.can_stats.bus_error++; 549 stats->rx_errors++; 550 break; 551 case PCH_ACK_ERR: 552 cf->can_id |= CAN_ERR_ACK; 553 priv->can.can_stats.bus_error++; 554 stats->rx_errors++; 555 break; 556 case PCH_BIT1_ERR: 557 case PCH_BIT0_ERR: 558 cf->data[2] |= CAN_ERR_PROT_BIT; 559 priv->can.can_stats.bus_error++; 560 stats->rx_errors++; 561 break; 562 case PCH_CRC_ERR: 563 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ | 564 CAN_ERR_PROT_LOC_CRC_DEL; 565 priv->can.can_stats.bus_error++; 566 stats->rx_errors++; 567 break; 568 case PCH_LEC_ALL: /* Written by CPU. No error status */ 569 break; 570 } 571 572 cf->data[6] = errc & PCH_TEC; 573 cf->data[7] = (errc & PCH_REC) >> 8; 574 575 priv->can.state = state; 576 netif_receive_skb(skb); 577 578 stats->rx_packets++; 579 stats->rx_bytes += cf->can_dlc; 580} 581 582static irqreturn_t pch_can_interrupt(int irq, void *dev_id) 583{ 584 struct net_device *ndev = (struct net_device *)dev_id; 585 struct pch_can_priv *priv = netdev_priv(ndev); 586 587 if (!pch_can_int_pending(priv)) 588 return IRQ_NONE; 589 590 pch_can_set_int_enables(priv, PCH_CAN_NONE); 591 napi_schedule(&priv->napi); 592 return IRQ_HANDLED; 593} 594 595static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id) 596{ 597 if (obj_id < PCH_FIFO_THRESH) { 598 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | 599 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask); 600 601 /* Clearing the Dir bit. */ 602 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR); 603 604 /* Clearing NewDat & IntPnd */ 605 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 606 PCH_IF_MCONT_INTPND); 607 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id); 608 } else if (obj_id > PCH_FIFO_THRESH) { 609 pch_can_int_clr(priv, obj_id); 610 } else if (obj_id == PCH_FIFO_THRESH) { 611 int cnt; 612 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++) 613 pch_can_int_clr(priv, cnt + 1); 614 } 615} 616 617static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id) 618{ 619 struct pch_can_priv *priv = netdev_priv(ndev); 620 struct net_device_stats *stats = &(priv->ndev->stats); 621 struct sk_buff *skb; 622 struct can_frame *cf; 623 624 netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n"); 625 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 626 PCH_IF_MCONT_MSGLOST); 627 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, 628 &priv->regs->ifregs[0].cmask); 629 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id); 630 631 skb = alloc_can_err_skb(ndev, &cf); 632 if (!skb) 633 return; 634 635 cf->can_id |= CAN_ERR_CRTL; 636 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 637 stats->rx_over_errors++; 638 stats->rx_errors++; 639 640 netif_receive_skb(skb); 641} 642 643static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota) 644{ 645 u32 reg; 646 canid_t id; 647 int rcv_pkts = 0; 648 struct sk_buff *skb; 649 struct can_frame *cf; 650 struct pch_can_priv *priv = netdev_priv(ndev); 651 struct net_device_stats *stats = &(priv->ndev->stats); 652 int i; 653 u32 id2; 654 u16 data_reg; 655 656 do { 657 /* Reading the message object from the Message RAM */ 658 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 659 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num); 660 661 /* Reading the MCONT register. */ 662 reg = ioread32(&priv->regs->ifregs[0].mcont); 663 664 if (reg & PCH_IF_MCONT_EOB) 665 break; 666 667 /* If MsgLost bit set. */ 668 if (reg & PCH_IF_MCONT_MSGLOST) { 669 pch_can_rx_msg_lost(ndev, obj_num); 670 rcv_pkts++; 671 quota--; 672 obj_num++; 673 continue; 674 } else if (!(reg & PCH_IF_MCONT_NEWDAT)) { 675 obj_num++; 676 continue; 677 } 678 679 skb = alloc_can_skb(priv->ndev, &cf); 680 if (!skb) { 681 netdev_err(ndev, "alloc_can_skb Failed\n"); 682 return rcv_pkts; 683 } 684 685 /* Get Received data */ 686 id2 = ioread32(&priv->regs->ifregs[0].id2); 687 if (id2 & PCH_ID2_XTD) { 688 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff); 689 id |= (((id2) & 0x1fff) << 16); 690 cf->can_id = id | CAN_EFF_FLAG; 691 } else { 692 id = (id2 >> 2) & CAN_SFF_MASK; 693 cf->can_id = id; 694 } 695 696 if (id2 & PCH_ID2_DIR) 697 cf->can_id |= CAN_RTR_FLAG; 698 699 cf->can_dlc = get_can_dlc((ioread32(&priv->regs-> 700 ifregs[0].mcont)) & 0xF); 701 702 for (i = 0; i < cf->can_dlc; i += 2) { 703 data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]); 704 cf->data[i] = data_reg; 705 cf->data[i + 1] = data_reg >> 8; 706 } 707 708 netif_receive_skb(skb); 709 rcv_pkts++; 710 stats->rx_packets++; 711 quota--; 712 stats->rx_bytes += cf->can_dlc; 713 714 pch_fifo_thresh(priv, obj_num); 715 obj_num++; 716 } while (quota > 0); 717 718 return rcv_pkts; 719} 720 721static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat) 722{ 723 struct pch_can_priv *priv = netdev_priv(ndev); 724 struct net_device_stats *stats = &(priv->ndev->stats); 725 u32 dlc; 726 727 can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1); 728 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND, 729 &priv->regs->ifregs[1].cmask); 730 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat); 731 dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) & 732 PCH_IF_MCONT_DLC); 733 stats->tx_bytes += dlc; 734 stats->tx_packets++; 735 if (int_stat == PCH_TX_OBJ_END) 736 netif_wake_queue(ndev); 737} 738 739static int pch_can_poll(struct napi_struct *napi, int quota) 740{ 741 struct net_device *ndev = napi->dev; 742 struct pch_can_priv *priv = netdev_priv(ndev); 743 u32 int_stat; 744 u32 reg_stat; 745 int quota_save = quota; 746 747 int_stat = pch_can_int_pending(priv); 748 if (!int_stat) 749 goto end; 750 751 if (int_stat == PCH_STATUS_INT) { 752 reg_stat = ioread32(&priv->regs->stat); 753 754 if ((reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) && 755 ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)) { 756 pch_can_error(ndev, reg_stat); 757 quota--; 758 } 759 760 if (reg_stat & (PCH_TX_OK | PCH_RX_OK)) 761 pch_can_bit_clear(&priv->regs->stat, 762 reg_stat & (PCH_TX_OK | PCH_RX_OK)); 763 764 int_stat = pch_can_int_pending(priv); 765 } 766 767 if (quota == 0) 768 goto end; 769 770 if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) { 771 quota -= pch_can_rx_normal(ndev, int_stat, quota); 772 } else if ((int_stat >= PCH_TX_OBJ_START) && 773 (int_stat <= PCH_TX_OBJ_END)) { 774 /* Handle transmission interrupt */ 775 pch_can_tx_complete(ndev, int_stat); 776 } 777 778end: 779 napi_complete(napi); 780 pch_can_set_int_enables(priv, PCH_CAN_ALL); 781 782 return quota_save - quota; 783} 784 785static int pch_set_bittiming(struct net_device *ndev) 786{ 787 struct pch_can_priv *priv = netdev_priv(ndev); 788 const struct can_bittiming *bt = &priv->can.bittiming; 789 u32 canbit; 790 u32 bepe; 791 792 /* Setting the CCE bit for accessing the Can Timing register. */ 793 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE); 794 795 canbit = (bt->brp - 1) & PCH_MSK_BITT_BRP; 796 canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT; 797 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT; 798 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT; 799 bepe = ((bt->brp - 1) & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT; 800 iowrite32(canbit, &priv->regs->bitt); 801 iowrite32(bepe, &priv->regs->brpe); 802 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE); 803 804 return 0; 805} 806 807static void pch_can_start(struct net_device *ndev) 808{ 809 struct pch_can_priv *priv = netdev_priv(ndev); 810 811 if (priv->can.state != CAN_STATE_STOPPED) 812 pch_can_reset(priv); 813 814 pch_set_bittiming(ndev); 815 pch_can_set_optmode(priv); 816 817 pch_can_set_tx_all(priv, 1); 818 pch_can_set_rx_all(priv, 1); 819 820 /* Setting the CAN to run mode. */ 821 pch_can_set_run_mode(priv, PCH_CAN_RUN); 822 823 priv->can.state = CAN_STATE_ERROR_ACTIVE; 824 825 return; 826} 827 828static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 829{ 830 int ret = 0; 831 832 switch (mode) { 833 case CAN_MODE_START: 834 pch_can_start(ndev); 835 netif_wake_queue(ndev); 836 break; 837 default: 838 ret = -EOPNOTSUPP; 839 break; 840 } 841 842 return ret; 843} 844 845static int pch_can_open(struct net_device *ndev) 846{ 847 struct pch_can_priv *priv = netdev_priv(ndev); 848 int retval; 849 850 /* Regstering the interrupt. */ 851 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED, 852 ndev->name, ndev); 853 if (retval) { 854 netdev_err(ndev, "request_irq failed.\n"); 855 goto req_irq_err; 856 } 857 858 /* Open common can device */ 859 retval = open_candev(ndev); 860 if (retval) { 861 netdev_err(ndev, "open_candev() failed %d\n", retval); 862 goto err_open_candev; 863 } 864 865 pch_can_init(priv); 866 pch_can_start(ndev); 867 napi_enable(&priv->napi); 868 netif_start_queue(ndev); 869 870 return 0; 871 872err_open_candev: 873 free_irq(priv->dev->irq, ndev); 874req_irq_err: 875 pch_can_release(priv); 876 877 return retval; 878} 879 880static int pch_close(struct net_device *ndev) 881{ 882 struct pch_can_priv *priv = netdev_priv(ndev); 883 884 netif_stop_queue(ndev); 885 napi_disable(&priv->napi); 886 pch_can_release(priv); 887 free_irq(priv->dev->irq, ndev); 888 close_candev(ndev); 889 priv->can.state = CAN_STATE_STOPPED; 890 return 0; 891} 892 893static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) 894{ 895 struct pch_can_priv *priv = netdev_priv(ndev); 896 struct can_frame *cf = (struct can_frame *)skb->data; 897 int tx_obj_no; 898 int i; 899 u32 id2; 900 901 if (can_dropped_invalid_skb(ndev, skb)) 902 return NETDEV_TX_OK; 903 904 tx_obj_no = priv->tx_obj; 905 if (priv->tx_obj == PCH_TX_OBJ_END) { 906 if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK) 907 netif_stop_queue(ndev); 908 909 priv->tx_obj = PCH_TX_OBJ_START; 910 } else { 911 priv->tx_obj++; 912 } 913 914 /* Setting the CMASK register. */ 915 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL); 916 917 /* If ID extended is set. */ 918 if (cf->can_id & CAN_EFF_FLAG) { 919 iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1); 920 id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD; 921 } else { 922 iowrite32(0, &priv->regs->ifregs[1].id1); 923 id2 = (cf->can_id & CAN_SFF_MASK) << 2; 924 } 925 926 id2 |= PCH_ID_MSGVAL; 927 928 /* If remote frame has to be transmitted.. */ 929 if (!(cf->can_id & CAN_RTR_FLAG)) 930 id2 |= PCH_ID2_DIR; 931 932 iowrite32(id2, &priv->regs->ifregs[1].id2); 933 934 /* Copy data to register */ 935 for (i = 0; i < cf->can_dlc; i += 2) { 936 iowrite16(cf->data[i] | (cf->data[i + 1] << 8), 937 &priv->regs->ifregs[1].data[i / 2]); 938 } 939 940 can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1); 941 942 /* Set the size of the data. Update if2_mcont */ 943 iowrite32(cf->can_dlc | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT | 944 PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont); 945 946 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no); 947 948 return NETDEV_TX_OK; 949} 950 951static const struct net_device_ops pch_can_netdev_ops = { 952 .ndo_open = pch_can_open, 953 .ndo_stop = pch_close, 954 .ndo_start_xmit = pch_xmit, 955}; 956 957static void pch_can_remove(struct pci_dev *pdev) 958{ 959 struct net_device *ndev = pci_get_drvdata(pdev); 960 struct pch_can_priv *priv = netdev_priv(ndev); 961 962 unregister_candev(priv->ndev); 963 if (priv->use_msi) 964 pci_disable_msi(priv->dev); 965 pci_release_regions(pdev); 966 pci_disable_device(pdev); 967 pci_set_drvdata(pdev, NULL); 968 pch_can_reset(priv); 969 pci_iounmap(pdev, priv->regs); 970 free_candev(priv->ndev); 971} 972 973#ifdef CONFIG_PM 974static void pch_can_set_int_custom(struct pch_can_priv *priv) 975{ 976 /* Clearing the IE, SIE and EIE bits of Can control register. */ 977 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE); 978 979 /* Appropriately setting them. */ 980 pch_can_bit_set(&priv->regs->cont, 981 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1)); 982} 983 984/* This function retrieves interrupt enabled for the CAN device. */ 985static u32 pch_can_get_int_enables(struct pch_can_priv *priv) 986{ 987 /* Obtaining the status of IE, SIE and EIE interrupt bits. */ 988 return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1; 989} 990 991static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num, 992 enum pch_ifreg dir) 993{ 994 u32 ie, enable; 995 996 if (dir) 997 ie = PCH_IF_MCONT_RXIE; 998 else 999 ie = PCH_IF_MCONT_TXIE; 1000 1001 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask); 1002 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num); 1003 1004 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) && 1005 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) 1006 enable = 1; 1007 else 1008 enable = 0; 1009 1010 return enable; 1011} 1012 1013static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, 1014 u32 buffer_num, int set) 1015{ 1016 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 1017 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num); 1018 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, 1019 &priv->regs->ifregs[0].cmask); 1020 if (set) 1021 pch_can_bit_clear(&priv->regs->ifregs[0].mcont, 1022 PCH_IF_MCONT_EOB); 1023 else 1024 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB); 1025 1026 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num); 1027} 1028 1029static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num) 1030{ 1031 u32 link; 1032 1033 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask); 1034 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num); 1035 1036 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB) 1037 link = 0; 1038 else 1039 link = 1; 1040 return link; 1041} 1042 1043static int pch_can_get_buffer_status(struct pch_can_priv *priv) 1044{ 1045 return (ioread32(&priv->regs->treq1) & 0xffff) | 1046 (ioread32(&priv->regs->treq2) << 16); 1047} 1048 1049static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state) 1050{ 1051 int i; 1052 int retval; 1053 u32 buf_stat; /* Variable for reading the transmit buffer status. */ 1054 int counter = PCH_COUNTER_LIMIT; 1055 1056 struct net_device *dev = pci_get_drvdata(pdev); 1057 struct pch_can_priv *priv = netdev_priv(dev); 1058 1059 /* Stop the CAN controller */ 1060 pch_can_set_run_mode(priv, PCH_CAN_STOP); 1061 1062 /* Indicate that we are aboutto/in suspend */ 1063 priv->can.state = CAN_STATE_STOPPED; 1064 1065 /* Waiting for all transmission to complete. */ 1066 while (counter) { 1067 buf_stat = pch_can_get_buffer_status(priv); 1068 if (!buf_stat) 1069 break; 1070 counter--; 1071 udelay(1); 1072 } 1073 if (!counter) 1074 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__); 1075 1076 /* Save interrupt configuration and then disable them */ 1077 priv->int_enables = pch_can_get_int_enables(priv); 1078 pch_can_set_int_enables(priv, PCH_CAN_DISABLE); 1079 1080 /* Save Tx buffer enable state */ 1081 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 1082 priv->tx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i, 1083 PCH_TX_IFREG); 1084 1085 /* Disable all Transmit buffers */ 1086 pch_can_set_tx_all(priv, 0); 1087 1088 /* Save Rx buffer enable state */ 1089 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 1090 priv->rx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i, 1091 PCH_RX_IFREG); 1092 priv->rx_link[i - 1] = pch_can_get_rx_buffer_link(priv, i); 1093 } 1094 1095 /* Disable all Receive buffers */ 1096 pch_can_set_rx_all(priv, 0); 1097 retval = pci_save_state(pdev); 1098 if (retval) { 1099 dev_err(&pdev->dev, "pci_save_state failed.\n"); 1100 } else { 1101 pci_enable_wake(pdev, PCI_D3hot, 0); 1102 pci_disable_device(pdev); 1103 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1104 } 1105 1106 return retval; 1107} 1108 1109static int pch_can_resume(struct pci_dev *pdev) 1110{ 1111 int i; 1112 int retval; 1113 struct net_device *dev = pci_get_drvdata(pdev); 1114 struct pch_can_priv *priv = netdev_priv(dev); 1115 1116 pci_set_power_state(pdev, PCI_D0); 1117 pci_restore_state(pdev); 1118 retval = pci_enable_device(pdev); 1119 if (retval) { 1120 dev_err(&pdev->dev, "pci_enable_device failed.\n"); 1121 return retval; 1122 } 1123 1124 pci_enable_wake(pdev, PCI_D3hot, 0); 1125 1126 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1127 1128 /* Disabling all interrupts. */ 1129 pch_can_set_int_enables(priv, PCH_CAN_DISABLE); 1130 1131 /* Setting the CAN device in Stop Mode. */ 1132 pch_can_set_run_mode(priv, PCH_CAN_STOP); 1133 1134 /* Configuring the transmit and receive buffers. */ 1135 pch_can_config_rx_tx_buffers(priv); 1136 1137 /* Restore the CAN state */ 1138 pch_set_bittiming(dev); 1139 1140 /* Listen/Active */ 1141 pch_can_set_optmode(priv); 1142 1143 /* Enabling the transmit buffer. */ 1144 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) 1145 pch_can_set_rxtx(priv, i, priv->tx_enable[i - 1], PCH_TX_IFREG); 1146 1147 /* Configuring the receive buffer and enabling them. */ 1148 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) { 1149 /* Restore buffer link */ 1150 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i - 1]); 1151 1152 /* Restore buffer enables */ 1153 pch_can_set_rxtx(priv, i, priv->rx_enable[i - 1], PCH_RX_IFREG); 1154 } 1155 1156 /* Enable CAN Interrupts */ 1157 pch_can_set_int_custom(priv); 1158 1159 /* Restore Run Mode */ 1160 pch_can_set_run_mode(priv, PCH_CAN_RUN); 1161 1162 return retval; 1163} 1164#else 1165#define pch_can_suspend NULL 1166#define pch_can_resume NULL 1167#endif 1168 1169static int pch_can_get_berr_counter(const struct net_device *dev, 1170 struct can_berr_counter *bec) 1171{ 1172 struct pch_can_priv *priv = netdev_priv(dev); 1173 u32 errc = ioread32(&priv->regs->errc); 1174 1175 bec->txerr = errc & PCH_TEC; 1176 bec->rxerr = (errc & PCH_REC) >> 8; 1177 1178 return 0; 1179} 1180 1181static int pch_can_probe(struct pci_dev *pdev, 1182 const struct pci_device_id *id) 1183{ 1184 struct net_device *ndev; 1185 struct pch_can_priv *priv; 1186 int rc; 1187 void __iomem *addr; 1188 1189 rc = pci_enable_device(pdev); 1190 if (rc) { 1191 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc); 1192 goto probe_exit_endev; 1193 } 1194 1195 rc = pci_request_regions(pdev, KBUILD_MODNAME); 1196 if (rc) { 1197 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc); 1198 goto probe_exit_pcireq; 1199 } 1200 1201 addr = pci_iomap(pdev, 1, 0); 1202 if (!addr) { 1203 rc = -EIO; 1204 dev_err(&pdev->dev, "Failed pci_iomap\n"); 1205 goto probe_exit_ipmap; 1206 } 1207 1208 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END); 1209 if (!ndev) { 1210 rc = -ENOMEM; 1211 dev_err(&pdev->dev, "Failed alloc_candev\n"); 1212 goto probe_exit_alloc_candev; 1213 } 1214 1215 priv = netdev_priv(ndev); 1216 priv->ndev = ndev; 1217 priv->regs = addr; 1218 priv->dev = pdev; 1219 priv->can.bittiming_const = &pch_can_bittiming_const; 1220 priv->can.do_set_mode = pch_can_do_set_mode; 1221 priv->can.do_get_berr_counter = pch_can_get_berr_counter; 1222 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | 1223 CAN_CTRLMODE_LOOPBACK; 1224 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */ 1225 1226 ndev->irq = pdev->irq; 1227 ndev->flags |= IFF_ECHO; 1228 1229 pci_set_drvdata(pdev, ndev); 1230 SET_NETDEV_DEV(ndev, &pdev->dev); 1231 ndev->netdev_ops = &pch_can_netdev_ops; 1232 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */ 1233 1234 netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END); 1235 1236 rc = pci_enable_msi(priv->dev); 1237 if (rc) { 1238 netdev_err(ndev, "PCH CAN opened without MSI\n"); 1239 priv->use_msi = 0; 1240 } else { 1241 netdev_err(ndev, "PCH CAN opened with MSI\n"); 1242 pci_set_master(pdev); 1243 priv->use_msi = 1; 1244 } 1245 1246 rc = register_candev(ndev); 1247 if (rc) { 1248 dev_err(&pdev->dev, "Failed register_candev %d\n", rc); 1249 goto probe_exit_reg_candev; 1250 } 1251 1252 return 0; 1253 1254probe_exit_reg_candev: 1255 if (priv->use_msi) 1256 pci_disable_msi(priv->dev); 1257 free_candev(ndev); 1258probe_exit_alloc_candev: 1259 pci_iounmap(pdev, addr); 1260probe_exit_ipmap: 1261 pci_release_regions(pdev); 1262probe_exit_pcireq: 1263 pci_disable_device(pdev); 1264probe_exit_endev: 1265 return rc; 1266} 1267 1268static struct pci_driver pch_can_pci_driver = { 1269 .name = "pch_can", 1270 .id_table = pch_pci_tbl, 1271 .probe = pch_can_probe, 1272 .remove = pch_can_remove, 1273 .suspend = pch_can_suspend, 1274 .resume = pch_can_resume, 1275}; 1276 1277module_pci_driver(pch_can_pci_driver); 1278 1279MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver"); 1280MODULE_LICENSE("GPL v2"); 1281MODULE_VERSION("0.94"); 1282