rcar_can.c revision 862e2b6af9413b43ef044979b934cab07bfd33e5
1/* Renesas R-Car CAN device driver 2 * 3 * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com> 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12#include <linux/module.h> 13#include <linux/kernel.h> 14#include <linux/types.h> 15#include <linux/interrupt.h> 16#include <linux/errno.h> 17#include <linux/netdevice.h> 18#include <linux/platform_device.h> 19#include <linux/can/led.h> 20#include <linux/can/dev.h> 21#include <linux/clk.h> 22#include <linux/can/platform/rcar_can.h> 23 24#define RCAR_CAN_DRV_NAME "rcar_can" 25 26/* Mailbox configuration: 27 * mailbox 60 - 63 - Rx FIFO mailboxes 28 * mailbox 56 - 59 - Tx FIFO mailboxes 29 * non-FIFO mailboxes are not used 30 */ 31#define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */ 32#define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */ 33#define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */ 34#define RCAR_CAN_FIFO_DEPTH 4 35 36/* Mailbox registers structure */ 37struct rcar_can_mbox_regs { 38 u32 id; /* IDE and RTR bits, SID and EID */ 39 u8 stub; /* Not used */ 40 u8 dlc; /* Data Length Code - bits [0..3] */ 41 u8 data[8]; /* Data Bytes */ 42 u8 tsh; /* Time Stamp Higher Byte */ 43 u8 tsl; /* Time Stamp Lower Byte */ 44}; 45 46struct rcar_can_regs { 47 struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */ 48 u32 mkr_2_9[8]; /* Mask Registers 2-9 */ 49 u32 fidcr[2]; /* FIFO Received ID Compare Register */ 50 u32 mkivlr1; /* Mask Invalid Register 1 */ 51 u32 mier1; /* Mailbox Interrupt Enable Register 1 */ 52 u32 mkr_0_1[2]; /* Mask Registers 0-1 */ 53 u32 mkivlr0; /* Mask Invalid Register 0*/ 54 u32 mier0; /* Mailbox Interrupt Enable Register 0 */ 55 u8 pad_440[0x3c0]; 56 u8 mctl[64]; /* Message Control Registers */ 57 u16 ctlr; /* Control Register */ 58 u16 str; /* Status register */ 59 u8 bcr[3]; /* Bit Configuration Register */ 60 u8 clkr; /* Clock Select Register */ 61 u8 rfcr; /* Receive FIFO Control Register */ 62 u8 rfpcr; /* Receive FIFO Pointer Control Register */ 63 u8 tfcr; /* Transmit FIFO Control Register */ 64 u8 tfpcr; /* Transmit FIFO Pointer Control Register */ 65 u8 eier; /* Error Interrupt Enable Register */ 66 u8 eifr; /* Error Interrupt Factor Judge Register */ 67 u8 recr; /* Receive Error Count Register */ 68 u8 tecr; /* Transmit Error Count Register */ 69 u8 ecsr; /* Error Code Store Register */ 70 u8 cssr; /* Channel Search Support Register */ 71 u8 mssr; /* Mailbox Search Status Register */ 72 u8 msmr; /* Mailbox Search Mode Register */ 73 u16 tsr; /* Time Stamp Register */ 74 u8 afsr; /* Acceptance Filter Support Register */ 75 u8 pad_857; 76 u8 tcr; /* Test Control Register */ 77 u8 pad_859[7]; 78 u8 ier; /* Interrupt Enable Register */ 79 u8 isr; /* Interrupt Status Register */ 80 u8 pad_862; 81 u8 mbsmr; /* Mailbox Search Mask Register */ 82}; 83 84struct rcar_can_priv { 85 struct can_priv can; /* Must be the first member! */ 86 struct net_device *ndev; 87 struct napi_struct napi; 88 struct rcar_can_regs __iomem *regs; 89 struct clk *clk; 90 struct clk *can_clk; 91 u8 tx_dlc[RCAR_CAN_FIFO_DEPTH]; 92 u32 tx_head; 93 u32 tx_tail; 94 u8 clock_select; 95 u8 ier; 96}; 97 98static const struct can_bittiming_const rcar_can_bittiming_const = { 99 .name = RCAR_CAN_DRV_NAME, 100 .tseg1_min = 4, 101 .tseg1_max = 16, 102 .tseg2_min = 2, 103 .tseg2_max = 8, 104 .sjw_max = 4, 105 .brp_min = 1, 106 .brp_max = 1024, 107 .brp_inc = 1, 108}; 109 110/* Control Register bits */ 111#define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */ 112#define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */ 113 /* at bus-off entry */ 114#define RCAR_CAN_CTLR_SLPM (1 << 10) 115#define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */ 116#define RCAR_CAN_CTLR_CANM_HALT (1 << 9) 117#define RCAR_CAN_CTLR_CANM_RESET (1 << 8) 118#define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8) 119#define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */ 120#define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */ 121#define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */ 122#define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */ 123 124/* Status Register bits */ 125#define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */ 126 127/* FIFO Received ID Compare Registers 0 and 1 bits */ 128#define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */ 129#define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */ 130 131/* Receive FIFO Control Register bits */ 132#define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */ 133#define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */ 134 135/* Transmit FIFO Control Register bits */ 136#define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */ 137 /* Number Status Bits */ 138#define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */ 139 /* Message Number Status Bits */ 140#define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */ 141 142#define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */ 143 /* for Rx mailboxes 0-31 */ 144#define RCAR_CAN_N_RX_MKREGS2 8 145 146/* Bit Configuration Register settings */ 147#define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20) 148#define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8) 149#define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4) 150#define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07) 151 152/* Mailbox and Mask Registers bits */ 153#define RCAR_CAN_IDE (1 << 31) 154#define RCAR_CAN_RTR (1 << 30) 155#define RCAR_CAN_SID_SHIFT 18 156 157/* Mailbox Interrupt Enable Register 1 bits */ 158#define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */ 159#define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */ 160 161/* Interrupt Enable Register bits */ 162#define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */ 163#define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */ 164 /* Enable Bit */ 165#define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */ 166 /* Enable Bit */ 167/* Interrupt Status Register bits */ 168#define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */ 169#define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */ 170 /* Status Bit */ 171#define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */ 172 /* Status Bit */ 173 174/* Error Interrupt Enable Register bits */ 175#define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */ 176#define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */ 177 /* Interrupt Enable */ 178#define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */ 179#define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */ 180#define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */ 181#define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */ 182#define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */ 183#define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */ 184 185/* Error Interrupt Factor Judge Register bits */ 186#define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */ 187#define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */ 188 /* Detect Flag */ 189#define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */ 190#define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */ 191#define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */ 192#define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */ 193#define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */ 194#define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */ 195 196/* Error Code Store Register bits */ 197#define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */ 198#define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */ 199#define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */ 200#define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */ 201#define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */ 202#define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */ 203#define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */ 204#define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */ 205 206#define RCAR_CAN_NAPI_WEIGHT 4 207#define MAX_STR_READS 0x100 208 209static void tx_failure_cleanup(struct net_device *ndev) 210{ 211 int i; 212 213 for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++) 214 can_free_echo_skb(ndev, i); 215} 216 217static void rcar_can_error(struct net_device *ndev) 218{ 219 struct rcar_can_priv *priv = netdev_priv(ndev); 220 struct net_device_stats *stats = &ndev->stats; 221 struct can_frame *cf; 222 struct sk_buff *skb; 223 u8 eifr, txerr = 0, rxerr = 0; 224 225 /* Propagate the error condition to the CAN stack */ 226 skb = alloc_can_err_skb(ndev, &cf); 227 228 eifr = readb(&priv->regs->eifr); 229 if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) { 230 txerr = readb(&priv->regs->tecr); 231 rxerr = readb(&priv->regs->recr); 232 if (skb) { 233 cf->can_id |= CAN_ERR_CRTL; 234 cf->data[6] = txerr; 235 cf->data[7] = rxerr; 236 } 237 } 238 if (eifr & RCAR_CAN_EIFR_BEIF) { 239 int rx_errors = 0, tx_errors = 0; 240 u8 ecsr; 241 242 netdev_dbg(priv->ndev, "Bus error interrupt:\n"); 243 if (skb) { 244 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 245 cf->data[2] = CAN_ERR_PROT_UNSPEC; 246 } 247 ecsr = readb(&priv->regs->ecsr); 248 if (ecsr & RCAR_CAN_ECSR_ADEF) { 249 netdev_dbg(priv->ndev, "ACK Delimiter Error\n"); 250 tx_errors++; 251 writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr); 252 if (skb) 253 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL; 254 } 255 if (ecsr & RCAR_CAN_ECSR_BE0F) { 256 netdev_dbg(priv->ndev, "Bit Error (dominant)\n"); 257 tx_errors++; 258 writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr); 259 if (skb) 260 cf->data[2] |= CAN_ERR_PROT_BIT0; 261 } 262 if (ecsr & RCAR_CAN_ECSR_BE1F) { 263 netdev_dbg(priv->ndev, "Bit Error (recessive)\n"); 264 tx_errors++; 265 writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr); 266 if (skb) 267 cf->data[2] |= CAN_ERR_PROT_BIT1; 268 } 269 if (ecsr & RCAR_CAN_ECSR_CEF) { 270 netdev_dbg(priv->ndev, "CRC Error\n"); 271 rx_errors++; 272 writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr); 273 if (skb) 274 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 275 } 276 if (ecsr & RCAR_CAN_ECSR_AEF) { 277 netdev_dbg(priv->ndev, "ACK Error\n"); 278 tx_errors++; 279 writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr); 280 if (skb) { 281 cf->can_id |= CAN_ERR_ACK; 282 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 283 } 284 } 285 if (ecsr & RCAR_CAN_ECSR_FEF) { 286 netdev_dbg(priv->ndev, "Form Error\n"); 287 rx_errors++; 288 writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr); 289 if (skb) 290 cf->data[2] |= CAN_ERR_PROT_FORM; 291 } 292 if (ecsr & RCAR_CAN_ECSR_SEF) { 293 netdev_dbg(priv->ndev, "Stuff Error\n"); 294 rx_errors++; 295 writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr); 296 if (skb) 297 cf->data[2] |= CAN_ERR_PROT_STUFF; 298 } 299 300 priv->can.can_stats.bus_error++; 301 ndev->stats.rx_errors += rx_errors; 302 ndev->stats.tx_errors += tx_errors; 303 writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr); 304 } 305 if (eifr & RCAR_CAN_EIFR_EWIF) { 306 netdev_dbg(priv->ndev, "Error warning interrupt\n"); 307 priv->can.state = CAN_STATE_ERROR_WARNING; 308 priv->can.can_stats.error_warning++; 309 /* Clear interrupt condition */ 310 writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr); 311 if (skb) 312 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING : 313 CAN_ERR_CRTL_RX_WARNING; 314 } 315 if (eifr & RCAR_CAN_EIFR_EPIF) { 316 netdev_dbg(priv->ndev, "Error passive interrupt\n"); 317 priv->can.state = CAN_STATE_ERROR_PASSIVE; 318 priv->can.can_stats.error_passive++; 319 /* Clear interrupt condition */ 320 writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr); 321 if (skb) 322 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE : 323 CAN_ERR_CRTL_RX_PASSIVE; 324 } 325 if (eifr & RCAR_CAN_EIFR_BOEIF) { 326 netdev_dbg(priv->ndev, "Bus-off entry interrupt\n"); 327 tx_failure_cleanup(ndev); 328 priv->ier = RCAR_CAN_IER_ERSIE; 329 writeb(priv->ier, &priv->regs->ier); 330 priv->can.state = CAN_STATE_BUS_OFF; 331 /* Clear interrupt condition */ 332 writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr); 333 can_bus_off(ndev); 334 if (skb) 335 cf->can_id |= CAN_ERR_BUSOFF; 336 } 337 if (eifr & RCAR_CAN_EIFR_ORIF) { 338 netdev_dbg(priv->ndev, "Receive overrun error interrupt\n"); 339 ndev->stats.rx_over_errors++; 340 ndev->stats.rx_errors++; 341 writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr); 342 if (skb) { 343 cf->can_id |= CAN_ERR_CRTL; 344 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 345 } 346 } 347 if (eifr & RCAR_CAN_EIFR_OLIF) { 348 netdev_dbg(priv->ndev, 349 "Overload Frame Transmission error interrupt\n"); 350 ndev->stats.rx_over_errors++; 351 ndev->stats.rx_errors++; 352 writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr); 353 if (skb) { 354 cf->can_id |= CAN_ERR_PROT; 355 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 356 } 357 } 358 359 if (skb) { 360 stats->rx_packets++; 361 stats->rx_bytes += cf->can_dlc; 362 netif_rx(skb); 363 } 364} 365 366static void rcar_can_tx_done(struct net_device *ndev) 367{ 368 struct rcar_can_priv *priv = netdev_priv(ndev); 369 struct net_device_stats *stats = &ndev->stats; 370 u8 isr; 371 372 while (1) { 373 u8 unsent = readb(&priv->regs->tfcr); 374 375 unsent = (unsent & RCAR_CAN_TFCR_TFUST) >> 376 RCAR_CAN_TFCR_TFUST_SHIFT; 377 if (priv->tx_head - priv->tx_tail <= unsent) 378 break; 379 stats->tx_packets++; 380 stats->tx_bytes += priv->tx_dlc[priv->tx_tail % 381 RCAR_CAN_FIFO_DEPTH]; 382 priv->tx_dlc[priv->tx_tail % RCAR_CAN_FIFO_DEPTH] = 0; 383 can_get_echo_skb(ndev, priv->tx_tail % RCAR_CAN_FIFO_DEPTH); 384 priv->tx_tail++; 385 netif_wake_queue(ndev); 386 } 387 /* Clear interrupt */ 388 isr = readb(&priv->regs->isr); 389 writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr); 390 can_led_event(ndev, CAN_LED_EVENT_TX); 391} 392 393static irqreturn_t rcar_can_interrupt(int irq, void *dev_id) 394{ 395 struct net_device *ndev = dev_id; 396 struct rcar_can_priv *priv = netdev_priv(ndev); 397 u8 isr; 398 399 isr = readb(&priv->regs->isr); 400 if (!(isr & priv->ier)) 401 return IRQ_NONE; 402 403 if (isr & RCAR_CAN_ISR_ERSF) 404 rcar_can_error(ndev); 405 406 if (isr & RCAR_CAN_ISR_TXFF) 407 rcar_can_tx_done(ndev); 408 409 if (isr & RCAR_CAN_ISR_RXFF) { 410 if (napi_schedule_prep(&priv->napi)) { 411 /* Disable Rx FIFO interrupts */ 412 priv->ier &= ~RCAR_CAN_IER_RXFIE; 413 writeb(priv->ier, &priv->regs->ier); 414 __napi_schedule(&priv->napi); 415 } 416 } 417 418 return IRQ_HANDLED; 419} 420 421static void rcar_can_set_bittiming(struct net_device *dev) 422{ 423 struct rcar_can_priv *priv = netdev_priv(dev); 424 struct can_bittiming *bt = &priv->can.bittiming; 425 u32 bcr; 426 427 bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) | 428 RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) | 429 RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1); 430 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access. 431 * All the registers are big-endian but they get byte-swapped on 32-bit 432 * read/write (but not on 8-bit, contrary to the manuals)... 433 */ 434 writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); 435} 436 437static void rcar_can_start(struct net_device *ndev) 438{ 439 struct rcar_can_priv *priv = netdev_priv(ndev); 440 u16 ctlr; 441 int i; 442 443 /* Set controller to known mode: 444 * - FIFO mailbox mode 445 * - accept all messages 446 * - overrun mode 447 * CAN is in sleep mode after MCU hardware or software reset. 448 */ 449 ctlr = readw(&priv->regs->ctlr); 450 ctlr &= ~RCAR_CAN_CTLR_SLPM; 451 writew(ctlr, &priv->regs->ctlr); 452 /* Go to reset mode */ 453 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 454 writew(ctlr, &priv->regs->ctlr); 455 for (i = 0; i < MAX_STR_READS; i++) { 456 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 457 break; 458 } 459 rcar_can_set_bittiming(ndev); 460 ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */ 461 ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */ 462 /* at bus-off */ 463 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */ 464 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */ 465 writew(ctlr, &priv->regs->ctlr); 466 467 /* Accept all SID and EID */ 468 writel(0, &priv->regs->mkr_2_9[6]); 469 writel(0, &priv->regs->mkr_2_9[7]); 470 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */ 471 writel(0, &priv->regs->mkivlr1); 472 /* Accept all frames */ 473 writel(0, &priv->regs->fidcr[0]); 474 writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]); 475 /* Enable and configure FIFO mailbox interrupts */ 476 writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1); 477 478 priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | 479 RCAR_CAN_IER_TXFIE; 480 writeb(priv->ier, &priv->regs->ier); 481 482 /* Accumulate error codes */ 483 writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr); 484 /* Enable error interrupts */ 485 writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE | 486 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ? 487 RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE | 488 RCAR_CAN_EIER_OLIE, &priv->regs->eier); 489 priv->can.state = CAN_STATE_ERROR_ACTIVE; 490 491 /* Go to operation mode */ 492 writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr); 493 for (i = 0; i < MAX_STR_READS; i++) { 494 if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)) 495 break; 496 } 497 /* Enable Rx and Tx FIFO */ 498 writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr); 499 writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr); 500} 501 502static int rcar_can_open(struct net_device *ndev) 503{ 504 struct rcar_can_priv *priv = netdev_priv(ndev); 505 int err; 506 507 err = clk_prepare_enable(priv->clk); 508 if (err) { 509 netdev_err(ndev, "failed to enable periperal clock, error %d\n", 510 err); 511 goto out; 512 } 513 err = clk_prepare_enable(priv->can_clk); 514 if (err) { 515 netdev_err(ndev, "failed to enable CAN clock, error %d\n", 516 err); 517 goto out_clock; 518 } 519 err = open_candev(ndev); 520 if (err) { 521 netdev_err(ndev, "open_candev() failed, error %d\n", err); 522 goto out_can_clock; 523 } 524 napi_enable(&priv->napi); 525 err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev); 526 if (err) { 527 netdev_err(ndev, "error requesting interrupt %x\n", ndev->irq); 528 goto out_close; 529 } 530 can_led_event(ndev, CAN_LED_EVENT_OPEN); 531 rcar_can_start(ndev); 532 netif_start_queue(ndev); 533 return 0; 534out_close: 535 napi_disable(&priv->napi); 536 close_candev(ndev); 537out_can_clock: 538 clk_disable_unprepare(priv->can_clk); 539out_clock: 540 clk_disable_unprepare(priv->clk); 541out: 542 return err; 543} 544 545static void rcar_can_stop(struct net_device *ndev) 546{ 547 struct rcar_can_priv *priv = netdev_priv(ndev); 548 u16 ctlr; 549 int i; 550 551 /* Go to (force) reset mode */ 552 ctlr = readw(&priv->regs->ctlr); 553 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 554 writew(ctlr, &priv->regs->ctlr); 555 for (i = 0; i < MAX_STR_READS; i++) { 556 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 557 break; 558 } 559 writel(0, &priv->regs->mier0); 560 writel(0, &priv->regs->mier1); 561 writeb(0, &priv->regs->ier); 562 writeb(0, &priv->regs->eier); 563 /* Go to sleep mode */ 564 ctlr |= RCAR_CAN_CTLR_SLPM; 565 writew(ctlr, &priv->regs->ctlr); 566 priv->can.state = CAN_STATE_STOPPED; 567} 568 569static int rcar_can_close(struct net_device *ndev) 570{ 571 struct rcar_can_priv *priv = netdev_priv(ndev); 572 573 netif_stop_queue(ndev); 574 rcar_can_stop(ndev); 575 free_irq(ndev->irq, ndev); 576 napi_disable(&priv->napi); 577 clk_disable_unprepare(priv->can_clk); 578 clk_disable_unprepare(priv->clk); 579 close_candev(ndev); 580 can_led_event(ndev, CAN_LED_EVENT_STOP); 581 return 0; 582} 583 584static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb, 585 struct net_device *ndev) 586{ 587 struct rcar_can_priv *priv = netdev_priv(ndev); 588 struct can_frame *cf = (struct can_frame *)skb->data; 589 u32 data, i; 590 591 if (can_dropped_invalid_skb(ndev, skb)) 592 return NETDEV_TX_OK; 593 594 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ 595 data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE; 596 else /* Standard frame format */ 597 data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT; 598 599 if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */ 600 data |= RCAR_CAN_RTR; 601 } else { 602 for (i = 0; i < cf->can_dlc; i++) 603 writeb(cf->data[i], 604 &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]); 605 } 606 607 writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id); 608 609 writeb(cf->can_dlc, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc); 610 611 priv->tx_dlc[priv->tx_head % RCAR_CAN_FIFO_DEPTH] = cf->can_dlc; 612 can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH); 613 priv->tx_head++; 614 /* Start Tx: write 0xff to the TFPCR register to increment 615 * the CPU-side pointer for the transmit FIFO to the next 616 * mailbox location 617 */ 618 writeb(0xff, &priv->regs->tfpcr); 619 /* Stop the queue if we've filled all FIFO entries */ 620 if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH) 621 netif_stop_queue(ndev); 622 623 return NETDEV_TX_OK; 624} 625 626static const struct net_device_ops rcar_can_netdev_ops = { 627 .ndo_open = rcar_can_open, 628 .ndo_stop = rcar_can_close, 629 .ndo_start_xmit = rcar_can_start_xmit, 630}; 631 632static void rcar_can_rx_pkt(struct rcar_can_priv *priv) 633{ 634 struct net_device_stats *stats = &priv->ndev->stats; 635 struct can_frame *cf; 636 struct sk_buff *skb; 637 u32 data; 638 u8 dlc; 639 640 skb = alloc_can_skb(priv->ndev, &cf); 641 if (!skb) { 642 stats->rx_dropped++; 643 return; 644 } 645 646 data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id); 647 if (data & RCAR_CAN_IDE) 648 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; 649 else 650 cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK; 651 652 dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc); 653 cf->can_dlc = get_can_dlc(dlc); 654 if (data & RCAR_CAN_RTR) { 655 cf->can_id |= CAN_RTR_FLAG; 656 } else { 657 for (dlc = 0; dlc < cf->can_dlc; dlc++) 658 cf->data[dlc] = 659 readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]); 660 } 661 662 can_led_event(priv->ndev, CAN_LED_EVENT_RX); 663 664 stats->rx_bytes += cf->can_dlc; 665 stats->rx_packets++; 666 netif_receive_skb(skb); 667} 668 669static int rcar_can_rx_poll(struct napi_struct *napi, int quota) 670{ 671 struct rcar_can_priv *priv = container_of(napi, 672 struct rcar_can_priv, napi); 673 int num_pkts; 674 675 for (num_pkts = 0; num_pkts < quota; num_pkts++) { 676 u8 rfcr, isr; 677 678 isr = readb(&priv->regs->isr); 679 /* Clear interrupt bit */ 680 if (isr & RCAR_CAN_ISR_RXFF) 681 writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr); 682 rfcr = readb(&priv->regs->rfcr); 683 if (rfcr & RCAR_CAN_RFCR_RFEST) 684 break; 685 rcar_can_rx_pkt(priv); 686 /* Write 0xff to the RFPCR register to increment 687 * the CPU-side pointer for the receive FIFO 688 * to the next mailbox location 689 */ 690 writeb(0xff, &priv->regs->rfpcr); 691 } 692 /* All packets processed */ 693 if (num_pkts < quota) { 694 napi_complete(napi); 695 priv->ier |= RCAR_CAN_IER_RXFIE; 696 writeb(priv->ier, &priv->regs->ier); 697 } 698 return num_pkts; 699} 700 701static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 702{ 703 switch (mode) { 704 case CAN_MODE_START: 705 rcar_can_start(ndev); 706 netif_wake_queue(ndev); 707 return 0; 708 default: 709 return -EOPNOTSUPP; 710 } 711} 712 713static int rcar_can_get_berr_counter(const struct net_device *dev, 714 struct can_berr_counter *bec) 715{ 716 struct rcar_can_priv *priv = netdev_priv(dev); 717 int err; 718 719 err = clk_prepare_enable(priv->clk); 720 if (err) 721 return err; 722 bec->txerr = readb(&priv->regs->tecr); 723 bec->rxerr = readb(&priv->regs->recr); 724 clk_disable_unprepare(priv->clk); 725 return 0; 726} 727 728static const char * const clock_names[] = { 729 [CLKR_CLKP1] = "clkp1", 730 [CLKR_CLKP2] = "clkp2", 731 [CLKR_CLKEXT] = "can_clk", 732}; 733 734static int rcar_can_probe(struct platform_device *pdev) 735{ 736 struct rcar_can_platform_data *pdata; 737 struct rcar_can_priv *priv; 738 struct net_device *ndev; 739 struct resource *mem; 740 void __iomem *addr; 741 u32 clock_select; 742 int err = -ENODEV; 743 int irq; 744 745 pdata = dev_get_platdata(&pdev->dev); 746 if (!pdata) { 747 dev_err(&pdev->dev, "No platform data provided!\n"); 748 goto fail; 749 } 750 clock_select = pdata->clock_select; 751 752 irq = platform_get_irq(pdev, 0); 753 if (!irq) { 754 dev_err(&pdev->dev, "No IRQ resource\n"); 755 goto fail; 756 } 757 758 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 759 addr = devm_ioremap_resource(&pdev->dev, mem); 760 if (IS_ERR(addr)) { 761 err = PTR_ERR(addr); 762 goto fail; 763 } 764 765 ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH); 766 if (!ndev) { 767 dev_err(&pdev->dev, "alloc_candev() failed\n"); 768 err = -ENOMEM; 769 goto fail; 770 } 771 772 priv = netdev_priv(ndev); 773 774 priv->clk = devm_clk_get(&pdev->dev, "clkp1"); 775 if (IS_ERR(priv->clk)) { 776 err = PTR_ERR(priv->clk); 777 dev_err(&pdev->dev, "cannot get peripheral clock: %d\n", err); 778 goto fail_clk; 779 } 780 781 if (clock_select >= ARRAY_SIZE(clock_names)) { 782 err = -EINVAL; 783 dev_err(&pdev->dev, "invalid CAN clock selected\n"); 784 goto fail_clk; 785 } 786 priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]); 787 if (IS_ERR(priv->can_clk)) { 788 err = PTR_ERR(priv->can_clk); 789 dev_err(&pdev->dev, "cannot get CAN clock: %d\n", err); 790 goto fail_clk; 791 } 792 793 ndev->netdev_ops = &rcar_can_netdev_ops; 794 ndev->irq = irq; 795 ndev->flags |= IFF_ECHO; 796 priv->ndev = ndev; 797 priv->regs = addr; 798 priv->clock_select = clock_select; 799 priv->can.clock.freq = clk_get_rate(priv->can_clk); 800 priv->can.bittiming_const = &rcar_can_bittiming_const; 801 priv->can.do_set_mode = rcar_can_do_set_mode; 802 priv->can.do_get_berr_counter = rcar_can_get_berr_counter; 803 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING; 804 platform_set_drvdata(pdev, ndev); 805 SET_NETDEV_DEV(ndev, &pdev->dev); 806 807 netif_napi_add(ndev, &priv->napi, rcar_can_rx_poll, 808 RCAR_CAN_NAPI_WEIGHT); 809 err = register_candev(ndev); 810 if (err) { 811 dev_err(&pdev->dev, "register_candev() failed, error %d\n", 812 err); 813 goto fail_candev; 814 } 815 816 devm_can_led_init(ndev); 817 818 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n", 819 priv->regs, ndev->irq); 820 821 return 0; 822fail_candev: 823 netif_napi_del(&priv->napi); 824fail_clk: 825 free_candev(ndev); 826fail: 827 return err; 828} 829 830static int rcar_can_remove(struct platform_device *pdev) 831{ 832 struct net_device *ndev = platform_get_drvdata(pdev); 833 struct rcar_can_priv *priv = netdev_priv(ndev); 834 835 unregister_candev(ndev); 836 netif_napi_del(&priv->napi); 837 free_candev(ndev); 838 return 0; 839} 840 841static int __maybe_unused rcar_can_suspend(struct device *dev) 842{ 843 struct net_device *ndev = dev_get_drvdata(dev); 844 struct rcar_can_priv *priv = netdev_priv(ndev); 845 u16 ctlr; 846 847 if (netif_running(ndev)) { 848 netif_stop_queue(ndev); 849 netif_device_detach(ndev); 850 } 851 ctlr = readw(&priv->regs->ctlr); 852 ctlr |= RCAR_CAN_CTLR_CANM_HALT; 853 writew(ctlr, &priv->regs->ctlr); 854 ctlr |= RCAR_CAN_CTLR_SLPM; 855 writew(ctlr, &priv->regs->ctlr); 856 priv->can.state = CAN_STATE_SLEEPING; 857 858 clk_disable(priv->clk); 859 return 0; 860} 861 862static int __maybe_unused rcar_can_resume(struct device *dev) 863{ 864 struct net_device *ndev = dev_get_drvdata(dev); 865 struct rcar_can_priv *priv = netdev_priv(ndev); 866 u16 ctlr; 867 int err; 868 869 err = clk_enable(priv->clk); 870 if (err) { 871 netdev_err(ndev, "clk_enable() failed, error %d\n", err); 872 return err; 873 } 874 875 ctlr = readw(&priv->regs->ctlr); 876 ctlr &= ~RCAR_CAN_CTLR_SLPM; 877 writew(ctlr, &priv->regs->ctlr); 878 ctlr &= ~RCAR_CAN_CTLR_CANM; 879 writew(ctlr, &priv->regs->ctlr); 880 priv->can.state = CAN_STATE_ERROR_ACTIVE; 881 882 if (netif_running(ndev)) { 883 netif_device_attach(ndev); 884 netif_start_queue(ndev); 885 } 886 return 0; 887} 888 889static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume); 890 891static struct platform_driver rcar_can_driver = { 892 .driver = { 893 .name = RCAR_CAN_DRV_NAME, 894 .owner = THIS_MODULE, 895 .pm = &rcar_can_pm_ops, 896 }, 897 .probe = rcar_can_probe, 898 .remove = rcar_can_remove, 899}; 900 901module_platform_driver(rcar_can_driver); 902 903MODULE_AUTHOR("Cogent Embedded, Inc."); 904MODULE_LICENSE("GPL"); 905MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC"); 906MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME); 907