rcar_can.c revision ca976d6af4e50899f4e840e8017ec29d8fe6b50e
1/* Renesas R-Car CAN device driver 2 * 3 * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com> 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12#include <linux/module.h> 13#include <linux/kernel.h> 14#include <linux/types.h> 15#include <linux/interrupt.h> 16#include <linux/errno.h> 17#include <linux/netdevice.h> 18#include <linux/platform_device.h> 19#include <linux/can/led.h> 20#include <linux/can/dev.h> 21#include <linux/clk.h> 22#include <linux/can/platform/rcar_can.h> 23#include <linux/of.h> 24 25#define RCAR_CAN_DRV_NAME "rcar_can" 26 27/* Mailbox configuration: 28 * mailbox 60 - 63 - Rx FIFO mailboxes 29 * mailbox 56 - 59 - Tx FIFO mailboxes 30 * non-FIFO mailboxes are not used 31 */ 32#define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */ 33#define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */ 34#define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */ 35#define RCAR_CAN_FIFO_DEPTH 4 36 37/* Mailbox registers structure */ 38struct rcar_can_mbox_regs { 39 u32 id; /* IDE and RTR bits, SID and EID */ 40 u8 stub; /* Not used */ 41 u8 dlc; /* Data Length Code - bits [0..3] */ 42 u8 data[8]; /* Data Bytes */ 43 u8 tsh; /* Time Stamp Higher Byte */ 44 u8 tsl; /* Time Stamp Lower Byte */ 45}; 46 47struct rcar_can_regs { 48 struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */ 49 u32 mkr_2_9[8]; /* Mask Registers 2-9 */ 50 u32 fidcr[2]; /* FIFO Received ID Compare Register */ 51 u32 mkivlr1; /* Mask Invalid Register 1 */ 52 u32 mier1; /* Mailbox Interrupt Enable Register 1 */ 53 u32 mkr_0_1[2]; /* Mask Registers 0-1 */ 54 u32 mkivlr0; /* Mask Invalid Register 0*/ 55 u32 mier0; /* Mailbox Interrupt Enable Register 0 */ 56 u8 pad_440[0x3c0]; 57 u8 mctl[64]; /* Message Control Registers */ 58 u16 ctlr; /* Control Register */ 59 u16 str; /* Status register */ 60 u8 bcr[3]; /* Bit Configuration Register */ 61 u8 clkr; /* Clock Select Register */ 62 u8 rfcr; /* Receive FIFO Control Register */ 63 u8 rfpcr; /* Receive FIFO Pointer Control Register */ 64 u8 tfcr; /* Transmit FIFO Control Register */ 65 u8 tfpcr; /* Transmit FIFO Pointer Control Register */ 66 u8 eier; /* Error Interrupt Enable Register */ 67 u8 eifr; /* Error Interrupt Factor Judge Register */ 68 u8 recr; /* Receive Error Count Register */ 69 u8 tecr; /* Transmit Error Count Register */ 70 u8 ecsr; /* Error Code Store Register */ 71 u8 cssr; /* Channel Search Support Register */ 72 u8 mssr; /* Mailbox Search Status Register */ 73 u8 msmr; /* Mailbox Search Mode Register */ 74 u16 tsr; /* Time Stamp Register */ 75 u8 afsr; /* Acceptance Filter Support Register */ 76 u8 pad_857; 77 u8 tcr; /* Test Control Register */ 78 u8 pad_859[7]; 79 u8 ier; /* Interrupt Enable Register */ 80 u8 isr; /* Interrupt Status Register */ 81 u8 pad_862; 82 u8 mbsmr; /* Mailbox Search Mask Register */ 83}; 84 85struct rcar_can_priv { 86 struct can_priv can; /* Must be the first member! */ 87 struct net_device *ndev; 88 struct napi_struct napi; 89 struct rcar_can_regs __iomem *regs; 90 struct clk *clk; 91 struct clk *can_clk; 92 u8 tx_dlc[RCAR_CAN_FIFO_DEPTH]; 93 u32 tx_head; 94 u32 tx_tail; 95 u8 clock_select; 96 u8 ier; 97}; 98 99static const struct can_bittiming_const rcar_can_bittiming_const = { 100 .name = RCAR_CAN_DRV_NAME, 101 .tseg1_min = 4, 102 .tseg1_max = 16, 103 .tseg2_min = 2, 104 .tseg2_max = 8, 105 .sjw_max = 4, 106 .brp_min = 1, 107 .brp_max = 1024, 108 .brp_inc = 1, 109}; 110 111/* Control Register bits */ 112#define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */ 113#define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */ 114 /* at bus-off entry */ 115#define RCAR_CAN_CTLR_SLPM (1 << 10) 116#define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */ 117#define RCAR_CAN_CTLR_CANM_HALT (1 << 9) 118#define RCAR_CAN_CTLR_CANM_RESET (1 << 8) 119#define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8) 120#define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */ 121#define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */ 122#define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */ 123#define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */ 124 125/* Status Register bits */ 126#define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */ 127 128/* FIFO Received ID Compare Registers 0 and 1 bits */ 129#define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */ 130#define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */ 131 132/* Receive FIFO Control Register bits */ 133#define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */ 134#define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */ 135 136/* Transmit FIFO Control Register bits */ 137#define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */ 138 /* Number Status Bits */ 139#define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */ 140 /* Message Number Status Bits */ 141#define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */ 142 143#define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */ 144 /* for Rx mailboxes 0-31 */ 145#define RCAR_CAN_N_RX_MKREGS2 8 146 147/* Bit Configuration Register settings */ 148#define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20) 149#define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8) 150#define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4) 151#define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07) 152 153/* Mailbox and Mask Registers bits */ 154#define RCAR_CAN_IDE (1 << 31) 155#define RCAR_CAN_RTR (1 << 30) 156#define RCAR_CAN_SID_SHIFT 18 157 158/* Mailbox Interrupt Enable Register 1 bits */ 159#define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */ 160#define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */ 161 162/* Interrupt Enable Register bits */ 163#define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */ 164#define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */ 165 /* Enable Bit */ 166#define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */ 167 /* Enable Bit */ 168/* Interrupt Status Register bits */ 169#define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */ 170#define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */ 171 /* Status Bit */ 172#define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */ 173 /* Status Bit */ 174 175/* Error Interrupt Enable Register bits */ 176#define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */ 177#define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */ 178 /* Interrupt Enable */ 179#define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */ 180#define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */ 181#define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */ 182#define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */ 183#define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */ 184#define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */ 185 186/* Error Interrupt Factor Judge Register bits */ 187#define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */ 188#define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */ 189 /* Detect Flag */ 190#define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */ 191#define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */ 192#define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */ 193#define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */ 194#define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */ 195#define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */ 196 197/* Error Code Store Register bits */ 198#define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */ 199#define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */ 200#define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */ 201#define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */ 202#define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */ 203#define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */ 204#define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */ 205#define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */ 206 207#define RCAR_CAN_NAPI_WEIGHT 4 208#define MAX_STR_READS 0x100 209 210static void tx_failure_cleanup(struct net_device *ndev) 211{ 212 int i; 213 214 for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++) 215 can_free_echo_skb(ndev, i); 216} 217 218static void rcar_can_error(struct net_device *ndev) 219{ 220 struct rcar_can_priv *priv = netdev_priv(ndev); 221 struct net_device_stats *stats = &ndev->stats; 222 struct can_frame *cf; 223 struct sk_buff *skb; 224 u8 eifr, txerr = 0, rxerr = 0; 225 226 /* Propagate the error condition to the CAN stack */ 227 skb = alloc_can_err_skb(ndev, &cf); 228 229 eifr = readb(&priv->regs->eifr); 230 if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) { 231 txerr = readb(&priv->regs->tecr); 232 rxerr = readb(&priv->regs->recr); 233 if (skb) { 234 cf->can_id |= CAN_ERR_CRTL; 235 cf->data[6] = txerr; 236 cf->data[7] = rxerr; 237 } 238 } 239 if (eifr & RCAR_CAN_EIFR_BEIF) { 240 int rx_errors = 0, tx_errors = 0; 241 u8 ecsr; 242 243 netdev_dbg(priv->ndev, "Bus error interrupt:\n"); 244 if (skb) { 245 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 246 cf->data[2] = CAN_ERR_PROT_UNSPEC; 247 } 248 ecsr = readb(&priv->regs->ecsr); 249 if (ecsr & RCAR_CAN_ECSR_ADEF) { 250 netdev_dbg(priv->ndev, "ACK Delimiter Error\n"); 251 tx_errors++; 252 writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr); 253 if (skb) 254 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL; 255 } 256 if (ecsr & RCAR_CAN_ECSR_BE0F) { 257 netdev_dbg(priv->ndev, "Bit Error (dominant)\n"); 258 tx_errors++; 259 writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr); 260 if (skb) 261 cf->data[2] |= CAN_ERR_PROT_BIT0; 262 } 263 if (ecsr & RCAR_CAN_ECSR_BE1F) { 264 netdev_dbg(priv->ndev, "Bit Error (recessive)\n"); 265 tx_errors++; 266 writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr); 267 if (skb) 268 cf->data[2] |= CAN_ERR_PROT_BIT1; 269 } 270 if (ecsr & RCAR_CAN_ECSR_CEF) { 271 netdev_dbg(priv->ndev, "CRC Error\n"); 272 rx_errors++; 273 writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr); 274 if (skb) 275 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 276 } 277 if (ecsr & RCAR_CAN_ECSR_AEF) { 278 netdev_dbg(priv->ndev, "ACK Error\n"); 279 tx_errors++; 280 writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr); 281 if (skb) { 282 cf->can_id |= CAN_ERR_ACK; 283 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 284 } 285 } 286 if (ecsr & RCAR_CAN_ECSR_FEF) { 287 netdev_dbg(priv->ndev, "Form Error\n"); 288 rx_errors++; 289 writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr); 290 if (skb) 291 cf->data[2] |= CAN_ERR_PROT_FORM; 292 } 293 if (ecsr & RCAR_CAN_ECSR_SEF) { 294 netdev_dbg(priv->ndev, "Stuff Error\n"); 295 rx_errors++; 296 writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr); 297 if (skb) 298 cf->data[2] |= CAN_ERR_PROT_STUFF; 299 } 300 301 priv->can.can_stats.bus_error++; 302 ndev->stats.rx_errors += rx_errors; 303 ndev->stats.tx_errors += tx_errors; 304 writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr); 305 } 306 if (eifr & RCAR_CAN_EIFR_EWIF) { 307 netdev_dbg(priv->ndev, "Error warning interrupt\n"); 308 priv->can.state = CAN_STATE_ERROR_WARNING; 309 priv->can.can_stats.error_warning++; 310 /* Clear interrupt condition */ 311 writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr); 312 if (skb) 313 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING : 314 CAN_ERR_CRTL_RX_WARNING; 315 } 316 if (eifr & RCAR_CAN_EIFR_EPIF) { 317 netdev_dbg(priv->ndev, "Error passive interrupt\n"); 318 priv->can.state = CAN_STATE_ERROR_PASSIVE; 319 priv->can.can_stats.error_passive++; 320 /* Clear interrupt condition */ 321 writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr); 322 if (skb) 323 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE : 324 CAN_ERR_CRTL_RX_PASSIVE; 325 } 326 if (eifr & RCAR_CAN_EIFR_BOEIF) { 327 netdev_dbg(priv->ndev, "Bus-off entry interrupt\n"); 328 tx_failure_cleanup(ndev); 329 priv->ier = RCAR_CAN_IER_ERSIE; 330 writeb(priv->ier, &priv->regs->ier); 331 priv->can.state = CAN_STATE_BUS_OFF; 332 /* Clear interrupt condition */ 333 writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr); 334 can_bus_off(ndev); 335 if (skb) 336 cf->can_id |= CAN_ERR_BUSOFF; 337 } 338 if (eifr & RCAR_CAN_EIFR_ORIF) { 339 netdev_dbg(priv->ndev, "Receive overrun error interrupt\n"); 340 ndev->stats.rx_over_errors++; 341 ndev->stats.rx_errors++; 342 writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr); 343 if (skb) { 344 cf->can_id |= CAN_ERR_CRTL; 345 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 346 } 347 } 348 if (eifr & RCAR_CAN_EIFR_OLIF) { 349 netdev_dbg(priv->ndev, 350 "Overload Frame Transmission error interrupt\n"); 351 ndev->stats.rx_over_errors++; 352 ndev->stats.rx_errors++; 353 writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr); 354 if (skb) { 355 cf->can_id |= CAN_ERR_PROT; 356 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 357 } 358 } 359 360 if (skb) { 361 stats->rx_packets++; 362 stats->rx_bytes += cf->can_dlc; 363 netif_rx(skb); 364 } 365} 366 367static void rcar_can_tx_done(struct net_device *ndev) 368{ 369 struct rcar_can_priv *priv = netdev_priv(ndev); 370 struct net_device_stats *stats = &ndev->stats; 371 u8 isr; 372 373 while (1) { 374 u8 unsent = readb(&priv->regs->tfcr); 375 376 unsent = (unsent & RCAR_CAN_TFCR_TFUST) >> 377 RCAR_CAN_TFCR_TFUST_SHIFT; 378 if (priv->tx_head - priv->tx_tail <= unsent) 379 break; 380 stats->tx_packets++; 381 stats->tx_bytes += priv->tx_dlc[priv->tx_tail % 382 RCAR_CAN_FIFO_DEPTH]; 383 priv->tx_dlc[priv->tx_tail % RCAR_CAN_FIFO_DEPTH] = 0; 384 can_get_echo_skb(ndev, priv->tx_tail % RCAR_CAN_FIFO_DEPTH); 385 priv->tx_tail++; 386 netif_wake_queue(ndev); 387 } 388 /* Clear interrupt */ 389 isr = readb(&priv->regs->isr); 390 writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr); 391 can_led_event(ndev, CAN_LED_EVENT_TX); 392} 393 394static irqreturn_t rcar_can_interrupt(int irq, void *dev_id) 395{ 396 struct net_device *ndev = dev_id; 397 struct rcar_can_priv *priv = netdev_priv(ndev); 398 u8 isr; 399 400 isr = readb(&priv->regs->isr); 401 if (!(isr & priv->ier)) 402 return IRQ_NONE; 403 404 if (isr & RCAR_CAN_ISR_ERSF) 405 rcar_can_error(ndev); 406 407 if (isr & RCAR_CAN_ISR_TXFF) 408 rcar_can_tx_done(ndev); 409 410 if (isr & RCAR_CAN_ISR_RXFF) { 411 if (napi_schedule_prep(&priv->napi)) { 412 /* Disable Rx FIFO interrupts */ 413 priv->ier &= ~RCAR_CAN_IER_RXFIE; 414 writeb(priv->ier, &priv->regs->ier); 415 __napi_schedule(&priv->napi); 416 } 417 } 418 419 return IRQ_HANDLED; 420} 421 422static void rcar_can_set_bittiming(struct net_device *dev) 423{ 424 struct rcar_can_priv *priv = netdev_priv(dev); 425 struct can_bittiming *bt = &priv->can.bittiming; 426 u32 bcr; 427 428 bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) | 429 RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) | 430 RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1); 431 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access. 432 * All the registers are big-endian but they get byte-swapped on 32-bit 433 * read/write (but not on 8-bit, contrary to the manuals)... 434 */ 435 writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); 436} 437 438static void rcar_can_start(struct net_device *ndev) 439{ 440 struct rcar_can_priv *priv = netdev_priv(ndev); 441 u16 ctlr; 442 int i; 443 444 /* Set controller to known mode: 445 * - FIFO mailbox mode 446 * - accept all messages 447 * - overrun mode 448 * CAN is in sleep mode after MCU hardware or software reset. 449 */ 450 ctlr = readw(&priv->regs->ctlr); 451 ctlr &= ~RCAR_CAN_CTLR_SLPM; 452 writew(ctlr, &priv->regs->ctlr); 453 /* Go to reset mode */ 454 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 455 writew(ctlr, &priv->regs->ctlr); 456 for (i = 0; i < MAX_STR_READS; i++) { 457 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 458 break; 459 } 460 rcar_can_set_bittiming(ndev); 461 ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */ 462 ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */ 463 /* at bus-off */ 464 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */ 465 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */ 466 writew(ctlr, &priv->regs->ctlr); 467 468 /* Accept all SID and EID */ 469 writel(0, &priv->regs->mkr_2_9[6]); 470 writel(0, &priv->regs->mkr_2_9[7]); 471 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */ 472 writel(0, &priv->regs->mkivlr1); 473 /* Accept all frames */ 474 writel(0, &priv->regs->fidcr[0]); 475 writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]); 476 /* Enable and configure FIFO mailbox interrupts */ 477 writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1); 478 479 priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | 480 RCAR_CAN_IER_TXFIE; 481 writeb(priv->ier, &priv->regs->ier); 482 483 /* Accumulate error codes */ 484 writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr); 485 /* Enable error interrupts */ 486 writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE | 487 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ? 488 RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE | 489 RCAR_CAN_EIER_OLIE, &priv->regs->eier); 490 priv->can.state = CAN_STATE_ERROR_ACTIVE; 491 492 /* Go to operation mode */ 493 writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr); 494 for (i = 0; i < MAX_STR_READS; i++) { 495 if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)) 496 break; 497 } 498 /* Enable Rx and Tx FIFO */ 499 writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr); 500 writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr); 501} 502 503static int rcar_can_open(struct net_device *ndev) 504{ 505 struct rcar_can_priv *priv = netdev_priv(ndev); 506 int err; 507 508 err = clk_prepare_enable(priv->clk); 509 if (err) { 510 netdev_err(ndev, "failed to enable periperal clock, error %d\n", 511 err); 512 goto out; 513 } 514 err = clk_prepare_enable(priv->can_clk); 515 if (err) { 516 netdev_err(ndev, "failed to enable CAN clock, error %d\n", 517 err); 518 goto out_clock; 519 } 520 err = open_candev(ndev); 521 if (err) { 522 netdev_err(ndev, "open_candev() failed, error %d\n", err); 523 goto out_can_clock; 524 } 525 napi_enable(&priv->napi); 526 err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev); 527 if (err) { 528 netdev_err(ndev, "error requesting interrupt %x\n", ndev->irq); 529 goto out_close; 530 } 531 can_led_event(ndev, CAN_LED_EVENT_OPEN); 532 rcar_can_start(ndev); 533 netif_start_queue(ndev); 534 return 0; 535out_close: 536 napi_disable(&priv->napi); 537 close_candev(ndev); 538out_can_clock: 539 clk_disable_unprepare(priv->can_clk); 540out_clock: 541 clk_disable_unprepare(priv->clk); 542out: 543 return err; 544} 545 546static void rcar_can_stop(struct net_device *ndev) 547{ 548 struct rcar_can_priv *priv = netdev_priv(ndev); 549 u16 ctlr; 550 int i; 551 552 /* Go to (force) reset mode */ 553 ctlr = readw(&priv->regs->ctlr); 554 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 555 writew(ctlr, &priv->regs->ctlr); 556 for (i = 0; i < MAX_STR_READS; i++) { 557 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 558 break; 559 } 560 writel(0, &priv->regs->mier0); 561 writel(0, &priv->regs->mier1); 562 writeb(0, &priv->regs->ier); 563 writeb(0, &priv->regs->eier); 564 /* Go to sleep mode */ 565 ctlr |= RCAR_CAN_CTLR_SLPM; 566 writew(ctlr, &priv->regs->ctlr); 567 priv->can.state = CAN_STATE_STOPPED; 568} 569 570static int rcar_can_close(struct net_device *ndev) 571{ 572 struct rcar_can_priv *priv = netdev_priv(ndev); 573 574 netif_stop_queue(ndev); 575 rcar_can_stop(ndev); 576 free_irq(ndev->irq, ndev); 577 napi_disable(&priv->napi); 578 clk_disable_unprepare(priv->can_clk); 579 clk_disable_unprepare(priv->clk); 580 close_candev(ndev); 581 can_led_event(ndev, CAN_LED_EVENT_STOP); 582 return 0; 583} 584 585static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb, 586 struct net_device *ndev) 587{ 588 struct rcar_can_priv *priv = netdev_priv(ndev); 589 struct can_frame *cf = (struct can_frame *)skb->data; 590 u32 data, i; 591 592 if (can_dropped_invalid_skb(ndev, skb)) 593 return NETDEV_TX_OK; 594 595 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ 596 data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE; 597 else /* Standard frame format */ 598 data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT; 599 600 if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */ 601 data |= RCAR_CAN_RTR; 602 } else { 603 for (i = 0; i < cf->can_dlc; i++) 604 writeb(cf->data[i], 605 &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]); 606 } 607 608 writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id); 609 610 writeb(cf->can_dlc, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc); 611 612 priv->tx_dlc[priv->tx_head % RCAR_CAN_FIFO_DEPTH] = cf->can_dlc; 613 can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH); 614 priv->tx_head++; 615 /* Start Tx: write 0xff to the TFPCR register to increment 616 * the CPU-side pointer for the transmit FIFO to the next 617 * mailbox location 618 */ 619 writeb(0xff, &priv->regs->tfpcr); 620 /* Stop the queue if we've filled all FIFO entries */ 621 if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH) 622 netif_stop_queue(ndev); 623 624 return NETDEV_TX_OK; 625} 626 627static const struct net_device_ops rcar_can_netdev_ops = { 628 .ndo_open = rcar_can_open, 629 .ndo_stop = rcar_can_close, 630 .ndo_start_xmit = rcar_can_start_xmit, 631 .ndo_change_mtu = can_change_mtu, 632}; 633 634static void rcar_can_rx_pkt(struct rcar_can_priv *priv) 635{ 636 struct net_device_stats *stats = &priv->ndev->stats; 637 struct can_frame *cf; 638 struct sk_buff *skb; 639 u32 data; 640 u8 dlc; 641 642 skb = alloc_can_skb(priv->ndev, &cf); 643 if (!skb) { 644 stats->rx_dropped++; 645 return; 646 } 647 648 data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id); 649 if (data & RCAR_CAN_IDE) 650 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; 651 else 652 cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK; 653 654 dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc); 655 cf->can_dlc = get_can_dlc(dlc); 656 if (data & RCAR_CAN_RTR) { 657 cf->can_id |= CAN_RTR_FLAG; 658 } else { 659 for (dlc = 0; dlc < cf->can_dlc; dlc++) 660 cf->data[dlc] = 661 readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]); 662 } 663 664 can_led_event(priv->ndev, CAN_LED_EVENT_RX); 665 666 stats->rx_bytes += cf->can_dlc; 667 stats->rx_packets++; 668 netif_receive_skb(skb); 669} 670 671static int rcar_can_rx_poll(struct napi_struct *napi, int quota) 672{ 673 struct rcar_can_priv *priv = container_of(napi, 674 struct rcar_can_priv, napi); 675 int num_pkts; 676 677 for (num_pkts = 0; num_pkts < quota; num_pkts++) { 678 u8 rfcr, isr; 679 680 isr = readb(&priv->regs->isr); 681 /* Clear interrupt bit */ 682 if (isr & RCAR_CAN_ISR_RXFF) 683 writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr); 684 rfcr = readb(&priv->regs->rfcr); 685 if (rfcr & RCAR_CAN_RFCR_RFEST) 686 break; 687 rcar_can_rx_pkt(priv); 688 /* Write 0xff to the RFPCR register to increment 689 * the CPU-side pointer for the receive FIFO 690 * to the next mailbox location 691 */ 692 writeb(0xff, &priv->regs->rfpcr); 693 } 694 /* All packets processed */ 695 if (num_pkts < quota) { 696 napi_complete(napi); 697 priv->ier |= RCAR_CAN_IER_RXFIE; 698 writeb(priv->ier, &priv->regs->ier); 699 } 700 return num_pkts; 701} 702 703static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 704{ 705 switch (mode) { 706 case CAN_MODE_START: 707 rcar_can_start(ndev); 708 netif_wake_queue(ndev); 709 return 0; 710 default: 711 return -EOPNOTSUPP; 712 } 713} 714 715static int rcar_can_get_berr_counter(const struct net_device *dev, 716 struct can_berr_counter *bec) 717{ 718 struct rcar_can_priv *priv = netdev_priv(dev); 719 int err; 720 721 err = clk_prepare_enable(priv->clk); 722 if (err) 723 return err; 724 bec->txerr = readb(&priv->regs->tecr); 725 bec->rxerr = readb(&priv->regs->recr); 726 clk_disable_unprepare(priv->clk); 727 return 0; 728} 729 730static const char * const clock_names[] = { 731 [CLKR_CLKP1] = "clkp1", 732 [CLKR_CLKP2] = "clkp2", 733 [CLKR_CLKEXT] = "can_clk", 734}; 735 736static int rcar_can_probe(struct platform_device *pdev) 737{ 738 struct rcar_can_platform_data *pdata; 739 struct rcar_can_priv *priv; 740 struct net_device *ndev; 741 struct resource *mem; 742 void __iomem *addr; 743 u32 clock_select = CLKR_CLKP1; 744 int err = -ENODEV; 745 int irq; 746 747 if (pdev->dev.of_node) { 748 of_property_read_u32(pdev->dev.of_node, 749 "renesas,can-clock-select", &clock_select); 750 } else { 751 pdata = dev_get_platdata(&pdev->dev); 752 if (!pdata) { 753 dev_err(&pdev->dev, "No platform data provided!\n"); 754 goto fail; 755 } 756 clock_select = pdata->clock_select; 757 } 758 759 irq = platform_get_irq(pdev, 0); 760 if (!irq) { 761 dev_err(&pdev->dev, "No IRQ resource\n"); 762 goto fail; 763 } 764 765 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 766 addr = devm_ioremap_resource(&pdev->dev, mem); 767 if (IS_ERR(addr)) { 768 err = PTR_ERR(addr); 769 goto fail; 770 } 771 772 ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH); 773 if (!ndev) { 774 dev_err(&pdev->dev, "alloc_candev() failed\n"); 775 err = -ENOMEM; 776 goto fail; 777 } 778 779 priv = netdev_priv(ndev); 780 781 priv->clk = devm_clk_get(&pdev->dev, "clkp1"); 782 if (IS_ERR(priv->clk)) { 783 err = PTR_ERR(priv->clk); 784 dev_err(&pdev->dev, "cannot get peripheral clock: %d\n", err); 785 goto fail_clk; 786 } 787 788 if (clock_select >= ARRAY_SIZE(clock_names)) { 789 err = -EINVAL; 790 dev_err(&pdev->dev, "invalid CAN clock selected\n"); 791 goto fail_clk; 792 } 793 priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]); 794 if (IS_ERR(priv->can_clk)) { 795 err = PTR_ERR(priv->can_clk); 796 dev_err(&pdev->dev, "cannot get CAN clock: %d\n", err); 797 goto fail_clk; 798 } 799 800 ndev->netdev_ops = &rcar_can_netdev_ops; 801 ndev->irq = irq; 802 ndev->flags |= IFF_ECHO; 803 priv->ndev = ndev; 804 priv->regs = addr; 805 priv->clock_select = clock_select; 806 priv->can.clock.freq = clk_get_rate(priv->can_clk); 807 priv->can.bittiming_const = &rcar_can_bittiming_const; 808 priv->can.do_set_mode = rcar_can_do_set_mode; 809 priv->can.do_get_berr_counter = rcar_can_get_berr_counter; 810 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING; 811 platform_set_drvdata(pdev, ndev); 812 SET_NETDEV_DEV(ndev, &pdev->dev); 813 814 netif_napi_add(ndev, &priv->napi, rcar_can_rx_poll, 815 RCAR_CAN_NAPI_WEIGHT); 816 err = register_candev(ndev); 817 if (err) { 818 dev_err(&pdev->dev, "register_candev() failed, error %d\n", 819 err); 820 goto fail_candev; 821 } 822 823 devm_can_led_init(ndev); 824 825 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n", 826 priv->regs, ndev->irq); 827 828 return 0; 829fail_candev: 830 netif_napi_del(&priv->napi); 831fail_clk: 832 free_candev(ndev); 833fail: 834 return err; 835} 836 837static int rcar_can_remove(struct platform_device *pdev) 838{ 839 struct net_device *ndev = platform_get_drvdata(pdev); 840 struct rcar_can_priv *priv = netdev_priv(ndev); 841 842 unregister_candev(ndev); 843 netif_napi_del(&priv->napi); 844 free_candev(ndev); 845 return 0; 846} 847 848static int __maybe_unused rcar_can_suspend(struct device *dev) 849{ 850 struct net_device *ndev = dev_get_drvdata(dev); 851 struct rcar_can_priv *priv = netdev_priv(ndev); 852 u16 ctlr; 853 854 if (netif_running(ndev)) { 855 netif_stop_queue(ndev); 856 netif_device_detach(ndev); 857 } 858 ctlr = readw(&priv->regs->ctlr); 859 ctlr |= RCAR_CAN_CTLR_CANM_HALT; 860 writew(ctlr, &priv->regs->ctlr); 861 ctlr |= RCAR_CAN_CTLR_SLPM; 862 writew(ctlr, &priv->regs->ctlr); 863 priv->can.state = CAN_STATE_SLEEPING; 864 865 clk_disable(priv->clk); 866 return 0; 867} 868 869static int __maybe_unused rcar_can_resume(struct device *dev) 870{ 871 struct net_device *ndev = dev_get_drvdata(dev); 872 struct rcar_can_priv *priv = netdev_priv(ndev); 873 u16 ctlr; 874 int err; 875 876 err = clk_enable(priv->clk); 877 if (err) { 878 netdev_err(ndev, "clk_enable() failed, error %d\n", err); 879 return err; 880 } 881 882 ctlr = readw(&priv->regs->ctlr); 883 ctlr &= ~RCAR_CAN_CTLR_SLPM; 884 writew(ctlr, &priv->regs->ctlr); 885 ctlr &= ~RCAR_CAN_CTLR_CANM; 886 writew(ctlr, &priv->regs->ctlr); 887 priv->can.state = CAN_STATE_ERROR_ACTIVE; 888 889 if (netif_running(ndev)) { 890 netif_device_attach(ndev); 891 netif_start_queue(ndev); 892 } 893 return 0; 894} 895 896static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume); 897 898static const struct of_device_id rcar_can_of_table[] __maybe_unused = { 899 { .compatible = "renesas,can-r8a7778" }, 900 { .compatible = "renesas,can-r8a7779" }, 901 { .compatible = "renesas,can-r8a7790" }, 902 { .compatible = "renesas,can-r8a7791" }, 903 { } 904}; 905MODULE_DEVICE_TABLE(of, rcar_can_of_table); 906 907static struct platform_driver rcar_can_driver = { 908 .driver = { 909 .name = RCAR_CAN_DRV_NAME, 910 .owner = THIS_MODULE, 911 .of_match_table = of_match_ptr(rcar_can_of_table), 912 .pm = &rcar_can_pm_ops, 913 }, 914 .probe = rcar_can_probe, 915 .remove = rcar_can_remove, 916}; 917 918module_platform_driver(rcar_can_driver); 919 920MODULE_AUTHOR("Cogent Embedded, Inc."); 921MODULE_LICENSE("GPL"); 922MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC"); 923MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME); 924