ems_pci.c revision 3c8ac0f2ad53a96ac58efe7c98fac2986d081dfc 
1/*
2 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
3 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
4 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the version 2 of the GNU General Public License
8 * as published by the Free Software Foundation
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/interrupt.h>
23#include <linux/netdevice.h>
24#include <linux/delay.h>
25#include <linux/slab.h>
26#include <linux/pci.h>
27#include <linux/can/dev.h>
28#include <linux/io.h>
29
30#include "sja1000.h"
31
32#define DRV_NAME  "ems_pci"
33
34MODULE_AUTHOR("Sebastian Haas <haas@ems-wuenche.com>");
35MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
36MODULE_SUPPORTED_DEVICE("EMS CPC-PCI/PCIe/104P CAN card");
37MODULE_LICENSE("GPL v2");
38
39#define EMS_PCI_V1_MAX_CHAN 2
40#define EMS_PCI_V2_MAX_CHAN 4
41#define EMS_PCI_MAX_CHAN    EMS_PCI_V2_MAX_CHAN
42
43struct ems_pci_card {
44	int version;
45	int channels;
46
47	struct pci_dev *pci_dev;
48	struct net_device *net_dev[EMS_PCI_MAX_CHAN];
49
50	void __iomem *conf_addr;
51	void __iomem *base_addr;
52};
53
54#define EMS_PCI_CAN_CLOCK (16000000 / 2)
55
56/*
57 * Register definitions and descriptions are from LinCAN 0.3.3.
58 *
59 * PSB4610 PITA-2 bridge control registers
60 */
61#define PITA2_ICR           0x00	/* Interrupt Control Register */
62#define PITA2_ICR_INT0      0x00000002	/* [RC] INT0 Active/Clear */
63#define PITA2_ICR_INT0_EN   0x00020000	/* [RW] Enable INT0 */
64
65#define PITA2_MISC          0x1c	/* Miscellaneous Register */
66#define PITA2_MISC_CONFIG   0x04000000	/* Multiplexed parallel interface */
67
68/*
69 * Register definitions for the PLX 9030
70 */
71#define PLX_ICSR            0x4c   /* Interrupt Control/Status register */
72#define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
73#define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
74#define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
75#define PLX_ICSR_ENA_CLR    (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \
76			     PLX_ICSR_LINTI1_CLR)
77
78/*
79 * The board configuration is probably following:
80 * RX1 is connected to ground.
81 * TX1 is not connected.
82 * CLKO is not connected.
83 * Setting the OCR register to 0xDA is a good idea.
84 * This means normal output mode, push-pull and the correct polarity.
85 */
86#define EMS_PCI_OCR         (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
87
88/*
89 * In the CDR register, you should set CBP to 1.
90 * You will probably also want to set the clock divider value to 7
91 * (meaning direct oscillator output) because the second SJA1000 chip
92 * is driven by the first one CLKOUT output.
93 */
94#define EMS_PCI_CDR             (CDR_CBP | CDR_CLKOUT_MASK)
95
96#define EMS_PCI_V1_BASE_BAR     1
97#define EMS_PCI_V1_CONF_SIZE    4096 /* size of PITA control area */
98#define EMS_PCI_V2_BASE_BAR     2
99#define EMS_PCI_V2_CONF_SIZE    128 /* size of PLX control area */
100#define EMS_PCI_CAN_BASE_OFFSET 0x400 /* offset where the controllers starts */
101#define EMS_PCI_CAN_CTRL_SIZE   0x200 /* memory size for each controller */
102
103#define EMS_PCI_BASE_SIZE  4096 /* size of controller area */
104
105static DEFINE_PCI_DEVICE_TABLE(ems_pci_tbl) = {
106	/* CPC-PCI v1 */
107	{PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
108	/* CPC-PCI v2 */
109	{PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
110	/* CPC-104P v2 */
111	{PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
112	{0,}
113};
114MODULE_DEVICE_TABLE(pci, ems_pci_tbl);
115
116/*
117 * Helper to read internal registers from card logic (not CAN)
118 */
119static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port)
120{
121	return readb(card->base_addr + (port * 4));
122}
123
124static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port)
125{
126	return readb(priv->reg_base + (port * 4));
127}
128
129static void ems_pci_v1_write_reg(const struct sja1000_priv *priv,
130				 int port, u8 val)
131{
132	writeb(val, priv->reg_base + (port * 4));
133}
134
135static void ems_pci_v1_post_irq(const struct sja1000_priv *priv)
136{
137	struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
138
139	/* reset int flag of pita */
140	writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
141	       card->conf_addr + PITA2_ICR);
142}
143
144static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port)
145{
146	return readb(priv->reg_base + port);
147}
148
149static void ems_pci_v2_write_reg(const struct sja1000_priv *priv,
150				 int port, u8 val)
151{
152	writeb(val, priv->reg_base + port);
153}
154
155static void ems_pci_v2_post_irq(const struct sja1000_priv *priv)
156{
157	struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
158
159	writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
160}
161
162/*
163 * Check if a CAN controller is present at the specified location
164 * by trying to set 'em into the PeliCAN mode
165 */
166static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
167{
168	unsigned char res;
169
170	/* Make sure SJA1000 is in reset mode */
171	priv->write_reg(priv, REG_MOD, 1);
172
173	priv->write_reg(priv, REG_CDR, CDR_PELICAN);
174
175	/* read reset-values */
176	res = priv->read_reg(priv, REG_CDR);
177
178	if (res == CDR_PELICAN)
179		return 1;
180
181	return 0;
182}
183
184static void ems_pci_del_card(struct pci_dev *pdev)
185{
186	struct ems_pci_card *card = pci_get_drvdata(pdev);
187	struct net_device *dev;
188	int i = 0;
189
190	for (i = 0; i < card->channels; i++) {
191		dev = card->net_dev[i];
192
193		if (!dev)
194			continue;
195
196		dev_info(&pdev->dev, "Removing %s.\n", dev->name);
197		unregister_sja1000dev(dev);
198		free_sja1000dev(dev);
199	}
200
201	if (card->base_addr != NULL)
202		pci_iounmap(card->pci_dev, card->base_addr);
203
204	if (card->conf_addr != NULL)
205		pci_iounmap(card->pci_dev, card->conf_addr);
206
207	kfree(card);
208
209	pci_disable_device(pdev);
210	pci_set_drvdata(pdev, NULL);
211}
212
213static void ems_pci_card_reset(struct ems_pci_card *card)
214{
215	/* Request board reset */
216	writeb(0, card->base_addr);
217}
218
219/*
220 * Probe PCI device for EMS CAN signature and register each available
221 * CAN channel to SJA1000 Socket-CAN subsystem.
222 */
223static int ems_pci_add_card(struct pci_dev *pdev,
224					const struct pci_device_id *ent)
225{
226	struct sja1000_priv *priv;
227	struct net_device *dev;
228	struct ems_pci_card *card;
229	int max_chan, conf_size, base_bar;
230	int err, i;
231
232	/* Enabling PCI device */
233	if (pci_enable_device(pdev) < 0) {
234		dev_err(&pdev->dev, "Enabling PCI device failed\n");
235		return -ENODEV;
236	}
237
238	/* Allocating card structures to hold addresses, ... */
239	card = kzalloc(sizeof(struct ems_pci_card), GFP_KERNEL);
240	if (card == NULL) {
241		dev_err(&pdev->dev, "Unable to allocate memory\n");
242		pci_disable_device(pdev);
243		return -ENOMEM;
244	}
245
246	pci_set_drvdata(pdev, card);
247
248	card->pci_dev = pdev;
249
250	card->channels = 0;
251
252	if (pdev->vendor == PCI_VENDOR_ID_PLX) {
253		card->version = 2; /* CPC-PCI v2 */
254		max_chan = EMS_PCI_V2_MAX_CHAN;
255		base_bar = EMS_PCI_V2_BASE_BAR;
256		conf_size = EMS_PCI_V2_CONF_SIZE;
257	} else {
258		card->version = 1; /* CPC-PCI v1 */
259		max_chan = EMS_PCI_V1_MAX_CHAN;
260		base_bar = EMS_PCI_V1_BASE_BAR;
261		conf_size = EMS_PCI_V1_CONF_SIZE;
262	}
263
264	/* Remap configuration space and controller memory area */
265	card->conf_addr = pci_iomap(pdev, 0, conf_size);
266	if (card->conf_addr == NULL) {
267		err = -ENOMEM;
268		goto failure_cleanup;
269	}
270
271	card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE);
272	if (card->base_addr == NULL) {
273		err = -ENOMEM;
274		goto failure_cleanup;
275	}
276
277	if (card->version == 1) {
278		/* Configure PITA-2 parallel interface (enable MUX) */
279		writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);
280
281		/* Check for unique EMS CAN signature */
282		if (ems_pci_v1_readb(card, 0) != 0x55 ||
283		    ems_pci_v1_readb(card, 1) != 0xAA ||
284		    ems_pci_v1_readb(card, 2) != 0x01 ||
285		    ems_pci_v1_readb(card, 3) != 0xCB ||
286		    ems_pci_v1_readb(card, 4) != 0x11) {
287			dev_err(&pdev->dev,
288				"Not EMS Dr. Thomas Wuensche interface\n");
289			err = -ENODEV;
290			goto failure_cleanup;
291		}
292	}
293
294	ems_pci_card_reset(card);
295
296	/* Detect available channels */
297	for (i = 0; i < max_chan; i++) {
298		dev = alloc_sja1000dev(0);
299		if (dev == NULL) {
300			err = -ENOMEM;
301			goto failure_cleanup;
302		}
303
304		card->net_dev[i] = dev;
305		priv = netdev_priv(dev);
306		priv->priv = card;
307		priv->irq_flags = IRQF_SHARED;
308
309		dev->irq = pdev->irq;
310		priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET
311					+ (i * EMS_PCI_CAN_CTRL_SIZE);
312		if (card->version == 1) {
313			priv->read_reg  = ems_pci_v1_read_reg;
314			priv->write_reg = ems_pci_v1_write_reg;
315			priv->post_irq  = ems_pci_v1_post_irq;
316		} else {
317			priv->read_reg  = ems_pci_v2_read_reg;
318			priv->write_reg = ems_pci_v2_write_reg;
319			priv->post_irq  = ems_pci_v2_post_irq;
320		}
321
322		/* Check if channel is present */
323		if (ems_pci_check_chan(priv)) {
324			priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
325			priv->ocr = EMS_PCI_OCR;
326			priv->cdr = EMS_PCI_CDR;
327
328			SET_NETDEV_DEV(dev, &pdev->dev);
329
330			if (card->version == 1)
331				/* reset int flag of pita */
332				writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
333				       card->conf_addr + PITA2_ICR);
334			else
335				/* enable IRQ in PLX 9030 */
336				writel(PLX_ICSR_ENA_CLR,
337				       card->conf_addr + PLX_ICSR);
338
339			/* Register SJA1000 device */
340			err = register_sja1000dev(dev);
341			if (err) {
342				dev_err(&pdev->dev, "Registering device failed "
343							"(err=%d)\n", err);
344				free_sja1000dev(dev);
345				goto failure_cleanup;
346			}
347
348			card->channels++;
349
350			dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n",
351					i + 1, priv->reg_base, dev->irq);
352		} else {
353			free_sja1000dev(dev);
354		}
355	}
356
357	return 0;
358
359failure_cleanup:
360	dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
361
362	ems_pci_del_card(pdev);
363
364	return err;
365}
366
367static struct pci_driver ems_pci_driver = {
368	.name = DRV_NAME,
369	.id_table = ems_pci_tbl,
370	.probe = ems_pci_add_card,
371	.remove = ems_pci_del_card,
372};
373
374module_pci_driver(ems_pci_driver);
375