ems_pci.c revision 9baa3c34ac4e27f7e062f266f50cc5dbea26a6c1 
1/*
2 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
3 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
4 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the version 2 of the GNU General Public License
8 * as published by the Free Software Foundation
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/interrupt.h>
22#include <linux/netdevice.h>
23#include <linux/delay.h>
24#include <linux/slab.h>
25#include <linux/pci.h>
26#include <linux/can/dev.h>
27#include <linux/io.h>
28
29#include "sja1000.h"
30
31#define DRV_NAME  "ems_pci"
32
33MODULE_AUTHOR("Sebastian Haas <haas@ems-wuenche.com>");
34MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
35MODULE_SUPPORTED_DEVICE("EMS CPC-PCI/PCIe/104P CAN card");
36MODULE_LICENSE("GPL v2");
37
38#define EMS_PCI_V1_MAX_CHAN 2
39#define EMS_PCI_V2_MAX_CHAN 4
40#define EMS_PCI_MAX_CHAN    EMS_PCI_V2_MAX_CHAN
41
42struct ems_pci_card {
43	int version;
44	int channels;
45
46	struct pci_dev *pci_dev;
47	struct net_device *net_dev[EMS_PCI_MAX_CHAN];
48
49	void __iomem *conf_addr;
50	void __iomem *base_addr;
51};
52
53#define EMS_PCI_CAN_CLOCK (16000000 / 2)
54
55/*
56 * Register definitions and descriptions are from LinCAN 0.3.3.
57 *
58 * PSB4610 PITA-2 bridge control registers
59 */
60#define PITA2_ICR           0x00	/* Interrupt Control Register */
61#define PITA2_ICR_INT0      0x00000002	/* [RC] INT0 Active/Clear */
62#define PITA2_ICR_INT0_EN   0x00020000	/* [RW] Enable INT0 */
63
64#define PITA2_MISC          0x1c	/* Miscellaneous Register */
65#define PITA2_MISC_CONFIG   0x04000000	/* Multiplexed parallel interface */
66
67/*
68 * Register definitions for the PLX 9030
69 */
70#define PLX_ICSR            0x4c   /* Interrupt Control/Status register */
71#define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
72#define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
73#define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
74#define PLX_ICSR_ENA_CLR    (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \
75			     PLX_ICSR_LINTI1_CLR)
76
77/*
78 * The board configuration is probably following:
79 * RX1 is connected to ground.
80 * TX1 is not connected.
81 * CLKO is not connected.
82 * Setting the OCR register to 0xDA is a good idea.
83 * This means normal output mode, push-pull and the correct polarity.
84 */
85#define EMS_PCI_OCR         (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
86
87/*
88 * In the CDR register, you should set CBP to 1.
89 * You will probably also want to set the clock divider value to 7
90 * (meaning direct oscillator output) because the second SJA1000 chip
91 * is driven by the first one CLKOUT output.
92 */
93#define EMS_PCI_CDR             (CDR_CBP | CDR_CLKOUT_MASK)
94
95#define EMS_PCI_V1_BASE_BAR     1
96#define EMS_PCI_V1_CONF_SIZE    4096 /* size of PITA control area */
97#define EMS_PCI_V2_BASE_BAR     2
98#define EMS_PCI_V2_CONF_SIZE    128 /* size of PLX control area */
99#define EMS_PCI_CAN_BASE_OFFSET 0x400 /* offset where the controllers starts */
100#define EMS_PCI_CAN_CTRL_SIZE   0x200 /* memory size for each controller */
101
102#define EMS_PCI_BASE_SIZE  4096 /* size of controller area */
103
104static const struct pci_device_id ems_pci_tbl[] = {
105	/* CPC-PCI v1 */
106	{PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
107	/* CPC-PCI v2 */
108	{PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
109	/* CPC-104P v2 */
110	{PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
111	{0,}
112};
113MODULE_DEVICE_TABLE(pci, ems_pci_tbl);
114
115/*
116 * Helper to read internal registers from card logic (not CAN)
117 */
118static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port)
119{
120	return readb(card->base_addr + (port * 4));
121}
122
123static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port)
124{
125	return readb(priv->reg_base + (port * 4));
126}
127
128static void ems_pci_v1_write_reg(const struct sja1000_priv *priv,
129				 int port, u8 val)
130{
131	writeb(val, priv->reg_base + (port * 4));
132}
133
134static void ems_pci_v1_post_irq(const struct sja1000_priv *priv)
135{
136	struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
137
138	/* reset int flag of pita */
139	writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
140	       card->conf_addr + PITA2_ICR);
141}
142
143static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port)
144{
145	return readb(priv->reg_base + port);
146}
147
148static void ems_pci_v2_write_reg(const struct sja1000_priv *priv,
149				 int port, u8 val)
150{
151	writeb(val, priv->reg_base + port);
152}
153
154static void ems_pci_v2_post_irq(const struct sja1000_priv *priv)
155{
156	struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
157
158	writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
159}
160
161/*
162 * Check if a CAN controller is present at the specified location
163 * by trying to set 'em into the PeliCAN mode
164 */
165static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
166{
167	unsigned char res;
168
169	/* Make sure SJA1000 is in reset mode */
170	priv->write_reg(priv, SJA1000_MOD, 1);
171
172	priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);
173
174	/* read reset-values */
175	res = priv->read_reg(priv, SJA1000_CDR);
176
177	if (res == CDR_PELICAN)
178		return 1;
179
180	return 0;
181}
182
183static void ems_pci_del_card(struct pci_dev *pdev)
184{
185	struct ems_pci_card *card = pci_get_drvdata(pdev);
186	struct net_device *dev;
187	int i = 0;
188
189	for (i = 0; i < card->channels; i++) {
190		dev = card->net_dev[i];
191
192		if (!dev)
193			continue;
194
195		dev_info(&pdev->dev, "Removing %s.\n", dev->name);
196		unregister_sja1000dev(dev);
197		free_sja1000dev(dev);
198	}
199
200	if (card->base_addr != NULL)
201		pci_iounmap(card->pci_dev, card->base_addr);
202
203	if (card->conf_addr != NULL)
204		pci_iounmap(card->pci_dev, card->conf_addr);
205
206	kfree(card);
207
208	pci_disable_device(pdev);
209}
210
211static void ems_pci_card_reset(struct ems_pci_card *card)
212{
213	/* Request board reset */
214	writeb(0, card->base_addr);
215}
216
217/*
218 * Probe PCI device for EMS CAN signature and register each available
219 * CAN channel to SJA1000 Socket-CAN subsystem.
220 */
221static int ems_pci_add_card(struct pci_dev *pdev,
222			    const struct pci_device_id *ent)
223{
224	struct sja1000_priv *priv;
225	struct net_device *dev;
226	struct ems_pci_card *card;
227	int max_chan, conf_size, base_bar;
228	int err, i;
229
230	/* Enabling PCI device */
231	if (pci_enable_device(pdev) < 0) {
232		dev_err(&pdev->dev, "Enabling PCI device failed\n");
233		return -ENODEV;
234	}
235
236	/* Allocating card structures to hold addresses, ... */
237	card = kzalloc(sizeof(struct ems_pci_card), GFP_KERNEL);
238	if (card == NULL) {
239		pci_disable_device(pdev);
240		return -ENOMEM;
241	}
242
243	pci_set_drvdata(pdev, card);
244
245	card->pci_dev = pdev;
246
247	card->channels = 0;
248
249	if (pdev->vendor == PCI_VENDOR_ID_PLX) {
250		card->version = 2; /* CPC-PCI v2 */
251		max_chan = EMS_PCI_V2_MAX_CHAN;
252		base_bar = EMS_PCI_V2_BASE_BAR;
253		conf_size = EMS_PCI_V2_CONF_SIZE;
254	} else {
255		card->version = 1; /* CPC-PCI v1 */
256		max_chan = EMS_PCI_V1_MAX_CHAN;
257		base_bar = EMS_PCI_V1_BASE_BAR;
258		conf_size = EMS_PCI_V1_CONF_SIZE;
259	}
260
261	/* Remap configuration space and controller memory area */
262	card->conf_addr = pci_iomap(pdev, 0, conf_size);
263	if (card->conf_addr == NULL) {
264		err = -ENOMEM;
265		goto failure_cleanup;
266	}
267
268	card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE);
269	if (card->base_addr == NULL) {
270		err = -ENOMEM;
271		goto failure_cleanup;
272	}
273
274	if (card->version == 1) {
275		/* Configure PITA-2 parallel interface (enable MUX) */
276		writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);
277
278		/* Check for unique EMS CAN signature */
279		if (ems_pci_v1_readb(card, 0) != 0x55 ||
280		    ems_pci_v1_readb(card, 1) != 0xAA ||
281		    ems_pci_v1_readb(card, 2) != 0x01 ||
282		    ems_pci_v1_readb(card, 3) != 0xCB ||
283		    ems_pci_v1_readb(card, 4) != 0x11) {
284			dev_err(&pdev->dev,
285				"Not EMS Dr. Thomas Wuensche interface\n");
286			err = -ENODEV;
287			goto failure_cleanup;
288		}
289	}
290
291	ems_pci_card_reset(card);
292
293	/* Detect available channels */
294	for (i = 0; i < max_chan; i++) {
295		dev = alloc_sja1000dev(0);
296		if (dev == NULL) {
297			err = -ENOMEM;
298			goto failure_cleanup;
299		}
300
301		card->net_dev[i] = dev;
302		priv = netdev_priv(dev);
303		priv->priv = card;
304		priv->irq_flags = IRQF_SHARED;
305
306		dev->irq = pdev->irq;
307		priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET
308					+ (i * EMS_PCI_CAN_CTRL_SIZE);
309		if (card->version == 1) {
310			priv->read_reg  = ems_pci_v1_read_reg;
311			priv->write_reg = ems_pci_v1_write_reg;
312			priv->post_irq  = ems_pci_v1_post_irq;
313		} else {
314			priv->read_reg  = ems_pci_v2_read_reg;
315			priv->write_reg = ems_pci_v2_write_reg;
316			priv->post_irq  = ems_pci_v2_post_irq;
317		}
318
319		/* Check if channel is present */
320		if (ems_pci_check_chan(priv)) {
321			priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
322			priv->ocr = EMS_PCI_OCR;
323			priv->cdr = EMS_PCI_CDR;
324
325			SET_NETDEV_DEV(dev, &pdev->dev);
326			dev->dev_id = i;
327
328			if (card->version == 1)
329				/* reset int flag of pita */
330				writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
331				       card->conf_addr + PITA2_ICR);
332			else
333				/* enable IRQ in PLX 9030 */
334				writel(PLX_ICSR_ENA_CLR,
335				       card->conf_addr + PLX_ICSR);
336
337			/* Register SJA1000 device */
338			err = register_sja1000dev(dev);
339			if (err) {
340				dev_err(&pdev->dev, "Registering device failed "
341							"(err=%d)\n", err);
342				free_sja1000dev(dev);
343				goto failure_cleanup;
344			}
345
346			card->channels++;
347
348			dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n",
349					i + 1, priv->reg_base, dev->irq);
350		} else {
351			free_sja1000dev(dev);
352		}
353	}
354
355	return 0;
356
357failure_cleanup:
358	dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
359
360	ems_pci_del_card(pdev);
361
362	return err;
363}
364
365static struct pci_driver ems_pci_driver = {
366	.name = DRV_NAME,
367	.id_table = ems_pci_tbl,
368	.probe = ems_pci_add_card,
369	.remove = ems_pci_del_card,
370};
371
372module_pci_driver(ems_pci_driver);
373