ems_pci.c revision dd52856ba24ed2f67679c86f207e5a9bab1eb93b 
1/*
2 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
3 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
4 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the version 2 of the GNU General Public License
8 * as published by the Free Software Foundation
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/interrupt.h>
23#include <linux/netdevice.h>
24#include <linux/delay.h>
25#include <linux/pci.h>
26#include <linux/can.h>
27#include <linux/can/dev.h>
28#include <linux/io.h>
29
30#include "sja1000.h"
31
32#define DRV_NAME  "ems_pci"
33
34MODULE_AUTHOR("Sebastian Haas <haas@ems-wuenche.com>");
35MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
36MODULE_SUPPORTED_DEVICE("EMS CPC-PCI/PCIe/104P CAN card");
37MODULE_LICENSE("GPL v2");
38
39#define EMS_PCI_V1_MAX_CHAN 2
40#define EMS_PCI_V2_MAX_CHAN 4
41#define EMS_PCI_MAX_CHAN    EMS_PCI_V2_MAX_CHAN
42
43struct ems_pci_card {
44	int version;
45	int channels;
46
47	struct pci_dev *pci_dev;
48	struct net_device *net_dev[EMS_PCI_MAX_CHAN];
49
50	void __iomem *conf_addr;
51	void __iomem *base_addr;
52};
53
54#define EMS_PCI_CAN_CLOCK (16000000 / 2)
55
56/*
57 * Register definitions and descriptions are from LinCAN 0.3.3.
58 *
59 * PSB4610 PITA-2 bridge control registers
60 */
61#define PITA2_ICR           0x00	/* Interrupt Control Register */
62#define PITA2_ICR_INT0      0x00000002	/* [RC] INT0 Active/Clear */
63#define PITA2_ICR_INT0_EN   0x00020000	/* [RW] Enable INT0 */
64
65#define PITA2_MISC          0x1c	/* Miscellaneous Register */
66#define PITA2_MISC_CONFIG   0x04000000	/* Multiplexed parallel interface */
67
68/*
69 * Register definitions for the PLX 9030
70 */
71#define PLX_ICSR            0x4c   /* Interrupt Control/Status register */
72#define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
73#define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
74#define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
75#define PLX_ICSR_ENA_CLR    (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \
76			     PLX_ICSR_LINTI1_CLR)
77
78/*
79 * The board configuration is probably following:
80 * RX1 is connected to ground.
81 * TX1 is not connected.
82 * CLKO is not connected.
83 * Setting the OCR register to 0xDA is a good idea.
84 * This means normal output mode, push-pull and the correct polarity.
85 */
86#define EMS_PCI_OCR         (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
87
88/*
89 * In the CDR register, you should set CBP to 1.
90 * You will probably also want to set the clock divider value to 7
91 * (meaning direct oscillator output) because the second SJA1000 chip
92 * is driven by the first one CLKOUT output.
93 */
94#define EMS_PCI_CDR             (CDR_CBP | CDR_CLKOUT_MASK)
95
96#define EMS_PCI_V1_BASE_BAR     1
97#define EMS_PCI_V1_MEM_SIZE     4096
98#define EMS_PCI_V2_BASE_BAR     2
99#define EMS_PCI_V2_MEM_SIZE     128
100#define EMS_PCI_CAN_BASE_OFFSET 0x400 /* offset where the controllers starts */
101#define EMS_PCI_CAN_CTRL_SIZE   0x200 /* memory size for each controller */
102
103static struct pci_device_id ems_pci_tbl[] = {
104	/* CPC-PCI v1 */
105	{PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
106	/* CPC-PCI v2 */
107	{PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
108	/* CPC-104P v2 */
109	{PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
110	{0,}
111};
112MODULE_DEVICE_TABLE(pci, ems_pci_tbl);
113
114/*
115 * Helper to read internal registers from card logic (not CAN)
116 */
117static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port)
118{
119	return readb(card->base_addr + (port * 4));
120}
121
122static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port)
123{
124	return readb(priv->reg_base + (port * 4));
125}
126
127static void ems_pci_v1_write_reg(const struct sja1000_priv *priv,
128				 int port, u8 val)
129{
130	writeb(val, priv->reg_base + (port * 4));
131}
132
133static void ems_pci_v1_post_irq(const struct sja1000_priv *priv)
134{
135	struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
136
137	/* reset int flag of pita */
138	writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
139	       card->conf_addr + PITA2_ICR);
140}
141
142static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port)
143{
144	return readb(priv->reg_base + port);
145}
146
147static void ems_pci_v2_write_reg(const struct sja1000_priv *priv,
148				 int port, u8 val)
149{
150	writeb(val, priv->reg_base + port);
151}
152
153static void ems_pci_v2_post_irq(const struct sja1000_priv *priv)
154{
155	struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
156
157	writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
158}
159
160/*
161 * Check if a CAN controller is present at the specified location
162 * by trying to set 'em into the PeliCAN mode
163 */
164static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
165{
166	unsigned char res;
167
168	/* Make sure SJA1000 is in reset mode */
169	priv->write_reg(priv, REG_MOD, 1);
170
171	priv->write_reg(priv, REG_CDR, CDR_PELICAN);
172
173	/* read reset-values */
174	res = priv->read_reg(priv, REG_CDR);
175
176	if (res == CDR_PELICAN)
177		return 1;
178
179	return 0;
180}
181
182static void ems_pci_del_card(struct pci_dev *pdev)
183{
184	struct ems_pci_card *card = pci_get_drvdata(pdev);
185	struct net_device *dev;
186	int i = 0;
187
188	for (i = 0; i < card->channels; i++) {
189		dev = card->net_dev[i];
190
191		if (!dev)
192			continue;
193
194		dev_info(&pdev->dev, "Removing %s.\n", dev->name);
195		unregister_sja1000dev(dev);
196		free_sja1000dev(dev);
197	}
198
199	if (card->base_addr != NULL)
200		pci_iounmap(card->pci_dev, card->base_addr);
201
202	if (card->conf_addr != NULL)
203		pci_iounmap(card->pci_dev, card->conf_addr);
204
205	kfree(card);
206
207	pci_disable_device(pdev);
208	pci_set_drvdata(pdev, NULL);
209}
210
211static void ems_pci_card_reset(struct ems_pci_card *card)
212{
213	/* Request board reset */
214	writeb(0, card->base_addr);
215}
216
217/*
218 * Probe PCI device for EMS CAN signature and register each available
219 * CAN channel to SJA1000 Socket-CAN subsystem.
220 */
221static int __devinit ems_pci_add_card(struct pci_dev *pdev,
222					const struct pci_device_id *ent)
223{
224	struct sja1000_priv *priv;
225	struct net_device *dev;
226	struct ems_pci_card *card;
227	int max_chan, mem_size, base_bar;
228	int err, i;
229
230	/* Enabling PCI device */
231	if (pci_enable_device(pdev) < 0) {
232		dev_err(&pdev->dev, "Enabling PCI device failed\n");
233		return -ENODEV;
234	}
235
236	/* Allocating card structures to hold addresses, ... */
237	card = kzalloc(sizeof(struct ems_pci_card), GFP_KERNEL);
238	if (card == NULL) {
239		dev_err(&pdev->dev, "Unable to allocate memory\n");
240		pci_disable_device(pdev);
241		return -ENOMEM;
242	}
243
244	pci_set_drvdata(pdev, card);
245
246	card->pci_dev = pdev;
247
248	card->channels = 0;
249
250	if (pdev->vendor == PCI_VENDOR_ID_PLX) {
251		card->version = 2; /* CPC-PCI v2 */
252		max_chan = EMS_PCI_V2_MAX_CHAN;
253		base_bar = EMS_PCI_V2_BASE_BAR;
254		mem_size = EMS_PCI_V2_MEM_SIZE;
255	} else {
256		card->version = 1; /* CPC-PCI v1 */
257		max_chan = EMS_PCI_V1_MAX_CHAN;
258		base_bar = EMS_PCI_V1_BASE_BAR;
259		mem_size = EMS_PCI_V1_MEM_SIZE;
260	}
261
262	/* Remap configuration space and controller memory area */
263	card->conf_addr = pci_iomap(pdev, 0, mem_size);
264	if (card->conf_addr == NULL) {
265		err = -ENOMEM;
266		goto failure_cleanup;
267	}
268
269	card->base_addr = pci_iomap(pdev, base_bar, mem_size);
270	if (card->base_addr == NULL) {
271		err = -ENOMEM;
272		goto failure_cleanup;
273	}
274
275	if (card->version == 1) {
276		/* Configure PITA-2 parallel interface (enable MUX) */
277		writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);
278
279		/* Check for unique EMS CAN signature */
280		if (ems_pci_v1_readb(card, 0) != 0x55 ||
281		    ems_pci_v1_readb(card, 1) != 0xAA ||
282		    ems_pci_v1_readb(card, 2) != 0x01 ||
283		    ems_pci_v1_readb(card, 3) != 0xCB ||
284		    ems_pci_v1_readb(card, 4) != 0x11) {
285			dev_err(&pdev->dev,
286				"Not EMS Dr. Thomas Wuensche interface\n");
287			err = -ENODEV;
288			goto failure_cleanup;
289		}
290	}
291
292	ems_pci_card_reset(card);
293
294	/* Detect available channels */
295	for (i = 0; i < max_chan; i++) {
296		dev = alloc_sja1000dev(0);
297		if (dev == NULL) {
298			err = -ENOMEM;
299			goto failure_cleanup;
300		}
301
302		card->net_dev[i] = dev;
303		priv = netdev_priv(dev);
304		priv->priv = card;
305		priv->irq_flags = IRQF_SHARED;
306
307		dev->irq = pdev->irq;
308		priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET
309					+ (i * EMS_PCI_CAN_CTRL_SIZE);
310		if (card->version == 1) {
311			priv->read_reg  = ems_pci_v1_read_reg;
312			priv->write_reg = ems_pci_v1_write_reg;
313			priv->post_irq  = ems_pci_v1_post_irq;
314		} else {
315			priv->read_reg  = ems_pci_v2_read_reg;
316			priv->write_reg = ems_pci_v2_write_reg;
317			priv->post_irq  = ems_pci_v2_post_irq;
318		}
319
320		/* Check if channel is present */
321		if (ems_pci_check_chan(priv)) {
322			priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
323			priv->ocr = EMS_PCI_OCR;
324			priv->cdr = EMS_PCI_CDR;
325
326			SET_NETDEV_DEV(dev, &pdev->dev);
327
328			if (card->version == 1)
329				/* reset int flag of pita */
330				writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
331				       card->conf_addr + PITA2_ICR);
332			else
333				/* enable IRQ in PLX 9030 */
334				writel(PLX_ICSR_ENA_CLR,
335				       card->conf_addr + PLX_ICSR);
336
337			/* Register SJA1000 device */
338			err = register_sja1000dev(dev);
339			if (err) {
340				dev_err(&pdev->dev, "Registering device failed "
341							"(err=%d)\n", err);
342				free_sja1000dev(dev);
343				goto failure_cleanup;
344			}
345
346			card->channels++;
347
348			dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n",
349					i + 1, priv->reg_base, dev->irq);
350		} else {
351			free_sja1000dev(dev);
352		}
353	}
354
355	return 0;
356
357failure_cleanup:
358	dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
359
360	ems_pci_del_card(pdev);
361
362	return err;
363}
364
365static struct pci_driver ems_pci_driver = {
366	.name = DRV_NAME,
367	.id_table = ems_pci_tbl,
368	.probe = ems_pci_add_card,
369	.remove = ems_pci_del_card,
370};
371
372static int __init ems_pci_init(void)
373{
374	return pci_register_driver(&ems_pci_driver);
375}
376
377static void __exit ems_pci_exit(void)
378{
379	pci_unregister_driver(&ems_pci_driver);
380}
381
382module_init(ems_pci_init);
383module_exit(ems_pci_exit);
384
385