peak_pci.c revision 3c8ac0f2ad53a96ac58efe7c98fac2986d081dfc
1/* 2 * Copyright (C) 2007, 2011 Wolfgang Grandegger <wg@grandegger.com> 3 * Copyright (C) 2012 Stephane Grosjean <s.grosjean@peak-system.com> 4 * 5 * Derived from the PCAN project file driver/src/pcan_pci.c: 6 * 7 * Copyright (C) 2001-2006 PEAK System-Technik GmbH 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19#include <linux/kernel.h> 20#include <linux/module.h> 21#include <linux/interrupt.h> 22#include <linux/netdevice.h> 23#include <linux/delay.h> 24#include <linux/pci.h> 25#include <linux/io.h> 26#include <linux/i2c.h> 27#include <linux/i2c-algo-bit.h> 28#include <linux/can.h> 29#include <linux/can/dev.h> 30 31#include "sja1000.h" 32 33MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>"); 34MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCI family cards"); 35MODULE_SUPPORTED_DEVICE("PEAK PCAN PCI/PCIe/PCIeC miniPCI CAN cards"); 36MODULE_SUPPORTED_DEVICE("PEAK PCAN miniPCIe/cPCI PC/104+ PCI/104e CAN Cards"); 37MODULE_LICENSE("GPL v2"); 38 39#define DRV_NAME "peak_pci" 40 41struct peak_pciec_card; 42struct peak_pci_chan { 43 void __iomem *cfg_base; /* Common for all channels */ 44 struct net_device *prev_dev; /* Chain of network devices */ 45 u16 icr_mask; /* Interrupt mask for fast ack */ 46 struct peak_pciec_card *pciec_card; /* only for PCIeC LEDs */ 47}; 48 49#define PEAK_PCI_CAN_CLOCK (16000000 / 2) 50 51#define PEAK_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) 52#define PEAK_PCI_OCR OCR_TX0_PUSHPULL 53 54/* 55 * Important PITA registers 56 */ 57#define PITA_ICR 0x00 /* Interrupt control register */ 58#define PITA_GPIOICR 0x18 /* GPIO interface control register */ 59#define PITA_MISC 0x1C /* Miscellaneous register */ 60 61#define PEAK_PCI_CFG_SIZE 0x1000 /* Size of the config PCI bar */ 62#define PEAK_PCI_CHAN_SIZE 0x0400 /* Size used by the channel */ 63 64#define PEAK_PCI_VENDOR_ID 0x001C /* The PCI device and vendor IDs */ 65#define PEAK_PCI_DEVICE_ID 0x0001 /* for PCI/PCIe slot cards */ 66#define PEAK_PCIEC_DEVICE_ID 0x0002 /* for ExpressCard slot cards */ 67#define PEAK_PCIE_DEVICE_ID 0x0003 /* for nextgen PCIe slot cards */ 68#define PEAK_CPCI_DEVICE_ID 0x0004 /* for nextgen cPCI slot cards */ 69#define PEAK_MPCI_DEVICE_ID 0x0005 /* for nextgen miniPCI slot cards */ 70#define PEAK_PC_104P_DEVICE_ID 0x0006 /* PCAN-PC/104+ cards */ 71#define PEAK_PCI_104E_DEVICE_ID 0x0007 /* PCAN-PCI/104 Express cards */ 72#define PEAK_MPCIE_DEVICE_ID 0x0008 /* The miniPCIe slot cards */ 73 74#define PEAK_PCI_CHAN_MAX 4 75 76static const u16 peak_pci_icr_masks[PEAK_PCI_CHAN_MAX] = { 77 0x02, 0x01, 0x40, 0x80 78}; 79 80static DEFINE_PCI_DEVICE_TABLE(peak_pci_tbl) = { 81 {PEAK_PCI_VENDOR_ID, PEAK_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 82 {PEAK_PCI_VENDOR_ID, PEAK_PCIE_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 83 {PEAK_PCI_VENDOR_ID, PEAK_MPCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 84 {PEAK_PCI_VENDOR_ID, PEAK_MPCIE_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 85 {PEAK_PCI_VENDOR_ID, PEAK_PC_104P_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 86 {PEAK_PCI_VENDOR_ID, PEAK_PCI_104E_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 87 {PEAK_PCI_VENDOR_ID, PEAK_CPCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 88#ifdef CONFIG_CAN_PEAK_PCIEC 89 {PEAK_PCI_VENDOR_ID, PEAK_PCIEC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 90#endif 91 {0,} 92}; 93 94MODULE_DEVICE_TABLE(pci, peak_pci_tbl); 95 96#ifdef CONFIG_CAN_PEAK_PCIEC 97/* 98 * PCAN-ExpressCard needs I2C bit-banging configuration option. 99 */ 100 101/* GPIOICR byte access offsets */ 102#define PITA_GPOUT 0x18 /* GPx output value */ 103#define PITA_GPIN 0x19 /* GPx input value */ 104#define PITA_GPOEN 0x1A /* configure GPx as ouput pin */ 105 106/* I2C GP bits */ 107#define PITA_GPIN_SCL 0x01 /* Serial Clock Line */ 108#define PITA_GPIN_SDA 0x04 /* Serial DAta line */ 109 110#define PCA9553_1_SLAVEADDR (0xC4 >> 1) 111 112/* PCA9553 LS0 fields values */ 113enum { 114 PCA9553_LOW, 115 PCA9553_HIGHZ, 116 PCA9553_PWM0, 117 PCA9553_PWM1 118}; 119 120/* LEDs control */ 121#define PCA9553_ON PCA9553_LOW 122#define PCA9553_OFF PCA9553_HIGHZ 123#define PCA9553_SLOW PCA9553_PWM0 124#define PCA9553_FAST PCA9553_PWM1 125 126#define PCA9553_LED(c) (1 << (c)) 127#define PCA9553_LED_STATE(s, c) ((s) << ((c) << 1)) 128 129#define PCA9553_LED_ON(c) PCA9553_LED_STATE(PCA9553_ON, c) 130#define PCA9553_LED_OFF(c) PCA9553_LED_STATE(PCA9553_OFF, c) 131#define PCA9553_LED_SLOW(c) PCA9553_LED_STATE(PCA9553_SLOW, c) 132#define PCA9553_LED_FAST(c) PCA9553_LED_STATE(PCA9553_FAST, c) 133#define PCA9553_LED_MASK(c) PCA9553_LED_STATE(0x03, c) 134 135#define PCA9553_LED_OFF_ALL (PCA9553_LED_OFF(0) | PCA9553_LED_OFF(1)) 136 137#define PCA9553_LS0_INIT 0x40 /* initial value (!= from 0x00) */ 138 139struct peak_pciec_chan { 140 struct net_device *netdev; 141 unsigned long prev_rx_bytes; 142 unsigned long prev_tx_bytes; 143}; 144 145struct peak_pciec_card { 146 void __iomem *cfg_base; /* Common for all channels */ 147 void __iomem *reg_base; /* first channel base address */ 148 u8 led_cache; /* leds state cache */ 149 150 /* PCIExpressCard i2c data */ 151 struct i2c_algo_bit_data i2c_bit; 152 struct i2c_adapter led_chip; 153 struct delayed_work led_work; /* led delayed work */ 154 int chan_count; 155 struct peak_pciec_chan channel[PEAK_PCI_CHAN_MAX]; 156}; 157 158/* "normal" pci register write callback is overloaded for leds control */ 159static void peak_pci_write_reg(const struct sja1000_priv *priv, 160 int port, u8 val); 161 162static inline void pita_set_scl_highz(struct peak_pciec_card *card) 163{ 164 u8 gp_outen = readb(card->cfg_base + PITA_GPOEN) & ~PITA_GPIN_SCL; 165 writeb(gp_outen, card->cfg_base + PITA_GPOEN); 166} 167 168static inline void pita_set_sda_highz(struct peak_pciec_card *card) 169{ 170 u8 gp_outen = readb(card->cfg_base + PITA_GPOEN) & ~PITA_GPIN_SDA; 171 writeb(gp_outen, card->cfg_base + PITA_GPOEN); 172} 173 174static void peak_pciec_init_pita_gpio(struct peak_pciec_card *card) 175{ 176 /* raise SCL & SDA GPIOs to high-Z */ 177 pita_set_scl_highz(card); 178 pita_set_sda_highz(card); 179} 180 181static void pita_setsda(void *data, int state) 182{ 183 struct peak_pciec_card *card = (struct peak_pciec_card *)data; 184 u8 gp_out, gp_outen; 185 186 /* set output sda always to 0 */ 187 gp_out = readb(card->cfg_base + PITA_GPOUT) & ~PITA_GPIN_SDA; 188 writeb(gp_out, card->cfg_base + PITA_GPOUT); 189 190 /* control output sda with GPOEN */ 191 gp_outen = readb(card->cfg_base + PITA_GPOEN); 192 if (state) 193 gp_outen &= ~PITA_GPIN_SDA; 194 else 195 gp_outen |= PITA_GPIN_SDA; 196 197 writeb(gp_outen, card->cfg_base + PITA_GPOEN); 198} 199 200static void pita_setscl(void *data, int state) 201{ 202 struct peak_pciec_card *card = (struct peak_pciec_card *)data; 203 u8 gp_out, gp_outen; 204 205 /* set output scl always to 0 */ 206 gp_out = readb(card->cfg_base + PITA_GPOUT) & ~PITA_GPIN_SCL; 207 writeb(gp_out, card->cfg_base + PITA_GPOUT); 208 209 /* control output scl with GPOEN */ 210 gp_outen = readb(card->cfg_base + PITA_GPOEN); 211 if (state) 212 gp_outen &= ~PITA_GPIN_SCL; 213 else 214 gp_outen |= PITA_GPIN_SCL; 215 216 writeb(gp_outen, card->cfg_base + PITA_GPOEN); 217} 218 219static int pita_getsda(void *data) 220{ 221 struct peak_pciec_card *card = (struct peak_pciec_card *)data; 222 223 /* set tristate */ 224 pita_set_sda_highz(card); 225 226 return (readb(card->cfg_base + PITA_GPIN) & PITA_GPIN_SDA) ? 1 : 0; 227} 228 229static int pita_getscl(void *data) 230{ 231 struct peak_pciec_card *card = (struct peak_pciec_card *)data; 232 233 /* set tristate */ 234 pita_set_scl_highz(card); 235 236 return (readb(card->cfg_base + PITA_GPIN) & PITA_GPIN_SCL) ? 1 : 0; 237} 238 239/* 240 * write commands to the LED chip though the I2C-bus of the PCAN-PCIeC 241 */ 242static int peak_pciec_write_pca9553(struct peak_pciec_card *card, 243 u8 offset, u8 data) 244{ 245 u8 buffer[2] = { 246 offset, 247 data 248 }; 249 struct i2c_msg msg = { 250 .addr = PCA9553_1_SLAVEADDR, 251 .len = 2, 252 .buf = buffer, 253 }; 254 int ret; 255 256 /* cache led mask */ 257 if ((offset == 5) && (data == card->led_cache)) 258 return 0; 259 260 ret = i2c_transfer(&card->led_chip, &msg, 1); 261 if (ret < 0) 262 return ret; 263 264 if (offset == 5) 265 card->led_cache = data; 266 267 return 0; 268} 269 270/* 271 * delayed work callback used to control the LEDs 272 */ 273static void peak_pciec_led_work(struct work_struct *work) 274{ 275 struct peak_pciec_card *card = 276 container_of(work, struct peak_pciec_card, led_work.work); 277 struct net_device *netdev; 278 u8 new_led = card->led_cache; 279 int i, up_count = 0; 280 281 /* first check what is to do */ 282 for (i = 0; i < card->chan_count; i++) { 283 /* default is: not configured */ 284 new_led &= ~PCA9553_LED_MASK(i); 285 new_led |= PCA9553_LED_ON(i); 286 287 netdev = card->channel[i].netdev; 288 if (!netdev || !(netdev->flags & IFF_UP)) 289 continue; 290 291 up_count++; 292 293 /* no activity (but configured) */ 294 new_led &= ~PCA9553_LED_MASK(i); 295 new_led |= PCA9553_LED_SLOW(i); 296 297 /* if bytes counters changed, set fast blinking led */ 298 if (netdev->stats.rx_bytes != card->channel[i].prev_rx_bytes) { 299 card->channel[i].prev_rx_bytes = netdev->stats.rx_bytes; 300 new_led &= ~PCA9553_LED_MASK(i); 301 new_led |= PCA9553_LED_FAST(i); 302 } 303 if (netdev->stats.tx_bytes != card->channel[i].prev_tx_bytes) { 304 card->channel[i].prev_tx_bytes = netdev->stats.tx_bytes; 305 new_led &= ~PCA9553_LED_MASK(i); 306 new_led |= PCA9553_LED_FAST(i); 307 } 308 } 309 310 /* check if LS0 settings changed, only update i2c if so */ 311 peak_pciec_write_pca9553(card, 5, new_led); 312 313 /* restart timer (except if no more configured channels) */ 314 if (up_count) 315 schedule_delayed_work(&card->led_work, HZ); 316} 317 318/* 319 * set LEDs blinking state 320 */ 321static void peak_pciec_set_leds(struct peak_pciec_card *card, u8 led_mask, u8 s) 322{ 323 u8 new_led = card->led_cache; 324 int i; 325 326 /* first check what is to do */ 327 for (i = 0; i < card->chan_count; i++) 328 if (led_mask & PCA9553_LED(i)) { 329 new_led &= ~PCA9553_LED_MASK(i); 330 new_led |= PCA9553_LED_STATE(s, i); 331 } 332 333 /* check if LS0 settings changed, only update i2c if so */ 334 peak_pciec_write_pca9553(card, 5, new_led); 335} 336 337/* 338 * start one second delayed work to control LEDs 339 */ 340static void peak_pciec_start_led_work(struct peak_pciec_card *card) 341{ 342 if (!delayed_work_pending(&card->led_work)) 343 schedule_delayed_work(&card->led_work, HZ); 344} 345 346/* 347 * stop LEDs delayed work 348 */ 349static void peak_pciec_stop_led_work(struct peak_pciec_card *card) 350{ 351 cancel_delayed_work_sync(&card->led_work); 352} 353 354/* 355 * initialize the PCA9553 4-bit I2C-bus LED chip 356 */ 357static int peak_pciec_init_leds(struct peak_pciec_card *card) 358{ 359 int err; 360 361 /* prescaler for frequency 0: "SLOW" = 1 Hz = "44" */ 362 err = peak_pciec_write_pca9553(card, 1, 44 / 1); 363 if (err) 364 return err; 365 366 /* duty cycle 0: 50% */ 367 err = peak_pciec_write_pca9553(card, 2, 0x80); 368 if (err) 369 return err; 370 371 /* prescaler for frequency 1: "FAST" = 5 Hz */ 372 err = peak_pciec_write_pca9553(card, 3, 44 / 5); 373 if (err) 374 return err; 375 376 /* duty cycle 1: 50% */ 377 err = peak_pciec_write_pca9553(card, 4, 0x80); 378 if (err) 379 return err; 380 381 /* switch LEDs to initial state */ 382 return peak_pciec_write_pca9553(card, 5, PCA9553_LS0_INIT); 383} 384 385/* 386 * restore LEDs state to off peak_pciec_leds_exit 387 */ 388static void peak_pciec_leds_exit(struct peak_pciec_card *card) 389{ 390 /* switch LEDs to off */ 391 peak_pciec_write_pca9553(card, 5, PCA9553_LED_OFF_ALL); 392} 393 394/* 395 * normal write sja1000 register method overloaded to catch when controller 396 * is started or stopped, to control leds 397 */ 398static void peak_pciec_write_reg(const struct sja1000_priv *priv, 399 int port, u8 val) 400{ 401 struct peak_pci_chan *chan = priv->priv; 402 struct peak_pciec_card *card = chan->pciec_card; 403 int c = (priv->reg_base - card->reg_base) / PEAK_PCI_CHAN_SIZE; 404 405 /* sja1000 register changes control the leds state */ 406 if (port == REG_MOD) 407 switch (val) { 408 case MOD_RM: 409 /* Reset Mode: set led on */ 410 peak_pciec_set_leds(card, PCA9553_LED(c), PCA9553_ON); 411 break; 412 case 0x00: 413 /* Normal Mode: led slow blinking and start led timer */ 414 peak_pciec_set_leds(card, PCA9553_LED(c), PCA9553_SLOW); 415 peak_pciec_start_led_work(card); 416 break; 417 default: 418 break; 419 } 420 421 /* call base function */ 422 peak_pci_write_reg(priv, port, val); 423} 424 425static struct i2c_algo_bit_data peak_pciec_i2c_bit_ops = { 426 .setsda = pita_setsda, 427 .setscl = pita_setscl, 428 .getsda = pita_getsda, 429 .getscl = pita_getscl, 430 .udelay = 10, 431 .timeout = HZ, 432}; 433 434static int peak_pciec_probe(struct pci_dev *pdev, struct net_device *dev) 435{ 436 struct sja1000_priv *priv = netdev_priv(dev); 437 struct peak_pci_chan *chan = priv->priv; 438 struct peak_pciec_card *card; 439 int err; 440 441 /* copy i2c object address from 1st channel */ 442 if (chan->prev_dev) { 443 struct sja1000_priv *prev_priv = netdev_priv(chan->prev_dev); 444 struct peak_pci_chan *prev_chan = prev_priv->priv; 445 446 card = prev_chan->pciec_card; 447 if (!card) 448 return -ENODEV; 449 450 /* channel is the first one: do the init part */ 451 } else { 452 /* create the bit banging I2C adapter structure */ 453 card = kzalloc(sizeof(struct peak_pciec_card), GFP_KERNEL); 454 if (!card) { 455 dev_err(&pdev->dev, 456 "failed allocating memory for i2c chip\n"); 457 return -ENOMEM; 458 } 459 460 card->cfg_base = chan->cfg_base; 461 card->reg_base = priv->reg_base; 462 463 card->led_chip.owner = THIS_MODULE; 464 card->led_chip.dev.parent = &pdev->dev; 465 card->led_chip.algo_data = &card->i2c_bit; 466 strncpy(card->led_chip.name, "peak_i2c", 467 sizeof(card->led_chip.name)); 468 469 card->i2c_bit = peak_pciec_i2c_bit_ops; 470 card->i2c_bit.udelay = 10; 471 card->i2c_bit.timeout = HZ; 472 card->i2c_bit.data = card; 473 474 peak_pciec_init_pita_gpio(card); 475 476 err = i2c_bit_add_bus(&card->led_chip); 477 if (err) { 478 dev_err(&pdev->dev, "i2c init failed\n"); 479 goto pciec_init_err_1; 480 } 481 482 err = peak_pciec_init_leds(card); 483 if (err) { 484 dev_err(&pdev->dev, "leds hardware init failed\n"); 485 goto pciec_init_err_2; 486 } 487 488 INIT_DELAYED_WORK(&card->led_work, peak_pciec_led_work); 489 /* PCAN-ExpressCard needs its own callback for leds */ 490 priv->write_reg = peak_pciec_write_reg; 491 } 492 493 chan->pciec_card = card; 494 card->channel[card->chan_count++].netdev = dev; 495 496 return 0; 497 498pciec_init_err_2: 499 i2c_del_adapter(&card->led_chip); 500 501pciec_init_err_1: 502 peak_pciec_init_pita_gpio(card); 503 kfree(card); 504 505 return err; 506} 507 508static void peak_pciec_remove(struct peak_pciec_card *card) 509{ 510 peak_pciec_stop_led_work(card); 511 peak_pciec_leds_exit(card); 512 i2c_del_adapter(&card->led_chip); 513 peak_pciec_init_pita_gpio(card); 514 kfree(card); 515} 516 517#else /* CONFIG_CAN_PEAK_PCIEC */ 518 519/* 520 * Placebo functions when PCAN-ExpressCard support is not selected 521 */ 522static inline int peak_pciec_probe(struct pci_dev *pdev, struct net_device *dev) 523{ 524 return -ENODEV; 525} 526 527static inline void peak_pciec_remove(struct peak_pciec_card *card) 528{ 529} 530#endif /* CONFIG_CAN_PEAK_PCIEC */ 531 532static u8 peak_pci_read_reg(const struct sja1000_priv *priv, int port) 533{ 534 return readb(priv->reg_base + (port << 2)); 535} 536 537static void peak_pci_write_reg(const struct sja1000_priv *priv, 538 int port, u8 val) 539{ 540 writeb(val, priv->reg_base + (port << 2)); 541} 542 543static void peak_pci_post_irq(const struct sja1000_priv *priv) 544{ 545 struct peak_pci_chan *chan = priv->priv; 546 u16 icr; 547 548 /* Select and clear in PITA stored interrupt */ 549 icr = readw(chan->cfg_base + PITA_ICR); 550 if (icr & chan->icr_mask) 551 writew(chan->icr_mask, chan->cfg_base + PITA_ICR); 552} 553 554static int peak_pci_probe(struct pci_dev *pdev, 555 const struct pci_device_id *ent) 556{ 557 struct sja1000_priv *priv; 558 struct peak_pci_chan *chan; 559 struct net_device *dev; 560 void __iomem *cfg_base, *reg_base; 561 u16 sub_sys_id, icr; 562 int i, err, channels; 563 564 err = pci_enable_device(pdev); 565 if (err) 566 return err; 567 568 err = pci_request_regions(pdev, DRV_NAME); 569 if (err) 570 goto failure_disable_pci; 571 572 err = pci_read_config_word(pdev, 0x2e, &sub_sys_id); 573 if (err) 574 goto failure_release_regions; 575 576 dev_dbg(&pdev->dev, "probing device %04x:%04x:%04x\n", 577 pdev->vendor, pdev->device, sub_sys_id); 578 579 err = pci_write_config_word(pdev, 0x44, 0); 580 if (err) 581 goto failure_release_regions; 582 583 if (sub_sys_id >= 12) 584 channels = 4; 585 else if (sub_sys_id >= 10) 586 channels = 3; 587 else if (sub_sys_id >= 4) 588 channels = 2; 589 else 590 channels = 1; 591 592 cfg_base = pci_iomap(pdev, 0, PEAK_PCI_CFG_SIZE); 593 if (!cfg_base) { 594 dev_err(&pdev->dev, "failed to map PCI resource #0\n"); 595 err = -ENOMEM; 596 goto failure_release_regions; 597 } 598 599 reg_base = pci_iomap(pdev, 1, PEAK_PCI_CHAN_SIZE * channels); 600 if (!reg_base) { 601 dev_err(&pdev->dev, "failed to map PCI resource #1\n"); 602 err = -ENOMEM; 603 goto failure_unmap_cfg_base; 604 } 605 606 /* Set GPIO control register */ 607 writew(0x0005, cfg_base + PITA_GPIOICR + 2); 608 /* Enable all channels of this card */ 609 writeb(0x00, cfg_base + PITA_GPIOICR); 610 /* Toggle reset */ 611 writeb(0x05, cfg_base + PITA_MISC + 3); 612 mdelay(5); 613 /* Leave parport mux mode */ 614 writeb(0x04, cfg_base + PITA_MISC + 3); 615 616 icr = readw(cfg_base + PITA_ICR + 2); 617 618 for (i = 0; i < channels; i++) { 619 dev = alloc_sja1000dev(sizeof(struct peak_pci_chan)); 620 if (!dev) { 621 err = -ENOMEM; 622 goto failure_remove_channels; 623 } 624 625 priv = netdev_priv(dev); 626 chan = priv->priv; 627 628 chan->cfg_base = cfg_base; 629 priv->reg_base = reg_base + i * PEAK_PCI_CHAN_SIZE; 630 631 priv->read_reg = peak_pci_read_reg; 632 priv->write_reg = peak_pci_write_reg; 633 priv->post_irq = peak_pci_post_irq; 634 635 priv->can.clock.freq = PEAK_PCI_CAN_CLOCK; 636 priv->ocr = PEAK_PCI_OCR; 637 priv->cdr = PEAK_PCI_CDR; 638 /* Neither a slave nor a single device distributes the clock */ 639 if (channels == 1 || i > 0) 640 priv->cdr |= CDR_CLK_OFF; 641 642 /* Setup interrupt handling */ 643 priv->irq_flags = IRQF_SHARED; 644 dev->irq = pdev->irq; 645 646 chan->icr_mask = peak_pci_icr_masks[i]; 647 icr |= chan->icr_mask; 648 649 SET_NETDEV_DEV(dev, &pdev->dev); 650 651 /* Create chain of SJA1000 devices */ 652 chan->prev_dev = pci_get_drvdata(pdev); 653 pci_set_drvdata(pdev, dev); 654 655 /* 656 * PCAN-ExpressCard needs some additional i2c init. 657 * This must be done *before* register_sja1000dev() but 658 * *after* devices linkage 659 */ 660 if (pdev->device == PEAK_PCIEC_DEVICE_ID) { 661 err = peak_pciec_probe(pdev, dev); 662 if (err) { 663 dev_err(&pdev->dev, 664 "failed to probe device (err %d)\n", 665 err); 666 goto failure_free_dev; 667 } 668 } 669 670 err = register_sja1000dev(dev); 671 if (err) { 672 dev_err(&pdev->dev, "failed to register device\n"); 673 goto failure_free_dev; 674 } 675 676 dev_info(&pdev->dev, 677 "%s at reg_base=0x%p cfg_base=0x%p irq=%d\n", 678 dev->name, priv->reg_base, chan->cfg_base, dev->irq); 679 } 680 681 /* Enable interrupts */ 682 writew(icr, cfg_base + PITA_ICR + 2); 683 684 return 0; 685 686failure_free_dev: 687 pci_set_drvdata(pdev, chan->prev_dev); 688 free_sja1000dev(dev); 689 690failure_remove_channels: 691 /* Disable interrupts */ 692 writew(0x0, cfg_base + PITA_ICR + 2); 693 694 chan = NULL; 695 for (dev = pci_get_drvdata(pdev); dev; dev = chan->prev_dev) { 696 unregister_sja1000dev(dev); 697 free_sja1000dev(dev); 698 priv = netdev_priv(dev); 699 chan = priv->priv; 700 } 701 702 /* free any PCIeC resources too */ 703 if (chan && chan->pciec_card) 704 peak_pciec_remove(chan->pciec_card); 705 706 pci_iounmap(pdev, reg_base); 707 708failure_unmap_cfg_base: 709 pci_iounmap(pdev, cfg_base); 710 711failure_release_regions: 712 pci_release_regions(pdev); 713 714failure_disable_pci: 715 pci_disable_device(pdev); 716 717 return err; 718} 719 720static void peak_pci_remove(struct pci_dev *pdev) 721{ 722 struct net_device *dev = pci_get_drvdata(pdev); /* Last device */ 723 struct sja1000_priv *priv = netdev_priv(dev); 724 struct peak_pci_chan *chan = priv->priv; 725 void __iomem *cfg_base = chan->cfg_base; 726 void __iomem *reg_base = priv->reg_base; 727 728 /* Disable interrupts */ 729 writew(0x0, cfg_base + PITA_ICR + 2); 730 731 /* Loop over all registered devices */ 732 while (1) { 733 dev_info(&pdev->dev, "removing device %s\n", dev->name); 734 unregister_sja1000dev(dev); 735 free_sja1000dev(dev); 736 dev = chan->prev_dev; 737 738 if (!dev) { 739 /* do that only for first channel */ 740 if (chan->pciec_card) 741 peak_pciec_remove(chan->pciec_card); 742 break; 743 } 744 priv = netdev_priv(dev); 745 chan = priv->priv; 746 } 747 748 pci_iounmap(pdev, reg_base); 749 pci_iounmap(pdev, cfg_base); 750 pci_release_regions(pdev); 751 pci_disable_device(pdev); 752 753 pci_set_drvdata(pdev, NULL); 754} 755 756static struct pci_driver peak_pci_driver = { 757 .name = DRV_NAME, 758 .id_table = peak_pci_tbl, 759 .probe = peak_pci_probe, 760 .remove = peak_pci_remove, 761}; 762 763module_pci_driver(peak_pci_driver); 764