plx_pci.c revision 05780d9808f72dc28a5c3602e11a7c53aef972ad
1/* 2 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su> 3 * 4 * Derived from the ems_pci.c driver: 5 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com> 6 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com> 7 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22#include <linux/kernel.h> 23#include <linux/module.h> 24#include <linux/interrupt.h> 25#include <linux/netdevice.h> 26#include <linux/delay.h> 27#include <linux/slab.h> 28#include <linux/pci.h> 29#include <linux/can/dev.h> 30#include <linux/io.h> 31 32#include "sja1000.h" 33 34#define DRV_NAME "sja1000_plx_pci" 35 36MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>"); 37MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with " 38 "the SJA1000 chips"); 39MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, " 40 "Adlink PCI-7841/cPCI-7841 SE, " 41 "Marathon CAN-bus-PCI, " 42 "TEWS TECHNOLOGIES TPMC810, " 43 "esd CAN-PCI/CPCI/PCI104/200, " 44 "esd CAN-PCI/PMC/266, " 45 "esd CAN-PCIe/2000, " 46 "Connect Tech Inc. CANpro/104-Plus Opto (CRG001), " 47 "IXXAT PC-I 04/PCI") 48MODULE_LICENSE("GPL v2"); 49 50#define PLX_PCI_MAX_CHAN 2 51 52struct plx_pci_card { 53 int channels; /* detected channels count */ 54 struct net_device *net_dev[PLX_PCI_MAX_CHAN]; 55 void __iomem *conf_addr; 56 57 /* Pointer to device-dependent reset function */ 58 void (*reset_func)(struct pci_dev *pdev); 59}; 60 61#define PLX_PCI_CAN_CLOCK (16000000 / 2) 62 63/* PLX9030/9050/9052 registers */ 64#define PLX_INTCSR 0x4c /* Interrupt Control/Status */ 65#define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response, 66 * Serial EEPROM, and Initialization 67 * Control register 68 */ 69 70#define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */ 71#define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */ 72#define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */ 73#define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */ 74 75/* PLX9056 registers */ 76#define PLX9056_INTCSR 0x68 /* Interrupt Control/Status */ 77#define PLX9056_CNTRL 0x6c /* Control / Software Reset */ 78 79#define PLX9056_LINTI (1 << 11) 80#define PLX9056_PCI_INT_EN (1 << 8) 81#define PLX9056_PCI_RCR (1 << 29) /* Read Configuration Registers */ 82 83/* 84 * The board configuration is probably following: 85 * RX1 is connected to ground. 86 * TX1 is not connected. 87 * CLKO is not connected. 88 * Setting the OCR register to 0xDA is a good idea. 89 * This means normal output mode, push-pull and the correct polarity. 90 */ 91#define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL) 92 93/* 94 * In the CDR register, you should set CBP to 1. 95 * You will probably also want to set the clock divider value to 7 96 * (meaning direct oscillator output) because the second SJA1000 chip 97 * is driven by the first one CLKOUT output. 98 */ 99#define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) 100 101/* SJA1000 Control Register in the BasicCAN Mode */ 102#define REG_CR 0x00 103 104/* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/ 105#define REG_CR_BASICCAN_INITIAL 0x21 106#define REG_CR_BASICCAN_INITIAL_MASK 0xa1 107#define REG_SR_BASICCAN_INITIAL 0x0c 108#define REG_IR_BASICCAN_INITIAL 0xe0 109 110/* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/ 111#define REG_MOD_PELICAN_INITIAL 0x01 112#define REG_SR_PELICAN_INITIAL 0x3c 113#define REG_IR_PELICAN_INITIAL 0x00 114 115#define ADLINK_PCI_VENDOR_ID 0x144A 116#define ADLINK_PCI_DEVICE_ID 0x7841 117 118#define ESD_PCI_SUB_SYS_ID_PCI200 0x0004 119#define ESD_PCI_SUB_SYS_ID_PCI266 0x0009 120#define ESD_PCI_SUB_SYS_ID_PMC266 0x000e 121#define ESD_PCI_SUB_SYS_ID_CPCI200 0x010b 122#define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200 123#define ESD_PCI_SUB_SYS_ID_PCI104200 0x0501 124 125#define IXXAT_PCI_VENDOR_ID 0x10b5 126#define IXXAT_PCI_DEVICE_ID 0x9050 127#define IXXAT_PCI_SUB_SYS_ID 0x2540 128 129#define MARATHON_PCI_DEVICE_ID 0x2715 130 131#define TEWS_PCI_VENDOR_ID 0x1498 132#define TEWS_PCI_DEVICE_ID_TMPC810 0x032A 133 134#define CTI_PCI_VENDOR_ID 0x12c4 135#define CTI_PCI_DEVICE_ID_CRG001 0x0900 136 137static void plx_pci_reset_common(struct pci_dev *pdev); 138static void plx_pci_reset_marathon(struct pci_dev *pdev); 139static void plx9056_pci_reset_common(struct pci_dev *pdev); 140 141struct plx_pci_channel_map { 142 u32 bar; 143 u32 offset; 144 u32 size; /* 0x00 - auto, e.g. length of entire bar */ 145}; 146 147struct plx_pci_card_info { 148 const char *name; 149 int channel_count; 150 u32 can_clock; 151 u8 ocr; /* output control register */ 152 u8 cdr; /* clock divider register */ 153 154 /* Parameters for mapping local configuration space */ 155 struct plx_pci_channel_map conf_map; 156 157 /* Parameters for mapping the SJA1000 chips */ 158 struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN]; 159 160 /* Pointer to device-dependent reset function */ 161 void (*reset_func)(struct pci_dev *pdev); 162}; 163 164static struct plx_pci_card_info plx_pci_card_info_adlink = { 165 "Adlink PCI-7841/cPCI-7841", 2, 166 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 167 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, 168 &plx_pci_reset_common 169 /* based on PLX9052 */ 170}; 171 172static struct plx_pci_card_info plx_pci_card_info_adlink_se = { 173 "Adlink PCI-7841/cPCI-7841 SE", 2, 174 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 175 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, 176 &plx_pci_reset_common 177 /* based on PLX9052 */ 178}; 179 180static struct plx_pci_card_info plx_pci_card_info_esd200 = { 181 "esd CAN-PCI/CPCI/PCI104/200", 2, 182 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 183 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 184 &plx_pci_reset_common 185 /* based on PLX9030/9050 */ 186}; 187 188static struct plx_pci_card_info plx_pci_card_info_esd266 = { 189 "esd CAN-PCI/PMC/266", 2, 190 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 191 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 192 &plx9056_pci_reset_common 193 /* based on PLX9056 */ 194}; 195 196static struct plx_pci_card_info plx_pci_card_info_esd2000 = { 197 "esd CAN-PCIe/2000", 2, 198 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 199 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 200 &plx9056_pci_reset_common 201 /* based on PEX8311 */ 202}; 203 204static struct plx_pci_card_info plx_pci_card_info_ixxat = { 205 "IXXAT PC-I 04/PCI", 2, 206 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 207 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x200, 0x80} }, 208 &plx_pci_reset_common 209 /* based on PLX9050 */ 210}; 211 212static struct plx_pci_card_info plx_pci_card_info_marathon = { 213 "Marathon CAN-bus-PCI", 2, 214 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 215 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} }, 216 &plx_pci_reset_marathon 217 /* based on PLX9052 */ 218}; 219 220static struct plx_pci_card_info plx_pci_card_info_tews = { 221 "TEWS TECHNOLOGIES TPMC810", 2, 222 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 223 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, 224 &plx_pci_reset_common 225 /* based on PLX9030 */ 226}; 227 228static struct plx_pci_card_info plx_pci_card_info_cti = { 229 "Connect Tech Inc. CANpro/104-Plus Opto (CRG001)", 2, 230 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 231 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, 232 &plx_pci_reset_common 233 /* based on PLX9030 */ 234}; 235 236static DEFINE_PCI_DEVICE_TABLE(plx_pci_tbl) = { 237 { 238 /* Adlink PCI-7841/cPCI-7841 */ 239 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, 240 PCI_ANY_ID, PCI_ANY_ID, 241 PCI_CLASS_NETWORK_OTHER << 8, ~0, 242 (kernel_ulong_t)&plx_pci_card_info_adlink 243 }, 244 { 245 /* Adlink PCI-7841/cPCI-7841 SE */ 246 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, 247 PCI_ANY_ID, PCI_ANY_ID, 248 PCI_CLASS_COMMUNICATION_OTHER << 8, ~0, 249 (kernel_ulong_t)&plx_pci_card_info_adlink_se 250 }, 251 { 252 /* esd CAN-PCI/200 */ 253 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 254 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200, 255 0, 0, 256 (kernel_ulong_t)&plx_pci_card_info_esd200 257 }, 258 { 259 /* esd CAN-CPCI/200 */ 260 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 261 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200, 262 0, 0, 263 (kernel_ulong_t)&plx_pci_card_info_esd200 264 }, 265 { 266 /* esd CAN-PCI104/200 */ 267 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 268 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200, 269 0, 0, 270 (kernel_ulong_t)&plx_pci_card_info_esd200 271 }, 272 { 273 /* esd CAN-PCI/266 */ 274 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 275 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266, 276 0, 0, 277 (kernel_ulong_t)&plx_pci_card_info_esd266 278 }, 279 { 280 /* esd CAN-PMC/266 */ 281 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 282 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266, 283 0, 0, 284 (kernel_ulong_t)&plx_pci_card_info_esd266 285 }, 286 { 287 /* esd CAN-PCIE/2000 */ 288 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 289 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000, 290 0, 0, 291 (kernel_ulong_t)&plx_pci_card_info_esd2000 292 }, 293 { 294 /* IXXAT PC-I 04/PCI card */ 295 IXXAT_PCI_VENDOR_ID, IXXAT_PCI_DEVICE_ID, 296 PCI_ANY_ID, IXXAT_PCI_SUB_SYS_ID, 297 0, 0, 298 (kernel_ulong_t)&plx_pci_card_info_ixxat 299 }, 300 { 301 /* Marathon CAN-bus-PCI card */ 302 PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID, 303 PCI_ANY_ID, PCI_ANY_ID, 304 0, 0, 305 (kernel_ulong_t)&plx_pci_card_info_marathon 306 }, 307 { 308 /* TEWS TECHNOLOGIES TPMC810 card */ 309 TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810, 310 PCI_ANY_ID, PCI_ANY_ID, 311 0, 0, 312 (kernel_ulong_t)&plx_pci_card_info_tews 313 }, 314 { 315 /* Connect Tech Inc. CANpro/104-Plus Opto (CRG001) card */ 316 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 317 CTI_PCI_VENDOR_ID, CTI_PCI_DEVICE_ID_CRG001, 318 0, 0, 319 (kernel_ulong_t)&plx_pci_card_info_cti 320 }, 321 { 0,} 322}; 323MODULE_DEVICE_TABLE(pci, plx_pci_tbl); 324 325static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port) 326{ 327 return ioread8(priv->reg_base + port); 328} 329 330static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val) 331{ 332 iowrite8(val, priv->reg_base + port); 333} 334 335/* 336 * Check if a CAN controller is present at the specified location 337 * by trying to switch 'em from the Basic mode into the PeliCAN mode. 338 * Also check states of some registers in reset mode. 339 */ 340static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) 341{ 342 int flag = 0; 343 344 /* 345 * Check registers after hardware reset (the Basic mode) 346 * See states on p. 10 of the Datasheet. 347 */ 348 if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) == 349 REG_CR_BASICCAN_INITIAL && 350 (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) && 351 (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL)) 352 flag = 1; 353 354 /* Bring the SJA1000 into the PeliCAN mode*/ 355 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN); 356 357 /* 358 * Check registers after reset in the PeliCAN mode. 359 * See states on p. 23 of the Datasheet. 360 */ 361 if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL && 362 priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL && 363 priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL) 364 return flag; 365 366 return 0; 367} 368 369/* 370 * PLX9030/50/52 software reset 371 * Also LRESET# asserts and brings to reset device on the Local Bus (if wired). 372 * For most cards it's enough for reset the SJA1000 chips. 373 */ 374static void plx_pci_reset_common(struct pci_dev *pdev) 375{ 376 struct plx_pci_card *card = pci_get_drvdata(pdev); 377 u32 cntrl; 378 379 cntrl = ioread32(card->conf_addr + PLX_CNTRL); 380 cntrl |= PLX_PCI_RESET; 381 iowrite32(cntrl, card->conf_addr + PLX_CNTRL); 382 udelay(100); 383 cntrl ^= PLX_PCI_RESET; 384 iowrite32(cntrl, card->conf_addr + PLX_CNTRL); 385}; 386 387/* 388 * PLX9056 software reset 389 * Assert LRESET# and reset device(s) on the Local Bus (if wired). 390 */ 391static void plx9056_pci_reset_common(struct pci_dev *pdev) 392{ 393 struct plx_pci_card *card = pci_get_drvdata(pdev); 394 u32 cntrl; 395 396 /* issue a local bus reset */ 397 cntrl = ioread32(card->conf_addr + PLX9056_CNTRL); 398 cntrl |= PLX_PCI_RESET; 399 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 400 udelay(100); 401 cntrl ^= PLX_PCI_RESET; 402 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 403 404 /* reload local configuration from EEPROM */ 405 cntrl |= PLX9056_PCI_RCR; 406 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 407 408 /* 409 * There is no safe way to poll for the end 410 * of reconfiguration process. Waiting for 10ms 411 * is safe. 412 */ 413 mdelay(10); 414 415 cntrl ^= PLX9056_PCI_RCR; 416 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 417}; 418 419/* Special reset function for Marathon card */ 420static void plx_pci_reset_marathon(struct pci_dev *pdev) 421{ 422 void __iomem *reset_addr; 423 int i; 424 static const int reset_bar[2] = {3, 5}; 425 426 plx_pci_reset_common(pdev); 427 428 for (i = 0; i < 2; i++) { 429 reset_addr = pci_iomap(pdev, reset_bar[i], 0); 430 if (!reset_addr) { 431 dev_err(&pdev->dev, "Failed to remap reset " 432 "space %d (BAR%d)\n", i, reset_bar[i]); 433 } else { 434 /* reset the SJA1000 chip */ 435 iowrite8(0x1, reset_addr); 436 udelay(100); 437 pci_iounmap(pdev, reset_addr); 438 } 439 } 440} 441 442static void plx_pci_del_card(struct pci_dev *pdev) 443{ 444 struct plx_pci_card *card = pci_get_drvdata(pdev); 445 struct net_device *dev; 446 struct sja1000_priv *priv; 447 int i = 0; 448 449 for (i = 0; i < PLX_PCI_MAX_CHAN; i++) { 450 dev = card->net_dev[i]; 451 if (!dev) 452 continue; 453 454 dev_info(&pdev->dev, "Removing %s\n", dev->name); 455 unregister_sja1000dev(dev); 456 priv = netdev_priv(dev); 457 if (priv->reg_base) 458 pci_iounmap(pdev, priv->reg_base); 459 free_sja1000dev(dev); 460 } 461 462 card->reset_func(pdev); 463 464 /* 465 * Disable interrupts from PCI-card and disable local 466 * interrupts 467 */ 468 if (pdev->device != PCI_DEVICE_ID_PLX_9056) 469 iowrite32(0x0, card->conf_addr + PLX_INTCSR); 470 else 471 iowrite32(0x0, card->conf_addr + PLX9056_INTCSR); 472 473 if (card->conf_addr) 474 pci_iounmap(pdev, card->conf_addr); 475 476 kfree(card); 477 478 pci_disable_device(pdev); 479} 480 481/* 482 * Probe PLX90xx based device for the SJA1000 chips and register each 483 * available CAN channel to SJA1000 Socket-CAN subsystem. 484 */ 485static int plx_pci_add_card(struct pci_dev *pdev, 486 const struct pci_device_id *ent) 487{ 488 struct sja1000_priv *priv; 489 struct net_device *dev; 490 struct plx_pci_card *card; 491 struct plx_pci_card_info *ci; 492 int err, i; 493 u32 val; 494 void __iomem *addr; 495 496 ci = (struct plx_pci_card_info *)ent->driver_data; 497 498 if (pci_enable_device(pdev) < 0) { 499 dev_err(&pdev->dev, "Failed to enable PCI device\n"); 500 return -ENODEV; 501 } 502 503 dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n", 504 ci->name, PCI_SLOT(pdev->devfn)); 505 506 /* Allocate card structures to hold addresses, ... */ 507 card = kzalloc(sizeof(*card), GFP_KERNEL); 508 if (!card) { 509 pci_disable_device(pdev); 510 return -ENOMEM; 511 } 512 513 pci_set_drvdata(pdev, card); 514 515 card->channels = 0; 516 517 /* Remap PLX90xx configuration space */ 518 addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size); 519 if (!addr) { 520 err = -ENOMEM; 521 dev_err(&pdev->dev, "Failed to remap configuration space " 522 "(BAR%d)\n", ci->conf_map.bar); 523 goto failure_cleanup; 524 } 525 card->conf_addr = addr + ci->conf_map.offset; 526 527 ci->reset_func(pdev); 528 card->reset_func = ci->reset_func; 529 530 /* Detect available channels */ 531 for (i = 0; i < ci->channel_count; i++) { 532 struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i]; 533 534 dev = alloc_sja1000dev(0); 535 if (!dev) { 536 err = -ENOMEM; 537 goto failure_cleanup; 538 } 539 540 card->net_dev[i] = dev; 541 priv = netdev_priv(dev); 542 priv->priv = card; 543 priv->irq_flags = IRQF_SHARED; 544 545 dev->irq = pdev->irq; 546 547 /* 548 * Remap IO space of the SJA1000 chips 549 * This is device-dependent mapping 550 */ 551 addr = pci_iomap(pdev, cm->bar, cm->size); 552 if (!addr) { 553 err = -ENOMEM; 554 dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar); 555 goto failure_cleanup; 556 } 557 558 priv->reg_base = addr + cm->offset; 559 priv->read_reg = plx_pci_read_reg; 560 priv->write_reg = plx_pci_write_reg; 561 562 /* Check if channel is present */ 563 if (plx_pci_check_sja1000(priv)) { 564 priv->can.clock.freq = ci->can_clock; 565 priv->ocr = ci->ocr; 566 priv->cdr = ci->cdr; 567 568 SET_NETDEV_DEV(dev, &pdev->dev); 569 570 /* Register SJA1000 device */ 571 err = register_sja1000dev(dev); 572 if (err) { 573 dev_err(&pdev->dev, "Registering device failed " 574 "(err=%d)\n", err); 575 goto failure_cleanup; 576 } 577 578 card->channels++; 579 580 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d " 581 "registered as %s\n", i + 1, priv->reg_base, 582 dev->irq, dev->name); 583 } else { 584 dev_err(&pdev->dev, "Channel #%d not detected\n", 585 i + 1); 586 free_sja1000dev(dev); 587 card->net_dev[i] = NULL; 588 } 589 } 590 591 if (!card->channels) { 592 err = -ENODEV; 593 goto failure_cleanup; 594 } 595 596 /* 597 * Enable interrupts from PCI-card (PLX90xx) and enable Local_1, 598 * Local_2 interrupts from the SJA1000 chips 599 */ 600 if (pdev->device != PCI_DEVICE_ID_PLX_9056) { 601 val = ioread32(card->conf_addr + PLX_INTCSR); 602 if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH) 603 val |= PLX_LINT1_EN | PLX_PCI_INT_EN; 604 else 605 val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN; 606 iowrite32(val, card->conf_addr + PLX_INTCSR); 607 } else { 608 iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN, 609 card->conf_addr + PLX9056_INTCSR); 610 } 611 return 0; 612 613failure_cleanup: 614 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err); 615 616 plx_pci_del_card(pdev); 617 618 return err; 619} 620 621static struct pci_driver plx_pci_driver = { 622 .name = DRV_NAME, 623 .id_table = plx_pci_tbl, 624 .probe = plx_pci_add_card, 625 .remove = plx_pci_del_card, 626}; 627 628module_pci_driver(plx_pci_driver); 629