plx_pci.c revision 82e381775f6da6b29ae625e73a2ea18844eb4825
1/* 2 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su> 3 * 4 * Derived from the ems_pci.c driver: 5 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com> 6 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com> 7 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 21 */ 22 23#include <linux/kernel.h> 24#include <linux/module.h> 25#include <linux/interrupt.h> 26#include <linux/netdevice.h> 27#include <linux/delay.h> 28#include <linux/slab.h> 29#include <linux/pci.h> 30#include <linux/can.h> 31#include <linux/can/dev.h> 32#include <linux/io.h> 33 34#include "sja1000.h" 35 36#define DRV_NAME "sja1000_plx_pci" 37 38MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>"); 39MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with " 40 "the SJA1000 chips"); 41MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, " 42 "Adlink PCI-7841/cPCI-7841 SE, " 43 "Marathon CAN-bus-PCI, " 44 "TEWS TECHNOLOGIES TPMC810, " 45 "esd CAN-PCI/CPCI/PCI104/200, " 46 "esd CAN-PCI/PMC/266, " 47 "esd CAN-PCIe/2000") 48MODULE_LICENSE("GPL v2"); 49 50#define PLX_PCI_MAX_CHAN 2 51 52struct plx_pci_card { 53 int channels; /* detected channels count */ 54 struct net_device *net_dev[PLX_PCI_MAX_CHAN]; 55 void __iomem *conf_addr; 56 57 /* Pointer to device-dependent reset function */ 58 void (*reset_func)(struct pci_dev *pdev); 59}; 60 61#define PLX_PCI_CAN_CLOCK (16000000 / 2) 62 63/* PLX9030/9050/9052 registers */ 64#define PLX_INTCSR 0x4c /* Interrupt Control/Status */ 65#define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response, 66 * Serial EEPROM, and Initialization 67 * Control register 68 */ 69 70#define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */ 71#define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */ 72#define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */ 73#define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */ 74 75/* PLX9056 registers */ 76#define PLX9056_INTCSR 0x68 /* Interrupt Control/Status */ 77#define PLX9056_CNTRL 0x6c /* Control / Software Reset */ 78 79#define PLX9056_LINTI (1 << 11) 80#define PLX9056_PCI_INT_EN (1 << 8) 81#define PLX9056_PCI_RCR (1 << 29) /* Read Configuration Registers */ 82 83/* 84 * The board configuration is probably following: 85 * RX1 is connected to ground. 86 * TX1 is not connected. 87 * CLKO is not connected. 88 * Setting the OCR register to 0xDA is a good idea. 89 * This means normal output mode, push-pull and the correct polarity. 90 */ 91#define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL) 92 93/* 94 * In the CDR register, you should set CBP to 1. 95 * You will probably also want to set the clock divider value to 7 96 * (meaning direct oscillator output) because the second SJA1000 chip 97 * is driven by the first one CLKOUT output. 98 */ 99#define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) 100 101/* SJA1000 Control Register in the BasicCAN Mode */ 102#define REG_CR 0x00 103 104/* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/ 105#define REG_CR_BASICCAN_INITIAL 0x21 106#define REG_CR_BASICCAN_INITIAL_MASK 0xa1 107#define REG_SR_BASICCAN_INITIAL 0x0c 108#define REG_IR_BASICCAN_INITIAL 0xe0 109 110/* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/ 111#define REG_MOD_PELICAN_INITIAL 0x01 112#define REG_SR_PELICAN_INITIAL 0x3c 113#define REG_IR_PELICAN_INITIAL 0x00 114 115#define ADLINK_PCI_VENDOR_ID 0x144A 116#define ADLINK_PCI_DEVICE_ID 0x7841 117 118#define ESD_PCI_SUB_SYS_ID_PCI200 0x0004 119#define ESD_PCI_SUB_SYS_ID_PCI266 0x0009 120#define ESD_PCI_SUB_SYS_ID_PMC266 0x000e 121#define ESD_PCI_SUB_SYS_ID_CPCI200 0x010b 122#define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200 123#define ESD_PCI_SUB_SYS_ID_PCI104200 0x0501 124 125#define MARATHON_PCI_DEVICE_ID 0x2715 126 127#define TEWS_PCI_VENDOR_ID 0x1498 128#define TEWS_PCI_DEVICE_ID_TMPC810 0x032A 129 130static void plx_pci_reset_common(struct pci_dev *pdev); 131static void plx_pci_reset_marathon(struct pci_dev *pdev); 132static void plx9056_pci_reset_common(struct pci_dev *pdev); 133 134struct plx_pci_channel_map { 135 u32 bar; 136 u32 offset; 137 u32 size; /* 0x00 - auto, e.g. length of entire bar */ 138}; 139 140struct plx_pci_card_info { 141 const char *name; 142 int channel_count; 143 u32 can_clock; 144 u8 ocr; /* output control register */ 145 u8 cdr; /* clock divider register */ 146 147 /* Parameters for mapping local configuration space */ 148 struct plx_pci_channel_map conf_map; 149 150 /* Parameters for mapping the SJA1000 chips */ 151 struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN]; 152 153 /* Pointer to device-dependent reset function */ 154 void (*reset_func)(struct pci_dev *pdev); 155}; 156 157static struct plx_pci_card_info plx_pci_card_info_adlink __devinitdata = { 158 "Adlink PCI-7841/cPCI-7841", 2, 159 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 160 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, 161 &plx_pci_reset_common 162 /* based on PLX9052 */ 163}; 164 165static struct plx_pci_card_info plx_pci_card_info_adlink_se __devinitdata = { 166 "Adlink PCI-7841/cPCI-7841 SE", 2, 167 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 168 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, 169 &plx_pci_reset_common 170 /* based on PLX9052 */ 171}; 172 173static struct plx_pci_card_info plx_pci_card_info_esd200 __devinitdata = { 174 "esd CAN-PCI/CPCI/PCI104/200", 2, 175 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 176 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 177 &plx_pci_reset_common 178 /* based on PLX9030/9050 */ 179}; 180 181static struct plx_pci_card_info plx_pci_card_info_esd266 __devinitdata = { 182 "esd CAN-PCI/PMC/266", 2, 183 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 184 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 185 &plx9056_pci_reset_common 186 /* based on PLX9056 */ 187}; 188 189static struct plx_pci_card_info plx_pci_card_info_esd2000 __devinitdata = { 190 "esd CAN-PCIe/2000", 2, 191 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 192 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 193 &plx9056_pci_reset_common 194 /* based on PEX8311 */ 195}; 196 197static struct plx_pci_card_info plx_pci_card_info_marathon __devinitdata = { 198 "Marathon CAN-bus-PCI", 2, 199 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 200 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} }, 201 &plx_pci_reset_marathon 202 /* based on PLX9052 */ 203}; 204 205static struct plx_pci_card_info plx_pci_card_info_tews __devinitdata = { 206 "TEWS TECHNOLOGIES TPMC810", 2, 207 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 208 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, 209 &plx_pci_reset_common 210 /* based on PLX9030 */ 211}; 212 213static DEFINE_PCI_DEVICE_TABLE(plx_pci_tbl) = { 214 { 215 /* Adlink PCI-7841/cPCI-7841 */ 216 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, 217 PCI_ANY_ID, PCI_ANY_ID, 218 PCI_CLASS_NETWORK_OTHER << 8, ~0, 219 (kernel_ulong_t)&plx_pci_card_info_adlink 220 }, 221 { 222 /* Adlink PCI-7841/cPCI-7841 SE */ 223 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, 224 PCI_ANY_ID, PCI_ANY_ID, 225 PCI_CLASS_COMMUNICATION_OTHER << 8, ~0, 226 (kernel_ulong_t)&plx_pci_card_info_adlink_se 227 }, 228 { 229 /* esd CAN-PCI/200 */ 230 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 231 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200, 232 0, 0, 233 (kernel_ulong_t)&plx_pci_card_info_esd200 234 }, 235 { 236 /* esd CAN-CPCI/200 */ 237 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 238 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200, 239 0, 0, 240 (kernel_ulong_t)&plx_pci_card_info_esd200 241 }, 242 { 243 /* esd CAN-PCI104/200 */ 244 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 245 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200, 246 0, 0, 247 (kernel_ulong_t)&plx_pci_card_info_esd200 248 }, 249 { 250 /* esd CAN-PCI/266 */ 251 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 252 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266, 253 0, 0, 254 (kernel_ulong_t)&plx_pci_card_info_esd266 255 }, 256 { 257 /* esd CAN-PMC/266 */ 258 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 259 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266, 260 0, 0, 261 (kernel_ulong_t)&plx_pci_card_info_esd266 262 }, 263 { 264 /* esd CAN-PCIE/2000 */ 265 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 266 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000, 267 0, 0, 268 (kernel_ulong_t)&plx_pci_card_info_esd2000 269 }, 270 { 271 /* Marathon CAN-bus-PCI card */ 272 PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID, 273 PCI_ANY_ID, PCI_ANY_ID, 274 0, 0, 275 (kernel_ulong_t)&plx_pci_card_info_marathon 276 }, 277 { 278 /* TEWS TECHNOLOGIES TPMC810 card */ 279 TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810, 280 PCI_ANY_ID, PCI_ANY_ID, 281 0, 0, 282 (kernel_ulong_t)&plx_pci_card_info_tews 283 }, 284 { 0,} 285}; 286MODULE_DEVICE_TABLE(pci, plx_pci_tbl); 287 288static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port) 289{ 290 return ioread8(priv->reg_base + port); 291} 292 293static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val) 294{ 295 iowrite8(val, priv->reg_base + port); 296} 297 298/* 299 * Check if a CAN controller is present at the specified location 300 * by trying to switch 'em from the Basic mode into the PeliCAN mode. 301 * Also check states of some registers in reset mode. 302 */ 303static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) 304{ 305 int flag = 0; 306 307 /* 308 * Check registers after hardware reset (the Basic mode) 309 * See states on p. 10 of the Datasheet. 310 */ 311 if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) == 312 REG_CR_BASICCAN_INITIAL && 313 (priv->read_reg(priv, REG_SR) == REG_SR_BASICCAN_INITIAL) && 314 (priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL)) 315 flag = 1; 316 317 /* Bring the SJA1000 into the PeliCAN mode*/ 318 priv->write_reg(priv, REG_CDR, CDR_PELICAN); 319 320 /* 321 * Check registers after reset in the PeliCAN mode. 322 * See states on p. 23 of the Datasheet. 323 */ 324 if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL && 325 priv->read_reg(priv, REG_SR) == REG_SR_PELICAN_INITIAL && 326 priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL) 327 return flag; 328 329 return 0; 330} 331 332/* 333 * PLX9030/50/52 software reset 334 * Also LRESET# asserts and brings to reset device on the Local Bus (if wired). 335 * For most cards it's enough for reset the SJA1000 chips. 336 */ 337static void plx_pci_reset_common(struct pci_dev *pdev) 338{ 339 struct plx_pci_card *card = pci_get_drvdata(pdev); 340 u32 cntrl; 341 342 cntrl = ioread32(card->conf_addr + PLX_CNTRL); 343 cntrl |= PLX_PCI_RESET; 344 iowrite32(cntrl, card->conf_addr + PLX_CNTRL); 345 udelay(100); 346 cntrl ^= PLX_PCI_RESET; 347 iowrite32(cntrl, card->conf_addr + PLX_CNTRL); 348}; 349 350/* 351 * PLX9056 software reset 352 * Assert LRESET# and reset device(s) on the Local Bus (if wired). 353 */ 354static void plx9056_pci_reset_common(struct pci_dev *pdev) 355{ 356 struct plx_pci_card *card = pci_get_drvdata(pdev); 357 u32 cntrl; 358 359 /* issue a local bus reset */ 360 cntrl = ioread32(card->conf_addr + PLX9056_CNTRL); 361 cntrl |= PLX_PCI_RESET; 362 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 363 udelay(100); 364 cntrl ^= PLX_PCI_RESET; 365 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 366 367 /* reload local configuration from EEPROM */ 368 cntrl |= PLX9056_PCI_RCR; 369 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 370 371 /* 372 * There is no safe way to poll for the end 373 * of reconfiguration process. Waiting for 10ms 374 * is safe. 375 */ 376 mdelay(10); 377 378 cntrl ^= PLX9056_PCI_RCR; 379 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 380}; 381 382/* Special reset function for Marathon card */ 383static void plx_pci_reset_marathon(struct pci_dev *pdev) 384{ 385 void __iomem *reset_addr; 386 int i; 387 int reset_bar[2] = {3, 5}; 388 389 plx_pci_reset_common(pdev); 390 391 for (i = 0; i < 2; i++) { 392 reset_addr = pci_iomap(pdev, reset_bar[i], 0); 393 if (!reset_addr) { 394 dev_err(&pdev->dev, "Failed to remap reset " 395 "space %d (BAR%d)\n", i, reset_bar[i]); 396 } else { 397 /* reset the SJA1000 chip */ 398 iowrite8(0x1, reset_addr); 399 udelay(100); 400 pci_iounmap(pdev, reset_addr); 401 } 402 } 403} 404 405static void plx_pci_del_card(struct pci_dev *pdev) 406{ 407 struct plx_pci_card *card = pci_get_drvdata(pdev); 408 struct net_device *dev; 409 struct sja1000_priv *priv; 410 int i = 0; 411 412 for (i = 0; i < card->channels; i++) { 413 dev = card->net_dev[i]; 414 if (!dev) 415 continue; 416 417 dev_info(&pdev->dev, "Removing %s\n", dev->name); 418 unregister_sja1000dev(dev); 419 priv = netdev_priv(dev); 420 if (priv->reg_base) 421 pci_iounmap(pdev, priv->reg_base); 422 free_sja1000dev(dev); 423 } 424 425 card->reset_func(pdev); 426 427 /* 428 * Disable interrupts from PCI-card and disable local 429 * interrupts 430 */ 431 if (pdev->device != PCI_DEVICE_ID_PLX_9056) 432 iowrite32(0x0, card->conf_addr + PLX_INTCSR); 433 else 434 iowrite32(0x0, card->conf_addr + PLX9056_INTCSR); 435 436 if (card->conf_addr) 437 pci_iounmap(pdev, card->conf_addr); 438 439 kfree(card); 440 441 pci_disable_device(pdev); 442 pci_set_drvdata(pdev, NULL); 443} 444 445/* 446 * Probe PLX90xx based device for the SJA1000 chips and register each 447 * available CAN channel to SJA1000 Socket-CAN subsystem. 448 */ 449static int __devinit plx_pci_add_card(struct pci_dev *pdev, 450 const struct pci_device_id *ent) 451{ 452 struct sja1000_priv *priv; 453 struct net_device *dev; 454 struct plx_pci_card *card; 455 struct plx_pci_card_info *ci; 456 int err, i; 457 u32 val; 458 void __iomem *addr; 459 460 ci = (struct plx_pci_card_info *)ent->driver_data; 461 462 if (pci_enable_device(pdev) < 0) { 463 dev_err(&pdev->dev, "Failed to enable PCI device\n"); 464 return -ENODEV; 465 } 466 467 dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n", 468 ci->name, PCI_SLOT(pdev->devfn)); 469 470 /* Allocate card structures to hold addresses, ... */ 471 card = kzalloc(sizeof(*card), GFP_KERNEL); 472 if (!card) { 473 dev_err(&pdev->dev, "Unable to allocate memory\n"); 474 pci_disable_device(pdev); 475 return -ENOMEM; 476 } 477 478 pci_set_drvdata(pdev, card); 479 480 card->channels = 0; 481 482 /* Remap PLX90xx configuration space */ 483 addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size); 484 if (!addr) { 485 err = -ENOMEM; 486 dev_err(&pdev->dev, "Failed to remap configuration space " 487 "(BAR%d)\n", ci->conf_map.bar); 488 goto failure_cleanup; 489 } 490 card->conf_addr = addr + ci->conf_map.offset; 491 492 ci->reset_func(pdev); 493 card->reset_func = ci->reset_func; 494 495 /* Detect available channels */ 496 for (i = 0; i < ci->channel_count; i++) { 497 struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i]; 498 499 dev = alloc_sja1000dev(0); 500 if (!dev) { 501 err = -ENOMEM; 502 goto failure_cleanup; 503 } 504 505 card->net_dev[i] = dev; 506 priv = netdev_priv(dev); 507 priv->priv = card; 508 priv->irq_flags = IRQF_SHARED; 509 510 dev->irq = pdev->irq; 511 512 /* 513 * Remap IO space of the SJA1000 chips 514 * This is device-dependent mapping 515 */ 516 addr = pci_iomap(pdev, cm->bar, cm->size); 517 if (!addr) { 518 err = -ENOMEM; 519 dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar); 520 goto failure_cleanup; 521 } 522 523 priv->reg_base = addr + cm->offset; 524 priv->read_reg = plx_pci_read_reg; 525 priv->write_reg = plx_pci_write_reg; 526 527 /* Check if channel is present */ 528 if (plx_pci_check_sja1000(priv)) { 529 priv->can.clock.freq = ci->can_clock; 530 priv->ocr = ci->ocr; 531 priv->cdr = ci->cdr; 532 533 SET_NETDEV_DEV(dev, &pdev->dev); 534 535 /* Register SJA1000 device */ 536 err = register_sja1000dev(dev); 537 if (err) { 538 dev_err(&pdev->dev, "Registering device failed " 539 "(err=%d)\n", err); 540 free_sja1000dev(dev); 541 goto failure_cleanup; 542 } 543 544 card->channels++; 545 546 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d " 547 "registered as %s\n", i + 1, priv->reg_base, 548 dev->irq, dev->name); 549 } else { 550 dev_err(&pdev->dev, "Channel #%d not detected\n", 551 i + 1); 552 free_sja1000dev(dev); 553 } 554 } 555 556 if (!card->channels) { 557 err = -ENODEV; 558 goto failure_cleanup; 559 } 560 561 /* 562 * Enable interrupts from PCI-card (PLX90xx) and enable Local_1, 563 * Local_2 interrupts from the SJA1000 chips 564 */ 565 if (pdev->device != PCI_DEVICE_ID_PLX_9056) { 566 val = ioread32(card->conf_addr + PLX_INTCSR); 567 if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH) 568 val |= PLX_LINT1_EN | PLX_PCI_INT_EN; 569 else 570 val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN; 571 iowrite32(val, card->conf_addr + PLX_INTCSR); 572 } else { 573 iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN, 574 card->conf_addr + PLX9056_INTCSR); 575 } 576 return 0; 577 578failure_cleanup: 579 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err); 580 581 plx_pci_del_card(pdev); 582 583 return err; 584} 585 586static struct pci_driver plx_pci_driver = { 587 .name = DRV_NAME, 588 .id_table = plx_pci_tbl, 589 .probe = plx_pci_add_card, 590 .remove = plx_pci_del_card, 591}; 592 593static int __init plx_pci_init(void) 594{ 595 return pci_register_driver(&plx_pci_driver); 596} 597 598static void __exit plx_pci_exit(void) 599{ 600 pci_unregister_driver(&plx_pci_driver); 601} 602 603module_init(plx_pci_init); 604module_exit(plx_pci_exit); 605