plx_pci.c revision 951f2f960e5bbce20309de44626cf11d17847712
1/* 2 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su> 3 * 4 * Derived from the ems_pci.c driver: 5 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com> 6 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com> 7 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 21 */ 22 23#include <linux/kernel.h> 24#include <linux/module.h> 25#include <linux/interrupt.h> 26#include <linux/netdevice.h> 27#include <linux/delay.h> 28#include <linux/slab.h> 29#include <linux/pci.h> 30#include <linux/can/dev.h> 31#include <linux/io.h> 32 33#include "sja1000.h" 34 35#define DRV_NAME "sja1000_plx_pci" 36 37MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>"); 38MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with " 39 "the SJA1000 chips"); 40MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, " 41 "Adlink PCI-7841/cPCI-7841 SE, " 42 "Marathon CAN-bus-PCI, " 43 "TEWS TECHNOLOGIES TPMC810, " 44 "esd CAN-PCI/CPCI/PCI104/200, " 45 "esd CAN-PCI/PMC/266, " 46 "esd CAN-PCIe/2000") 47MODULE_LICENSE("GPL v2"); 48 49#define PLX_PCI_MAX_CHAN 2 50 51struct plx_pci_card { 52 int channels; /* detected channels count */ 53 struct net_device *net_dev[PLX_PCI_MAX_CHAN]; 54 void __iomem *conf_addr; 55 56 /* Pointer to device-dependent reset function */ 57 void (*reset_func)(struct pci_dev *pdev); 58}; 59 60#define PLX_PCI_CAN_CLOCK (16000000 / 2) 61 62/* PLX9030/9050/9052 registers */ 63#define PLX_INTCSR 0x4c /* Interrupt Control/Status */ 64#define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response, 65 * Serial EEPROM, and Initialization 66 * Control register 67 */ 68 69#define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */ 70#define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */ 71#define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */ 72#define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */ 73 74/* PLX9056 registers */ 75#define PLX9056_INTCSR 0x68 /* Interrupt Control/Status */ 76#define PLX9056_CNTRL 0x6c /* Control / Software Reset */ 77 78#define PLX9056_LINTI (1 << 11) 79#define PLX9056_PCI_INT_EN (1 << 8) 80#define PLX9056_PCI_RCR (1 << 29) /* Read Configuration Registers */ 81 82/* 83 * The board configuration is probably following: 84 * RX1 is connected to ground. 85 * TX1 is not connected. 86 * CLKO is not connected. 87 * Setting the OCR register to 0xDA is a good idea. 88 * This means normal output mode, push-pull and the correct polarity. 89 */ 90#define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL) 91 92/* 93 * In the CDR register, you should set CBP to 1. 94 * You will probably also want to set the clock divider value to 7 95 * (meaning direct oscillator output) because the second SJA1000 chip 96 * is driven by the first one CLKOUT output. 97 */ 98#define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) 99 100/* SJA1000 Control Register in the BasicCAN Mode */ 101#define REG_CR 0x00 102 103/* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/ 104#define REG_CR_BASICCAN_INITIAL 0x21 105#define REG_CR_BASICCAN_INITIAL_MASK 0xa1 106#define REG_SR_BASICCAN_INITIAL 0x0c 107#define REG_IR_BASICCAN_INITIAL 0xe0 108 109/* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/ 110#define REG_MOD_PELICAN_INITIAL 0x01 111#define REG_SR_PELICAN_INITIAL 0x3c 112#define REG_IR_PELICAN_INITIAL 0x00 113 114#define ADLINK_PCI_VENDOR_ID 0x144A 115#define ADLINK_PCI_DEVICE_ID 0x7841 116 117#define ESD_PCI_SUB_SYS_ID_PCI200 0x0004 118#define ESD_PCI_SUB_SYS_ID_PCI266 0x0009 119#define ESD_PCI_SUB_SYS_ID_PMC266 0x000e 120#define ESD_PCI_SUB_SYS_ID_CPCI200 0x010b 121#define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200 122#define ESD_PCI_SUB_SYS_ID_PCI104200 0x0501 123 124#define MARATHON_PCI_DEVICE_ID 0x2715 125 126#define TEWS_PCI_VENDOR_ID 0x1498 127#define TEWS_PCI_DEVICE_ID_TMPC810 0x032A 128 129static void plx_pci_reset_common(struct pci_dev *pdev); 130static void plx_pci_reset_marathon(struct pci_dev *pdev); 131static void plx9056_pci_reset_common(struct pci_dev *pdev); 132 133struct plx_pci_channel_map { 134 u32 bar; 135 u32 offset; 136 u32 size; /* 0x00 - auto, e.g. length of entire bar */ 137}; 138 139struct plx_pci_card_info { 140 const char *name; 141 int channel_count; 142 u32 can_clock; 143 u8 ocr; /* output control register */ 144 u8 cdr; /* clock divider register */ 145 146 /* Parameters for mapping local configuration space */ 147 struct plx_pci_channel_map conf_map; 148 149 /* Parameters for mapping the SJA1000 chips */ 150 struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN]; 151 152 /* Pointer to device-dependent reset function */ 153 void (*reset_func)(struct pci_dev *pdev); 154}; 155 156static struct plx_pci_card_info plx_pci_card_info_adlink __devinitdata = { 157 "Adlink PCI-7841/cPCI-7841", 2, 158 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 159 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, 160 &plx_pci_reset_common 161 /* based on PLX9052 */ 162}; 163 164static struct plx_pci_card_info plx_pci_card_info_adlink_se __devinitdata = { 165 "Adlink PCI-7841/cPCI-7841 SE", 2, 166 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 167 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, 168 &plx_pci_reset_common 169 /* based on PLX9052 */ 170}; 171 172static struct plx_pci_card_info plx_pci_card_info_esd200 __devinitdata = { 173 "esd CAN-PCI/CPCI/PCI104/200", 2, 174 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 175 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 176 &plx_pci_reset_common 177 /* based on PLX9030/9050 */ 178}; 179 180static struct plx_pci_card_info plx_pci_card_info_esd266 __devinitdata = { 181 "esd CAN-PCI/PMC/266", 2, 182 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 183 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 184 &plx9056_pci_reset_common 185 /* based on PLX9056 */ 186}; 187 188static struct plx_pci_card_info plx_pci_card_info_esd2000 __devinitdata = { 189 "esd CAN-PCIe/2000", 2, 190 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 191 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 192 &plx9056_pci_reset_common 193 /* based on PEX8311 */ 194}; 195 196static struct plx_pci_card_info plx_pci_card_info_marathon __devinitdata = { 197 "Marathon CAN-bus-PCI", 2, 198 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 199 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} }, 200 &plx_pci_reset_marathon 201 /* based on PLX9052 */ 202}; 203 204static struct plx_pci_card_info plx_pci_card_info_tews __devinitdata = { 205 "TEWS TECHNOLOGIES TPMC810", 2, 206 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 207 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, 208 &plx_pci_reset_common 209 /* based on PLX9030 */ 210}; 211 212static DEFINE_PCI_DEVICE_TABLE(plx_pci_tbl) = { 213 { 214 /* Adlink PCI-7841/cPCI-7841 */ 215 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, 216 PCI_ANY_ID, PCI_ANY_ID, 217 PCI_CLASS_NETWORK_OTHER << 8, ~0, 218 (kernel_ulong_t)&plx_pci_card_info_adlink 219 }, 220 { 221 /* Adlink PCI-7841/cPCI-7841 SE */ 222 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, 223 PCI_ANY_ID, PCI_ANY_ID, 224 PCI_CLASS_COMMUNICATION_OTHER << 8, ~0, 225 (kernel_ulong_t)&plx_pci_card_info_adlink_se 226 }, 227 { 228 /* esd CAN-PCI/200 */ 229 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 230 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200, 231 0, 0, 232 (kernel_ulong_t)&plx_pci_card_info_esd200 233 }, 234 { 235 /* esd CAN-CPCI/200 */ 236 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 237 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200, 238 0, 0, 239 (kernel_ulong_t)&plx_pci_card_info_esd200 240 }, 241 { 242 /* esd CAN-PCI104/200 */ 243 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 244 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200, 245 0, 0, 246 (kernel_ulong_t)&plx_pci_card_info_esd200 247 }, 248 { 249 /* esd CAN-PCI/266 */ 250 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 251 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266, 252 0, 0, 253 (kernel_ulong_t)&plx_pci_card_info_esd266 254 }, 255 { 256 /* esd CAN-PMC/266 */ 257 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 258 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266, 259 0, 0, 260 (kernel_ulong_t)&plx_pci_card_info_esd266 261 }, 262 { 263 /* esd CAN-PCIE/2000 */ 264 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 265 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000, 266 0, 0, 267 (kernel_ulong_t)&plx_pci_card_info_esd2000 268 }, 269 { 270 /* Marathon CAN-bus-PCI card */ 271 PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID, 272 PCI_ANY_ID, PCI_ANY_ID, 273 0, 0, 274 (kernel_ulong_t)&plx_pci_card_info_marathon 275 }, 276 { 277 /* TEWS TECHNOLOGIES TPMC810 card */ 278 TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810, 279 PCI_ANY_ID, PCI_ANY_ID, 280 0, 0, 281 (kernel_ulong_t)&plx_pci_card_info_tews 282 }, 283 { 0,} 284}; 285MODULE_DEVICE_TABLE(pci, plx_pci_tbl); 286 287static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port) 288{ 289 return ioread8(priv->reg_base + port); 290} 291 292static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val) 293{ 294 iowrite8(val, priv->reg_base + port); 295} 296 297/* 298 * Check if a CAN controller is present at the specified location 299 * by trying to switch 'em from the Basic mode into the PeliCAN mode. 300 * Also check states of some registers in reset mode. 301 */ 302static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) 303{ 304 int flag = 0; 305 306 /* 307 * Check registers after hardware reset (the Basic mode) 308 * See states on p. 10 of the Datasheet. 309 */ 310 if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) == 311 REG_CR_BASICCAN_INITIAL && 312 (priv->read_reg(priv, REG_SR) == REG_SR_BASICCAN_INITIAL) && 313 (priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL)) 314 flag = 1; 315 316 /* Bring the SJA1000 into the PeliCAN mode*/ 317 priv->write_reg(priv, REG_CDR, CDR_PELICAN); 318 319 /* 320 * Check registers after reset in the PeliCAN mode. 321 * See states on p. 23 of the Datasheet. 322 */ 323 if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL && 324 priv->read_reg(priv, REG_SR) == REG_SR_PELICAN_INITIAL && 325 priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL) 326 return flag; 327 328 return 0; 329} 330 331/* 332 * PLX9030/50/52 software reset 333 * Also LRESET# asserts and brings to reset device on the Local Bus (if wired). 334 * For most cards it's enough for reset the SJA1000 chips. 335 */ 336static void plx_pci_reset_common(struct pci_dev *pdev) 337{ 338 struct plx_pci_card *card = pci_get_drvdata(pdev); 339 u32 cntrl; 340 341 cntrl = ioread32(card->conf_addr + PLX_CNTRL); 342 cntrl |= PLX_PCI_RESET; 343 iowrite32(cntrl, card->conf_addr + PLX_CNTRL); 344 udelay(100); 345 cntrl ^= PLX_PCI_RESET; 346 iowrite32(cntrl, card->conf_addr + PLX_CNTRL); 347}; 348 349/* 350 * PLX9056 software reset 351 * Assert LRESET# and reset device(s) on the Local Bus (if wired). 352 */ 353static void plx9056_pci_reset_common(struct pci_dev *pdev) 354{ 355 struct plx_pci_card *card = pci_get_drvdata(pdev); 356 u32 cntrl; 357 358 /* issue a local bus reset */ 359 cntrl = ioread32(card->conf_addr + PLX9056_CNTRL); 360 cntrl |= PLX_PCI_RESET; 361 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 362 udelay(100); 363 cntrl ^= PLX_PCI_RESET; 364 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 365 366 /* reload local configuration from EEPROM */ 367 cntrl |= PLX9056_PCI_RCR; 368 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 369 370 /* 371 * There is no safe way to poll for the end 372 * of reconfiguration process. Waiting for 10ms 373 * is safe. 374 */ 375 mdelay(10); 376 377 cntrl ^= PLX9056_PCI_RCR; 378 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 379}; 380 381/* Special reset function for Marathon card */ 382static void plx_pci_reset_marathon(struct pci_dev *pdev) 383{ 384 void __iomem *reset_addr; 385 int i; 386 static const int reset_bar[2] = {3, 5}; 387 388 plx_pci_reset_common(pdev); 389 390 for (i = 0; i < 2; i++) { 391 reset_addr = pci_iomap(pdev, reset_bar[i], 0); 392 if (!reset_addr) { 393 dev_err(&pdev->dev, "Failed to remap reset " 394 "space %d (BAR%d)\n", i, reset_bar[i]); 395 } else { 396 /* reset the SJA1000 chip */ 397 iowrite8(0x1, reset_addr); 398 udelay(100); 399 pci_iounmap(pdev, reset_addr); 400 } 401 } 402} 403 404static void plx_pci_del_card(struct pci_dev *pdev) 405{ 406 struct plx_pci_card *card = pci_get_drvdata(pdev); 407 struct net_device *dev; 408 struct sja1000_priv *priv; 409 int i = 0; 410 411 for (i = 0; i < PLX_PCI_MAX_CHAN; i++) { 412 dev = card->net_dev[i]; 413 if (!dev) 414 continue; 415 416 dev_info(&pdev->dev, "Removing %s\n", dev->name); 417 unregister_sja1000dev(dev); 418 priv = netdev_priv(dev); 419 if (priv->reg_base) 420 pci_iounmap(pdev, priv->reg_base); 421 free_sja1000dev(dev); 422 } 423 424 card->reset_func(pdev); 425 426 /* 427 * Disable interrupts from PCI-card and disable local 428 * interrupts 429 */ 430 if (pdev->device != PCI_DEVICE_ID_PLX_9056) 431 iowrite32(0x0, card->conf_addr + PLX_INTCSR); 432 else 433 iowrite32(0x0, card->conf_addr + PLX9056_INTCSR); 434 435 if (card->conf_addr) 436 pci_iounmap(pdev, card->conf_addr); 437 438 kfree(card); 439 440 pci_disable_device(pdev); 441 pci_set_drvdata(pdev, NULL); 442} 443 444/* 445 * Probe PLX90xx based device for the SJA1000 chips and register each 446 * available CAN channel to SJA1000 Socket-CAN subsystem. 447 */ 448static int __devinit plx_pci_add_card(struct pci_dev *pdev, 449 const struct pci_device_id *ent) 450{ 451 struct sja1000_priv *priv; 452 struct net_device *dev; 453 struct plx_pci_card *card; 454 struct plx_pci_card_info *ci; 455 int err, i; 456 u32 val; 457 void __iomem *addr; 458 459 ci = (struct plx_pci_card_info *)ent->driver_data; 460 461 if (pci_enable_device(pdev) < 0) { 462 dev_err(&pdev->dev, "Failed to enable PCI device\n"); 463 return -ENODEV; 464 } 465 466 dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n", 467 ci->name, PCI_SLOT(pdev->devfn)); 468 469 /* Allocate card structures to hold addresses, ... */ 470 card = kzalloc(sizeof(*card), GFP_KERNEL); 471 if (!card) { 472 dev_err(&pdev->dev, "Unable to allocate memory\n"); 473 pci_disable_device(pdev); 474 return -ENOMEM; 475 } 476 477 pci_set_drvdata(pdev, card); 478 479 card->channels = 0; 480 481 /* Remap PLX90xx configuration space */ 482 addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size); 483 if (!addr) { 484 err = -ENOMEM; 485 dev_err(&pdev->dev, "Failed to remap configuration space " 486 "(BAR%d)\n", ci->conf_map.bar); 487 goto failure_cleanup; 488 } 489 card->conf_addr = addr + ci->conf_map.offset; 490 491 ci->reset_func(pdev); 492 card->reset_func = ci->reset_func; 493 494 /* Detect available channels */ 495 for (i = 0; i < ci->channel_count; i++) { 496 struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i]; 497 498 dev = alloc_sja1000dev(0); 499 if (!dev) { 500 err = -ENOMEM; 501 goto failure_cleanup; 502 } 503 504 card->net_dev[i] = dev; 505 priv = netdev_priv(dev); 506 priv->priv = card; 507 priv->irq_flags = IRQF_SHARED; 508 509 dev->irq = pdev->irq; 510 511 /* 512 * Remap IO space of the SJA1000 chips 513 * This is device-dependent mapping 514 */ 515 addr = pci_iomap(pdev, cm->bar, cm->size); 516 if (!addr) { 517 err = -ENOMEM; 518 dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar); 519 goto failure_cleanup; 520 } 521 522 priv->reg_base = addr + cm->offset; 523 priv->read_reg = plx_pci_read_reg; 524 priv->write_reg = plx_pci_write_reg; 525 526 /* Check if channel is present */ 527 if (plx_pci_check_sja1000(priv)) { 528 priv->can.clock.freq = ci->can_clock; 529 priv->ocr = ci->ocr; 530 priv->cdr = ci->cdr; 531 532 SET_NETDEV_DEV(dev, &pdev->dev); 533 534 /* Register SJA1000 device */ 535 err = register_sja1000dev(dev); 536 if (err) { 537 dev_err(&pdev->dev, "Registering device failed " 538 "(err=%d)\n", err); 539 goto failure_cleanup; 540 } 541 542 card->channels++; 543 544 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d " 545 "registered as %s\n", i + 1, priv->reg_base, 546 dev->irq, dev->name); 547 } else { 548 dev_err(&pdev->dev, "Channel #%d not detected\n", 549 i + 1); 550 free_sja1000dev(dev); 551 card->net_dev[i] = NULL; 552 } 553 } 554 555 if (!card->channels) { 556 err = -ENODEV; 557 goto failure_cleanup; 558 } 559 560 /* 561 * Enable interrupts from PCI-card (PLX90xx) and enable Local_1, 562 * Local_2 interrupts from the SJA1000 chips 563 */ 564 if (pdev->device != PCI_DEVICE_ID_PLX_9056) { 565 val = ioread32(card->conf_addr + PLX_INTCSR); 566 if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH) 567 val |= PLX_LINT1_EN | PLX_PCI_INT_EN; 568 else 569 val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN; 570 iowrite32(val, card->conf_addr + PLX_INTCSR); 571 } else { 572 iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN, 573 card->conf_addr + PLX9056_INTCSR); 574 } 575 return 0; 576 577failure_cleanup: 578 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err); 579 580 plx_pci_del_card(pdev); 581 582 return err; 583} 584 585static struct pci_driver plx_pci_driver = { 586 .name = DRV_NAME, 587 .id_table = plx_pci_tbl, 588 .probe = plx_pci_add_card, 589 .remove = plx_pci_del_card, 590}; 591 592static int __init plx_pci_init(void) 593{ 594 return pci_register_driver(&plx_pci_driver); 595} 596 597static void __exit plx_pci_exit(void) 598{ 599 pci_unregister_driver(&plx_pci_driver); 600} 601 602module_init(plx_pci_init); 603module_exit(plx_pci_exit); 604