ti_hecc.c revision 3ccd4c6167d3b39d52631767ebbf8b5677c5855d
1/* 2 * TI HECC (CAN) device driver 3 * 4 * This driver supports TI's HECC (High End CAN Controller module) and the 5 * specs for the same is available at <http://www.ti.com> 6 * 7 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation version 2. 12 * 13 * This program is distributed as is WITHOUT ANY WARRANTY of any 14 * kind, whether express or implied; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20/* 21 * Your platform definitions should specify module ram offsets and interrupt 22 * number to use as follows: 23 * 24 * static struct ti_hecc_platform_data am3517_evm_hecc_pdata = { 25 * .scc_hecc_offset = 0, 26 * .scc_ram_offset = 0x3000, 27 * .hecc_ram_offset = 0x3000, 28 * .mbx_offset = 0x2000, 29 * .int_line = 0, 30 * .revision = 1, 31 * }; 32 * 33 * Please see include/can/platform/ti_hecc.h for description of above fields 34 * 35 */ 36 37#include <linux/module.h> 38#include <linux/init.h> 39#include <linux/kernel.h> 40#include <linux/types.h> 41#include <linux/interrupt.h> 42#include <linux/errno.h> 43#include <linux/netdevice.h> 44#include <linux/skbuff.h> 45#include <linux/platform_device.h> 46#include <linux/clk.h> 47 48#include <linux/can.h> 49#include <linux/can/dev.h> 50#include <linux/can/error.h> 51#include <linux/can/platform/ti_hecc.h> 52 53#define DRV_NAME "ti_hecc" 54#define HECC_MODULE_VERSION "0.7" 55MODULE_VERSION(HECC_MODULE_VERSION); 56#define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION 57 58/* TX / RX Mailbox Configuration */ 59#define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */ 60#define MAX_TX_PRIO 0x3F /* hardware value - do not change */ 61 62/* 63 * Important Note: TX mailbox configuration 64 * TX mailboxes should be restricted to the number of SKB buffers to avoid 65 * maintaining SKB buffers separately. TX mailboxes should be a power of 2 66 * for the mailbox logic to work. Top mailbox numbers are reserved for RX 67 * and lower mailboxes for TX. 68 * 69 * HECC_MAX_TX_MBOX HECC_MB_TX_SHIFT 70 * 4 (default) 2 71 * 8 3 72 * 16 4 73 */ 74#define HECC_MB_TX_SHIFT 2 /* as per table above */ 75#define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT) 76 77#define HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT) 78#define HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT) 79#define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1) 80#define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK) 81#define HECC_TX_MBOX_MASK (~(BIT(HECC_MAX_TX_MBOX) - 1)) 82#define HECC_DEF_NAPI_WEIGHT HECC_MAX_RX_MBOX 83 84/* 85 * Important Note: RX mailbox configuration 86 * RX mailboxes are further logically split into two - main and buffer 87 * mailboxes. The goal is to get all packets into main mailboxes as 88 * driven by mailbox number and receive priority (higher to lower) and 89 * buffer mailboxes are used to receive pkts while main mailboxes are being 90 * processed. This ensures in-order packet reception. 91 * 92 * Here are the recommended values for buffer mailbox. Note that RX mailboxes 93 * start after TX mailboxes: 94 * 95 * HECC_MAX_RX_MBOX HECC_RX_BUFFER_MBOX No of buffer mailboxes 96 * 28 12 8 97 * 16 20 4 98 */ 99 100#define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX) 101#define HECC_RX_BUFFER_MBOX 12 /* as per table above */ 102#define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1) 103#define HECC_RX_HIGH_MBOX_MASK (~(BIT(HECC_RX_BUFFER_MBOX) - 1)) 104 105/* TI HECC module registers */ 106#define HECC_CANME 0x0 /* Mailbox enable */ 107#define HECC_CANMD 0x4 /* Mailbox direction */ 108#define HECC_CANTRS 0x8 /* Transmit request set */ 109#define HECC_CANTRR 0xC /* Transmit request */ 110#define HECC_CANTA 0x10 /* Transmission acknowledge */ 111#define HECC_CANAA 0x14 /* Abort acknowledge */ 112#define HECC_CANRMP 0x18 /* Receive message pending */ 113#define HECC_CANRML 0x1C /* Remote message lost */ 114#define HECC_CANRFP 0x20 /* Remote frame pending */ 115#define HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */ 116#define HECC_CANMC 0x28 /* Master control */ 117#define HECC_CANBTC 0x2C /* Bit timing configuration */ 118#define HECC_CANES 0x30 /* Error and status */ 119#define HECC_CANTEC 0x34 /* Transmit error counter */ 120#define HECC_CANREC 0x38 /* Receive error counter */ 121#define HECC_CANGIF0 0x3C /* Global interrupt flag 0 */ 122#define HECC_CANGIM 0x40 /* Global interrupt mask */ 123#define HECC_CANGIF1 0x44 /* Global interrupt flag 1 */ 124#define HECC_CANMIM 0x48 /* Mailbox interrupt mask */ 125#define HECC_CANMIL 0x4C /* Mailbox interrupt level */ 126#define HECC_CANOPC 0x50 /* Overwrite protection control */ 127#define HECC_CANTIOC 0x54 /* Transmit I/O control */ 128#define HECC_CANRIOC 0x58 /* Receive I/O control */ 129#define HECC_CANLNT 0x5C /* HECC only: Local network time */ 130#define HECC_CANTOC 0x60 /* HECC only: Time-out control */ 131#define HECC_CANTOS 0x64 /* HECC only: Time-out status */ 132#define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */ 133#define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */ 134 135/* Mailbox registers */ 136#define HECC_CANMID 0x0 137#define HECC_CANMCF 0x4 138#define HECC_CANMDL 0x8 139#define HECC_CANMDH 0xC 140 141#define HECC_SET_REG 0xFFFFFFFF 142#define HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */ 143#define HECC_CCE_WAIT_COUNT 100 /* Wait for ~1 sec for CCE bit */ 144 145#define HECC_CANMC_SCM BIT(13) /* SCC compat mode */ 146#define HECC_CANMC_CCR BIT(12) /* Change config request */ 147#define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */ 148#define HECC_CANMC_ABO BIT(7) /* Auto Bus On */ 149#define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */ 150#define HECC_CANMC_SRES BIT(5) /* Software reset */ 151 152#define HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */ 153#define HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */ 154 155#define HECC_CANMID_IDE BIT(31) /* Extended frame format */ 156#define HECC_CANMID_AME BIT(30) /* Acceptance mask enable */ 157#define HECC_CANMID_AAM BIT(29) /* Auto answer mode */ 158 159#define HECC_CANES_FE BIT(24) /* form error */ 160#define HECC_CANES_BE BIT(23) /* bit error */ 161#define HECC_CANES_SA1 BIT(22) /* stuck at dominant error */ 162#define HECC_CANES_CRCE BIT(21) /* CRC error */ 163#define HECC_CANES_SE BIT(20) /* stuff bit error */ 164#define HECC_CANES_ACKE BIT(19) /* ack error */ 165#define HECC_CANES_BO BIT(18) /* Bus off status */ 166#define HECC_CANES_EP BIT(17) /* Error passive status */ 167#define HECC_CANES_EW BIT(16) /* Error warning status */ 168#define HECC_CANES_SMA BIT(5) /* suspend mode ack */ 169#define HECC_CANES_CCE BIT(4) /* Change config enabled */ 170#define HECC_CANES_PDA BIT(3) /* Power down mode ack */ 171 172#define HECC_CANBTC_SAM BIT(7) /* sample points */ 173 174#define HECC_BUS_ERROR (HECC_CANES_FE | HECC_CANES_BE |\ 175 HECC_CANES_CRCE | HECC_CANES_SE |\ 176 HECC_CANES_ACKE) 177 178#define HECC_CANMCF_RTR BIT(4) /* Remote transmit request */ 179 180#define HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */ 181#define HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */ 182#define HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */ 183#define HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */ 184#define HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */ 185#define HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */ 186#define HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */ 187#define HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */ 188#define HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */ 189#define HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */ 190#define HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */ 191#define HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */ 192#define HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */ 193#define HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */ 194#define HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */ 195 196/* CAN Bittiming constants as per HECC specs */ 197static struct can_bittiming_const ti_hecc_bittiming_const = { 198 .name = DRV_NAME, 199 .tseg1_min = 1, 200 .tseg1_max = 16, 201 .tseg2_min = 1, 202 .tseg2_max = 8, 203 .sjw_max = 4, 204 .brp_min = 1, 205 .brp_max = 256, 206 .brp_inc = 1, 207}; 208 209struct ti_hecc_priv { 210 struct can_priv can; /* MUST be first member/field */ 211 struct napi_struct napi; 212 struct net_device *ndev; 213 struct clk *clk; 214 void __iomem *base; 215 u32 scc_ram_offset; 216 u32 hecc_ram_offset; 217 u32 mbx_offset; 218 u32 int_line; 219 spinlock_t mbx_lock; /* CANME register needs protection */ 220 u32 tx_head; 221 u32 tx_tail; 222 u32 rx_next; 223}; 224 225static inline int get_tx_head_mb(struct ti_hecc_priv *priv) 226{ 227 return priv->tx_head & HECC_TX_MB_MASK; 228} 229 230static inline int get_tx_tail_mb(struct ti_hecc_priv *priv) 231{ 232 return priv->tx_tail & HECC_TX_MB_MASK; 233} 234 235static inline int get_tx_head_prio(struct ti_hecc_priv *priv) 236{ 237 return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO; 238} 239 240static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val) 241{ 242 __raw_writel(val, priv->base + priv->hecc_ram_offset + mbxno * 4); 243} 244 245static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno, 246 u32 reg, u32 val) 247{ 248 __raw_writel(val, priv->base + priv->mbx_offset + mbxno * 0x10 + 249 reg); 250} 251 252static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg) 253{ 254 return __raw_readl(priv->base + priv->mbx_offset + mbxno * 0x10 + 255 reg); 256} 257 258static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val) 259{ 260 __raw_writel(val, priv->base + reg); 261} 262 263static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg) 264{ 265 return __raw_readl(priv->base + reg); 266} 267 268static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg, 269 u32 bit_mask) 270{ 271 hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask); 272} 273 274static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg, 275 u32 bit_mask) 276{ 277 hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask); 278} 279 280static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask) 281{ 282 return (hecc_read(priv, reg) & bit_mask) ? 1 : 0; 283} 284 285static int ti_hecc_get_state(const struct net_device *ndev, 286 enum can_state *state) 287{ 288 struct ti_hecc_priv *priv = netdev_priv(ndev); 289 290 *state = priv->can.state; 291 return 0; 292} 293 294static int ti_hecc_set_btc(struct ti_hecc_priv *priv) 295{ 296 struct can_bittiming *bit_timing = &priv->can.bittiming; 297 u32 can_btc; 298 299 can_btc = (bit_timing->phase_seg2 - 1) & 0x7; 300 can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1) 301 & 0xF) << 3; 302 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) { 303 if (bit_timing->brp > 4) 304 can_btc |= HECC_CANBTC_SAM; 305 else 306 dev_warn(priv->ndev->dev.parent, "WARN: Triple" \ 307 "sampling not set due to h/w limitations"); 308 } 309 can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8; 310 can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16; 311 312 /* ERM being set to 0 by default meaning resync at falling edge */ 313 314 hecc_write(priv, HECC_CANBTC, can_btc); 315 dev_info(priv->ndev->dev.parent, "setting CANBTC=%#x\n", can_btc); 316 317 return 0; 318} 319 320static void ti_hecc_reset(struct net_device *ndev) 321{ 322 u32 cnt; 323 struct ti_hecc_priv *priv = netdev_priv(ndev); 324 325 dev_dbg(ndev->dev.parent, "resetting hecc ...\n"); 326 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES); 327 328 /* Set change control request and wait till enabled */ 329 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR); 330 331 /* 332 * INFO: It has been observed that at times CCE bit may not be 333 * set and hw seems to be ok even if this bit is not set so 334 * timing out with a timing of 1ms to respect the specs 335 */ 336 cnt = HECC_CCE_WAIT_COUNT; 337 while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) { 338 --cnt; 339 udelay(10); 340 } 341 342 /* 343 * Note: On HECC, BTC can be programmed only in initialization mode, so 344 * it is expected that the can bittiming parameters are set via ip 345 * utility before the device is opened 346 */ 347 ti_hecc_set_btc(priv); 348 349 /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */ 350 hecc_write(priv, HECC_CANMC, 0); 351 352 /* 353 * INFO: CAN net stack handles bus off and hence disabling auto-bus-on 354 * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO); 355 */ 356 357 /* 358 * INFO: It has been observed that at times CCE bit may not be 359 * set and hw seems to be ok even if this bit is not set so 360 */ 361 cnt = HECC_CCE_WAIT_COUNT; 362 while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) { 363 --cnt; 364 udelay(10); 365 } 366 367 /* Enable TX and RX I/O Control pins */ 368 hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN); 369 hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN); 370 371 /* Clear registers for clean operation */ 372 hecc_write(priv, HECC_CANTA, HECC_SET_REG); 373 hecc_write(priv, HECC_CANRMP, HECC_SET_REG); 374 hecc_write(priv, HECC_CANGIF0, HECC_SET_REG); 375 hecc_write(priv, HECC_CANGIF1, HECC_SET_REG); 376 hecc_write(priv, HECC_CANME, 0); 377 hecc_write(priv, HECC_CANMD, 0); 378 379 /* SCC compat mode NOT supported (and not needed too) */ 380 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM); 381} 382 383static void ti_hecc_start(struct net_device *ndev) 384{ 385 struct ti_hecc_priv *priv = netdev_priv(ndev); 386 u32 cnt, mbxno, mbx_mask; 387 388 /* put HECC in initialization mode and set btc */ 389 ti_hecc_reset(ndev); 390 391 priv->tx_head = priv->tx_tail = HECC_TX_MASK; 392 priv->rx_next = HECC_RX_FIRST_MBOX; 393 394 /* Enable local and global acceptance mask registers */ 395 hecc_write(priv, HECC_CANGAM, HECC_SET_REG); 396 397 /* Prepare configured mailboxes to receive messages */ 398 for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) { 399 mbxno = HECC_MAX_MAILBOXES - 1 - cnt; 400 mbx_mask = BIT(mbxno); 401 hecc_clear_bit(priv, HECC_CANME, mbx_mask); 402 hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME); 403 hecc_write_lam(priv, mbxno, HECC_SET_REG); 404 hecc_set_bit(priv, HECC_CANMD, mbx_mask); 405 hecc_set_bit(priv, HECC_CANME, mbx_mask); 406 hecc_set_bit(priv, HECC_CANMIM, mbx_mask); 407 } 408 409 /* Prevent message over-write & Enable interrupts */ 410 hecc_write(priv, HECC_CANOPC, HECC_SET_REG); 411 if (priv->int_line) { 412 hecc_write(priv, HECC_CANMIL, HECC_SET_REG); 413 hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK | 414 HECC_CANGIM_I1EN | HECC_CANGIM_SIL); 415 } else { 416 hecc_write(priv, HECC_CANMIL, 0); 417 hecc_write(priv, HECC_CANGIM, 418 HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN); 419 } 420 priv->can.state = CAN_STATE_ERROR_ACTIVE; 421} 422 423static void ti_hecc_stop(struct net_device *ndev) 424{ 425 struct ti_hecc_priv *priv = netdev_priv(ndev); 426 427 /* Disable interrupts and disable mailboxes */ 428 hecc_write(priv, HECC_CANGIM, 0); 429 hecc_write(priv, HECC_CANMIM, 0); 430 hecc_write(priv, HECC_CANME, 0); 431 priv->can.state = CAN_STATE_STOPPED; 432} 433 434static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode) 435{ 436 int ret = 0; 437 438 switch (mode) { 439 case CAN_MODE_START: 440 ti_hecc_start(ndev); 441 netif_wake_queue(ndev); 442 break; 443 default: 444 ret = -EOPNOTSUPP; 445 break; 446 } 447 448 return ret; 449} 450 451/* 452 * ti_hecc_xmit: HECC Transmit 453 * 454 * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the 455 * priority of the mailbox for tranmission is dependent upon priority setting 456 * field in mailbox registers. The mailbox with highest value in priority field 457 * is transmitted first. Only when two mailboxes have the same value in 458 * priority field the highest numbered mailbox is transmitted first. 459 * 460 * To utilize the HECC priority feature as described above we start with the 461 * highest numbered mailbox with highest priority level and move on to the next 462 * mailbox with the same priority level and so on. Once we loop through all the 463 * transmit mailboxes we choose the next priority level (lower) and so on 464 * until we reach the lowest priority level on the lowest numbered mailbox 465 * when we stop transmission until all mailboxes are transmitted and then 466 * restart at highest numbered mailbox with highest priority. 467 * 468 * Two counters (head and tail) are used to track the next mailbox to transmit 469 * and to track the echo buffer for already transmitted mailbox. The queue 470 * is stopped when all the mailboxes are busy or when there is a priority 471 * value roll-over happens. 472 */ 473static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev) 474{ 475 struct ti_hecc_priv *priv = netdev_priv(ndev); 476 struct can_frame *cf = (struct can_frame *)skb->data; 477 u32 mbxno, mbx_mask, data; 478 unsigned long flags; 479 480 if (can_dropped_invalid_skb(ndev, skb)) 481 return NETDEV_TX_OK; 482 483 mbxno = get_tx_head_mb(priv); 484 mbx_mask = BIT(mbxno); 485 spin_lock_irqsave(&priv->mbx_lock, flags); 486 if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) { 487 spin_unlock_irqrestore(&priv->mbx_lock, flags); 488 netif_stop_queue(ndev); 489 dev_err(priv->ndev->dev.parent, 490 "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n", 491 priv->tx_head, priv->tx_tail); 492 return NETDEV_TX_BUSY; 493 } 494 spin_unlock_irqrestore(&priv->mbx_lock, flags); 495 496 /* Prepare mailbox for transmission */ 497 if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */ 498 data |= HECC_CANMCF_RTR; 499 data |= get_tx_head_prio(priv) << 8; 500 hecc_write_mbx(priv, mbxno, HECC_CANMCF, data); 501 502 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ 503 data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE; 504 else /* Standard frame format */ 505 data = (cf->can_id & CAN_SFF_MASK) << 18; 506 hecc_write_mbx(priv, mbxno, HECC_CANMID, data); 507 hecc_write_mbx(priv, mbxno, HECC_CANMDL, 508 be32_to_cpu(*(u32 *)(cf->data))); 509 if (cf->can_dlc > 4) 510 hecc_write_mbx(priv, mbxno, HECC_CANMDH, 511 be32_to_cpu(*(u32 *)(cf->data + 4))); 512 else 513 *(u32 *)(cf->data + 4) = 0; 514 can_put_echo_skb(skb, ndev, mbxno); 515 516 spin_lock_irqsave(&priv->mbx_lock, flags); 517 --priv->tx_head; 518 if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) || 519 (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) { 520 netif_stop_queue(ndev); 521 } 522 hecc_set_bit(priv, HECC_CANME, mbx_mask); 523 spin_unlock_irqrestore(&priv->mbx_lock, flags); 524 525 hecc_clear_bit(priv, HECC_CANMD, mbx_mask); 526 hecc_set_bit(priv, HECC_CANMIM, mbx_mask); 527 hecc_write(priv, HECC_CANTRS, mbx_mask); 528 529 return NETDEV_TX_OK; 530} 531 532static int ti_hecc_rx_pkt(struct ti_hecc_priv *priv, int mbxno) 533{ 534 struct net_device_stats *stats = &priv->ndev->stats; 535 struct can_frame *cf; 536 struct sk_buff *skb; 537 u32 data, mbx_mask; 538 unsigned long flags; 539 540 skb = alloc_can_skb(priv->ndev, &cf); 541 if (!skb) { 542 if (printk_ratelimit()) 543 dev_err(priv->ndev->dev.parent, 544 "ti_hecc_rx_pkt: alloc_can_skb() failed\n"); 545 return -ENOMEM; 546 } 547 548 mbx_mask = BIT(mbxno); 549 data = hecc_read_mbx(priv, mbxno, HECC_CANMID); 550 if (data & HECC_CANMID_IDE) 551 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; 552 else 553 cf->can_id = (data >> 18) & CAN_SFF_MASK; 554 data = hecc_read_mbx(priv, mbxno, HECC_CANMCF); 555 if (data & HECC_CANMCF_RTR) 556 cf->can_id |= CAN_RTR_FLAG; 557 cf->can_dlc = get_can_dlc(data & 0xF); 558 data = hecc_read_mbx(priv, mbxno, HECC_CANMDL); 559 *(u32 *)(cf->data) = cpu_to_be32(data); 560 if (cf->can_dlc > 4) { 561 data = hecc_read_mbx(priv, mbxno, HECC_CANMDH); 562 *(u32 *)(cf->data + 4) = cpu_to_be32(data); 563 } else { 564 *(u32 *)(cf->data + 4) = 0; 565 } 566 spin_lock_irqsave(&priv->mbx_lock, flags); 567 hecc_clear_bit(priv, HECC_CANME, mbx_mask); 568 hecc_write(priv, HECC_CANRMP, mbx_mask); 569 /* enable mailbox only if it is part of rx buffer mailboxes */ 570 if (priv->rx_next < HECC_RX_BUFFER_MBOX) 571 hecc_set_bit(priv, HECC_CANME, mbx_mask); 572 spin_unlock_irqrestore(&priv->mbx_lock, flags); 573 574 stats->rx_bytes += cf->can_dlc; 575 netif_receive_skb(skb); 576 stats->rx_packets++; 577 578 return 0; 579} 580 581/* 582 * ti_hecc_rx_poll - HECC receive pkts 583 * 584 * The receive mailboxes start from highest numbered mailbox till last xmit 585 * mailbox. On CAN frame reception the hardware places the data into highest 586 * numbered mailbox that matches the CAN ID filter. Since all receive mailboxes 587 * have same filtering (ALL CAN frames) packets will arrive in the highest 588 * available RX mailbox and we need to ensure in-order packet reception. 589 * 590 * To ensure the packets are received in the right order we logically divide 591 * the RX mailboxes into main and buffer mailboxes. Packets are received as per 592 * mailbox priotity (higher to lower) in the main bank and once it is full we 593 * disable further reception into main mailboxes. While the main mailboxes are 594 * processed in NAPI, further packets are received in buffer mailboxes. 595 * 596 * We maintain a RX next mailbox counter to process packets and once all main 597 * mailboxe packets are passed to the upper stack we enable all of them but 598 * continue to process packets received in buffer mailboxes. With each packet 599 * received from buffer mailbox we enable it immediately so as to handle the 600 * overflow from higher mailboxes. 601 */ 602static int ti_hecc_rx_poll(struct napi_struct *napi, int quota) 603{ 604 struct net_device *ndev = napi->dev; 605 struct ti_hecc_priv *priv = netdev_priv(ndev); 606 u32 num_pkts = 0; 607 u32 mbx_mask; 608 unsigned long pending_pkts, flags; 609 610 if (!netif_running(ndev)) 611 return 0; 612 613 while ((pending_pkts = hecc_read(priv, HECC_CANRMP)) && 614 num_pkts < quota) { 615 mbx_mask = BIT(priv->rx_next); /* next rx mailbox to process */ 616 if (mbx_mask & pending_pkts) { 617 if (ti_hecc_rx_pkt(priv, priv->rx_next) < 0) 618 return num_pkts; 619 ++num_pkts; 620 } else if (priv->rx_next > HECC_RX_BUFFER_MBOX) { 621 break; /* pkt not received yet */ 622 } 623 --priv->rx_next; 624 if (priv->rx_next == HECC_RX_BUFFER_MBOX) { 625 /* enable high bank mailboxes */ 626 spin_lock_irqsave(&priv->mbx_lock, flags); 627 mbx_mask = hecc_read(priv, HECC_CANME); 628 mbx_mask |= HECC_RX_HIGH_MBOX_MASK; 629 hecc_write(priv, HECC_CANME, mbx_mask); 630 spin_unlock_irqrestore(&priv->mbx_lock, flags); 631 } else if (priv->rx_next == HECC_MAX_TX_MBOX - 1) { 632 priv->rx_next = HECC_RX_FIRST_MBOX; 633 break; 634 } 635 } 636 637 /* Enable packet interrupt if all pkts are handled */ 638 if (hecc_read(priv, HECC_CANRMP) == 0) { 639 napi_complete(napi); 640 /* Re-enable RX mailbox interrupts */ 641 mbx_mask = hecc_read(priv, HECC_CANMIM); 642 mbx_mask |= HECC_TX_MBOX_MASK; 643 hecc_write(priv, HECC_CANMIM, mbx_mask); 644 } 645 646 return num_pkts; 647} 648 649static int ti_hecc_error(struct net_device *ndev, int int_status, 650 int err_status) 651{ 652 struct ti_hecc_priv *priv = netdev_priv(ndev); 653 struct net_device_stats *stats = &ndev->stats; 654 struct can_frame *cf; 655 struct sk_buff *skb; 656 657 /* propogate the error condition to the can stack */ 658 skb = alloc_can_err_skb(ndev, &cf); 659 if (!skb) { 660 if (printk_ratelimit()) 661 dev_err(priv->ndev->dev.parent, 662 "ti_hecc_error: alloc_can_err_skb() failed\n"); 663 return -ENOMEM; 664 } 665 666 if (int_status & HECC_CANGIF_WLIF) { /* warning level int */ 667 if ((int_status & HECC_CANGIF_BOIF) == 0) { 668 priv->can.state = CAN_STATE_ERROR_WARNING; 669 ++priv->can.can_stats.error_warning; 670 cf->can_id |= CAN_ERR_CRTL; 671 if (hecc_read(priv, HECC_CANTEC) > 96) 672 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; 673 if (hecc_read(priv, HECC_CANREC) > 96) 674 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; 675 } 676 hecc_set_bit(priv, HECC_CANES, HECC_CANES_EW); 677 dev_dbg(priv->ndev->dev.parent, "Error Warning interrupt\n"); 678 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); 679 } 680 681 if (int_status & HECC_CANGIF_EPIF) { /* error passive int */ 682 if ((int_status & HECC_CANGIF_BOIF) == 0) { 683 priv->can.state = CAN_STATE_ERROR_PASSIVE; 684 ++priv->can.can_stats.error_passive; 685 cf->can_id |= CAN_ERR_CRTL; 686 if (hecc_read(priv, HECC_CANTEC) > 127) 687 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 688 if (hecc_read(priv, HECC_CANREC) > 127) 689 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 690 } 691 hecc_set_bit(priv, HECC_CANES, HECC_CANES_EP); 692 dev_dbg(priv->ndev->dev.parent, "Error passive interrupt\n"); 693 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); 694 } 695 696 /* 697 * Need to check busoff condition in error status register too to 698 * ensure warning interrupts don't hog the system 699 */ 700 if ((int_status & HECC_CANGIF_BOIF) || (err_status & HECC_CANES_BO)) { 701 priv->can.state = CAN_STATE_BUS_OFF; 702 cf->can_id |= CAN_ERR_BUSOFF; 703 hecc_set_bit(priv, HECC_CANES, HECC_CANES_BO); 704 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); 705 /* Disable all interrupts in bus-off to avoid int hog */ 706 hecc_write(priv, HECC_CANGIM, 0); 707 can_bus_off(ndev); 708 } 709 710 if (err_status & HECC_BUS_ERROR) { 711 ++priv->can.can_stats.bus_error; 712 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 713 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 714 if (err_status & HECC_CANES_FE) { 715 hecc_set_bit(priv, HECC_CANES, HECC_CANES_FE); 716 cf->data[2] |= CAN_ERR_PROT_FORM; 717 } 718 if (err_status & HECC_CANES_BE) { 719 hecc_set_bit(priv, HECC_CANES, HECC_CANES_BE); 720 cf->data[2] |= CAN_ERR_PROT_BIT; 721 } 722 if (err_status & HECC_CANES_SE) { 723 hecc_set_bit(priv, HECC_CANES, HECC_CANES_SE); 724 cf->data[2] |= CAN_ERR_PROT_STUFF; 725 } 726 if (err_status & HECC_CANES_CRCE) { 727 hecc_set_bit(priv, HECC_CANES, HECC_CANES_CRCE); 728 cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ | 729 CAN_ERR_PROT_LOC_CRC_DEL; 730 } 731 if (err_status & HECC_CANES_ACKE) { 732 hecc_set_bit(priv, HECC_CANES, HECC_CANES_ACKE); 733 cf->data[2] |= CAN_ERR_PROT_LOC_ACK | 734 CAN_ERR_PROT_LOC_ACK_DEL; 735 } 736 } 737 738 netif_receive_skb(skb); 739 stats->rx_packets++; 740 stats->rx_bytes += cf->can_dlc; 741 return 0; 742} 743 744static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id) 745{ 746 struct net_device *ndev = (struct net_device *)dev_id; 747 struct ti_hecc_priv *priv = netdev_priv(ndev); 748 struct net_device_stats *stats = &ndev->stats; 749 u32 mbxno, mbx_mask, int_status, err_status; 750 unsigned long ack, flags; 751 752 int_status = hecc_read(priv, 753 (priv->int_line) ? HECC_CANGIF1 : HECC_CANGIF0); 754 755 if (!int_status) 756 return IRQ_NONE; 757 758 err_status = hecc_read(priv, HECC_CANES); 759 if (err_status & (HECC_BUS_ERROR | HECC_CANES_BO | 760 HECC_CANES_EP | HECC_CANES_EW)) 761 ti_hecc_error(ndev, int_status, err_status); 762 763 if (int_status & HECC_CANGIF_GMIF) { 764 while (priv->tx_tail - priv->tx_head > 0) { 765 mbxno = get_tx_tail_mb(priv); 766 mbx_mask = BIT(mbxno); 767 if (!(mbx_mask & hecc_read(priv, HECC_CANTA))) 768 break; 769 hecc_clear_bit(priv, HECC_CANMIM, mbx_mask); 770 hecc_write(priv, HECC_CANTA, mbx_mask); 771 spin_lock_irqsave(&priv->mbx_lock, flags); 772 hecc_clear_bit(priv, HECC_CANME, mbx_mask); 773 spin_unlock_irqrestore(&priv->mbx_lock, flags); 774 stats->tx_bytes += hecc_read_mbx(priv, mbxno, 775 HECC_CANMCF) & 0xF; 776 stats->tx_packets++; 777 can_get_echo_skb(ndev, mbxno); 778 --priv->tx_tail; 779 } 780 781 /* restart queue if wrap-up or if queue stalled on last pkt */ 782 if (((priv->tx_head == priv->tx_tail) && 783 ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) || 784 (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) && 785 ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK))) 786 netif_wake_queue(ndev); 787 788 /* Disable RX mailbox interrupts and let NAPI reenable them */ 789 if (hecc_read(priv, HECC_CANRMP)) { 790 ack = hecc_read(priv, HECC_CANMIM); 791 ack &= BIT(HECC_MAX_TX_MBOX) - 1; 792 hecc_write(priv, HECC_CANMIM, ack); 793 napi_schedule(&priv->napi); 794 } 795 } 796 797 /* clear all interrupt conditions - read back to avoid spurious ints */ 798 if (priv->int_line) { 799 hecc_write(priv, HECC_CANGIF1, HECC_SET_REG); 800 int_status = hecc_read(priv, HECC_CANGIF1); 801 } else { 802 hecc_write(priv, HECC_CANGIF0, HECC_SET_REG); 803 int_status = hecc_read(priv, HECC_CANGIF0); 804 } 805 806 return IRQ_HANDLED; 807} 808 809static int ti_hecc_open(struct net_device *ndev) 810{ 811 struct ti_hecc_priv *priv = netdev_priv(ndev); 812 int err; 813 814 err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED, 815 ndev->name, ndev); 816 if (err) { 817 dev_err(ndev->dev.parent, "error requesting interrupt\n"); 818 return err; 819 } 820 821 /* Open common can device */ 822 err = open_candev(ndev); 823 if (err) { 824 dev_err(ndev->dev.parent, "open_candev() failed %d\n", err); 825 free_irq(ndev->irq, ndev); 826 return err; 827 } 828 829 clk_enable(priv->clk); 830 ti_hecc_start(ndev); 831 napi_enable(&priv->napi); 832 netif_start_queue(ndev); 833 834 return 0; 835} 836 837static int ti_hecc_close(struct net_device *ndev) 838{ 839 struct ti_hecc_priv *priv = netdev_priv(ndev); 840 841 netif_stop_queue(ndev); 842 napi_disable(&priv->napi); 843 ti_hecc_stop(ndev); 844 free_irq(ndev->irq, ndev); 845 clk_disable(priv->clk); 846 close_candev(ndev); 847 848 return 0; 849} 850 851static const struct net_device_ops ti_hecc_netdev_ops = { 852 .ndo_open = ti_hecc_open, 853 .ndo_stop = ti_hecc_close, 854 .ndo_start_xmit = ti_hecc_xmit, 855}; 856 857static int ti_hecc_probe(struct platform_device *pdev) 858{ 859 struct net_device *ndev = (struct net_device *)0; 860 struct ti_hecc_priv *priv; 861 struct ti_hecc_platform_data *pdata; 862 struct resource *mem, *irq; 863 void __iomem *addr; 864 int err = -ENODEV; 865 866 pdata = pdev->dev.platform_data; 867 if (!pdata) { 868 dev_err(&pdev->dev, "No platform data\n"); 869 goto probe_exit; 870 } 871 872 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 873 if (!mem) { 874 dev_err(&pdev->dev, "No mem resources\n"); 875 goto probe_exit; 876 } 877 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 878 if (!irq) { 879 dev_err(&pdev->dev, "No irq resource\n"); 880 goto probe_exit; 881 } 882 if (!request_mem_region(mem->start, resource_size(mem), pdev->name)) { 883 dev_err(&pdev->dev, "HECC region already claimed\n"); 884 err = -EBUSY; 885 goto probe_exit; 886 } 887 addr = ioremap(mem->start, resource_size(mem)); 888 if (!addr) { 889 dev_err(&pdev->dev, "ioremap failed\n"); 890 err = -ENOMEM; 891 goto probe_exit_free_region; 892 } 893 894 ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX); 895 if (!ndev) { 896 dev_err(&pdev->dev, "alloc_candev failed\n"); 897 err = -ENOMEM; 898 goto probe_exit_iounmap; 899 } 900 901 priv = netdev_priv(ndev); 902 priv->ndev = ndev; 903 priv->base = addr; 904 priv->scc_ram_offset = pdata->scc_ram_offset; 905 priv->hecc_ram_offset = pdata->hecc_ram_offset; 906 priv->mbx_offset = pdata->mbx_offset; 907 priv->int_line = pdata->int_line; 908 909 priv->can.bittiming_const = &ti_hecc_bittiming_const; 910 priv->can.do_set_mode = ti_hecc_do_set_mode; 911 priv->can.do_get_state = ti_hecc_get_state; 912 913 ndev->irq = irq->start; 914 ndev->flags |= IFF_ECHO; 915 platform_set_drvdata(pdev, ndev); 916 SET_NETDEV_DEV(ndev, &pdev->dev); 917 ndev->netdev_ops = &ti_hecc_netdev_ops; 918 919 priv->clk = clk_get(&pdev->dev, "hecc_ck"); 920 if (IS_ERR(priv->clk)) { 921 dev_err(&pdev->dev, "No clock available\n"); 922 err = PTR_ERR(priv->clk); 923 priv->clk = NULL; 924 goto probe_exit_candev; 925 } 926 priv->can.clock.freq = clk_get_rate(priv->clk); 927 netif_napi_add(ndev, &priv->napi, ti_hecc_rx_poll, 928 HECC_DEF_NAPI_WEIGHT); 929 930 err = register_candev(ndev); 931 if (err) { 932 dev_err(&pdev->dev, "register_candev() failed\n"); 933 goto probe_exit_clk; 934 } 935 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n", 936 priv->base, (u32) ndev->irq); 937 938 return 0; 939 940probe_exit_clk: 941 clk_put(priv->clk); 942probe_exit_candev: 943 free_candev(ndev); 944probe_exit_iounmap: 945 iounmap(addr); 946probe_exit_free_region: 947 release_mem_region(mem->start, resource_size(mem)); 948probe_exit: 949 return err; 950} 951 952static int __devexit ti_hecc_remove(struct platform_device *pdev) 953{ 954 struct resource *res; 955 struct net_device *ndev = platform_get_drvdata(pdev); 956 struct ti_hecc_priv *priv = netdev_priv(ndev); 957 958 clk_put(priv->clk); 959 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 960 iounmap(priv->base); 961 release_mem_region(res->start, resource_size(res)); 962 unregister_candev(ndev); 963 free_candev(ndev); 964 platform_set_drvdata(pdev, NULL); 965 966 return 0; 967} 968 969/* TI HECC netdevice driver: platform driver structure */ 970static struct platform_driver ti_hecc_driver = { 971 .driver = { 972 .name = DRV_NAME, 973 .owner = THIS_MODULE, 974 }, 975 .probe = ti_hecc_probe, 976 .remove = __devexit_p(ti_hecc_remove), 977}; 978 979static int __init ti_hecc_init_driver(void) 980{ 981 printk(KERN_INFO DRV_DESC "\n"); 982 return platform_driver_register(&ti_hecc_driver); 983} 984module_init(ti_hecc_init_driver); 985 986static void __exit ti_hecc_exit_driver(void) 987{ 988 printk(KERN_INFO DRV_DESC " unloaded\n"); 989 platform_driver_unregister(&ti_hecc_driver); 990} 991module_exit(ti_hecc_exit_driver); 992 993MODULE_AUTHOR("Anant Gole <anantgole@ti.com>"); 994MODULE_LICENSE("GPL v2"); 995MODULE_DESCRIPTION(DRV_DESC); 996