xilinx_can.c revision 92593a035ee6a81f50b54ab34b23b1c1319ee413
1/* Xilinx CAN device driver 2 * 3 * Copyright (C) 2012 - 2014 Xilinx, Inc. 4 * Copyright (C) 2009 PetaLogix. All rights reserved. 5 * 6 * Description: 7 * This driver is developed for Axi CAN IP and for Zynq CANPS Controller. 8 * This program is free software: you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation, either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19#include <linux/clk.h> 20#include <linux/errno.h> 21#include <linux/init.h> 22#include <linux/interrupt.h> 23#include <linux/io.h> 24#include <linux/kernel.h> 25#include <linux/module.h> 26#include <linux/netdevice.h> 27#include <linux/of.h> 28#include <linux/platform_device.h> 29#include <linux/skbuff.h> 30#include <linux/string.h> 31#include <linux/types.h> 32#include <linux/can/dev.h> 33#include <linux/can/error.h> 34#include <linux/can/led.h> 35 36#define DRIVER_NAME "xilinx_can" 37 38/* CAN registers set */ 39enum xcan_reg { 40 XCAN_SRR_OFFSET = 0x00, /* Software reset */ 41 XCAN_MSR_OFFSET = 0x04, /* Mode select */ 42 XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */ 43 XCAN_BTR_OFFSET = 0x0C, /* Bit timing */ 44 XCAN_ECR_OFFSET = 0x10, /* Error counter */ 45 XCAN_ESR_OFFSET = 0x14, /* Error status */ 46 XCAN_SR_OFFSET = 0x18, /* Status */ 47 XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */ 48 XCAN_IER_OFFSET = 0x20, /* Interrupt enable */ 49 XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */ 50 XCAN_TXFIFO_ID_OFFSET = 0x30,/* TX FIFO ID */ 51 XCAN_TXFIFO_DLC_OFFSET = 0x34, /* TX FIFO DLC */ 52 XCAN_TXFIFO_DW1_OFFSET = 0x38, /* TX FIFO Data Word 1 */ 53 XCAN_TXFIFO_DW2_OFFSET = 0x3C, /* TX FIFO Data Word 2 */ 54 XCAN_RXFIFO_ID_OFFSET = 0x50, /* RX FIFO ID */ 55 XCAN_RXFIFO_DLC_OFFSET = 0x54, /* RX FIFO DLC */ 56 XCAN_RXFIFO_DW1_OFFSET = 0x58, /* RX FIFO Data Word 1 */ 57 XCAN_RXFIFO_DW2_OFFSET = 0x5C, /* RX FIFO Data Word 2 */ 58}; 59 60/* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */ 61#define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */ 62#define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */ 63#define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */ 64#define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */ 65#define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */ 66#define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */ 67#define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */ 68#define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */ 69#define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */ 70#define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */ 71#define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */ 72#define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */ 73#define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */ 74#define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */ 75#define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */ 76#define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */ 77#define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */ 78#define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */ 79#define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */ 80#define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */ 81#define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */ 82#define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */ 83#define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */ 84#define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */ 85#define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */ 86#define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */ 87#define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */ 88#define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */ 89#define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */ 90#define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */ 91#define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */ 92#define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */ 93#define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */ 94#define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */ 95#define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */ 96#define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */ 97#define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */ 98#define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */ 99 100#define XCAN_INTR_ALL (XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |\ 101 XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | \ 102 XCAN_IXR_RXNEMP_MASK | XCAN_IXR_ERROR_MASK | \ 103 XCAN_IXR_ARBLST_MASK | XCAN_IXR_RXOK_MASK) 104 105/* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */ 106#define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */ 107#define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */ 108#define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */ 109#define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */ 110#define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */ 111#define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */ 112 113/* CAN frame length constants */ 114#define XCAN_FRAME_MAX_DATA_LEN 8 115#define XCAN_TIMEOUT (1 * HZ) 116 117/** 118 * struct xcan_priv - This definition define CAN driver instance 119 * @can: CAN private data structure. 120 * @tx_head: Tx CAN packets ready to send on the queue 121 * @tx_tail: Tx CAN packets successfully sended on the queue 122 * @tx_max: Maximum number packets the driver can send 123 * @napi: NAPI structure 124 * @read_reg: For reading data from CAN registers 125 * @write_reg: For writing data to CAN registers 126 * @dev: Network device data structure 127 * @reg_base: Ioremapped address to registers 128 * @irq_flags: For request_irq() 129 * @bus_clk: Pointer to struct clk 130 * @can_clk: Pointer to struct clk 131 */ 132struct xcan_priv { 133 struct can_priv can; 134 unsigned int tx_head; 135 unsigned int tx_tail; 136 unsigned int tx_max; 137 struct napi_struct napi; 138 u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg); 139 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg, 140 u32 val); 141 struct net_device *dev; 142 void __iomem *reg_base; 143 unsigned long irq_flags; 144 struct clk *bus_clk; 145 struct clk *can_clk; 146}; 147 148/* CAN Bittiming constants as per Xilinx CAN specs */ 149static const struct can_bittiming_const xcan_bittiming_const = { 150 .name = DRIVER_NAME, 151 .tseg1_min = 1, 152 .tseg1_max = 16, 153 .tseg2_min = 1, 154 .tseg2_max = 8, 155 .sjw_max = 4, 156 .brp_min = 1, 157 .brp_max = 256, 158 .brp_inc = 1, 159}; 160 161/** 162 * xcan_write_reg_le - Write a value to the device register little endian 163 * @priv: Driver private data structure 164 * @reg: Register offset 165 * @val: Value to write at the Register offset 166 * 167 * Write data to the paricular CAN register 168 */ 169static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg, 170 u32 val) 171{ 172 iowrite32(val, priv->reg_base + reg); 173} 174 175/** 176 * xcan_read_reg_le - Read a value from the device register little endian 177 * @priv: Driver private data structure 178 * @reg: Register offset 179 * 180 * Read data from the particular CAN register 181 * Return: value read from the CAN register 182 */ 183static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg) 184{ 185 return ioread32(priv->reg_base + reg); 186} 187 188/** 189 * xcan_write_reg_be - Write a value to the device register big endian 190 * @priv: Driver private data structure 191 * @reg: Register offset 192 * @val: Value to write at the Register offset 193 * 194 * Write data to the paricular CAN register 195 */ 196static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg, 197 u32 val) 198{ 199 iowrite32be(val, priv->reg_base + reg); 200} 201 202/** 203 * xcan_read_reg_be - Read a value from the device register big endian 204 * @priv: Driver private data structure 205 * @reg: Register offset 206 * 207 * Read data from the particular CAN register 208 * Return: value read from the CAN register 209 */ 210static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg) 211{ 212 return ioread32be(priv->reg_base + reg); 213} 214 215/** 216 * set_reset_mode - Resets the CAN device mode 217 * @ndev: Pointer to net_device structure 218 * 219 * This is the driver reset mode routine.The driver 220 * enters into configuration mode. 221 * 222 * Return: 0 on success and failure value on error 223 */ 224static int set_reset_mode(struct net_device *ndev) 225{ 226 struct xcan_priv *priv = netdev_priv(ndev); 227 unsigned long timeout; 228 229 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); 230 231 timeout = jiffies + XCAN_TIMEOUT; 232 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) { 233 if (time_after(jiffies, timeout)) { 234 netdev_warn(ndev, "timed out for config mode\n"); 235 return -ETIMEDOUT; 236 } 237 usleep_range(500, 10000); 238 } 239 240 return 0; 241} 242 243/** 244 * xcan_set_bittiming - CAN set bit timing routine 245 * @ndev: Pointer to net_device structure 246 * 247 * This is the driver set bittiming routine. 248 * Return: 0 on success and failure value on error 249 */ 250static int xcan_set_bittiming(struct net_device *ndev) 251{ 252 struct xcan_priv *priv = netdev_priv(ndev); 253 struct can_bittiming *bt = &priv->can.bittiming; 254 u32 btr0, btr1; 255 u32 is_config_mode; 256 257 /* Check whether Xilinx CAN is in configuration mode. 258 * It cannot set bit timing if Xilinx CAN is not in configuration mode. 259 */ 260 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) & 261 XCAN_SR_CONFIG_MASK; 262 if (!is_config_mode) { 263 netdev_alert(ndev, 264 "BUG! Cannot set bittiming - CAN is not in config mode\n"); 265 return -EPERM; 266 } 267 268 /* Setting Baud Rate prescalar value in BRPR Register */ 269 btr0 = (bt->brp - 1); 270 271 /* Setting Time Segment 1 in BTR Register */ 272 btr1 = (bt->prop_seg + bt->phase_seg1 - 1); 273 274 /* Setting Time Segment 2 in BTR Register */ 275 btr1 |= (bt->phase_seg2 - 1) << XCAN_BTR_TS2_SHIFT; 276 277 /* Setting Synchronous jump width in BTR Register */ 278 btr1 |= (bt->sjw - 1) << XCAN_BTR_SJW_SHIFT; 279 280 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0); 281 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1); 282 283 netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n", 284 priv->read_reg(priv, XCAN_BRPR_OFFSET), 285 priv->read_reg(priv, XCAN_BTR_OFFSET)); 286 287 return 0; 288} 289 290/** 291 * xcan_chip_start - This the drivers start routine 292 * @ndev: Pointer to net_device structure 293 * 294 * This is the drivers start routine. 295 * Based on the State of the CAN device it puts 296 * the CAN device into a proper mode. 297 * 298 * Return: 0 on success and failure value on error 299 */ 300static int xcan_chip_start(struct net_device *ndev) 301{ 302 struct xcan_priv *priv = netdev_priv(ndev); 303 u32 reg_msr, reg_sr_mask; 304 int err; 305 unsigned long timeout; 306 307 /* Check if it is in reset mode */ 308 err = set_reset_mode(ndev); 309 if (err < 0) 310 return err; 311 312 err = xcan_set_bittiming(ndev); 313 if (err < 0) 314 return err; 315 316 /* Enable interrupts */ 317 priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL); 318 319 /* Check whether it is loopback mode or normal mode */ 320 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 321 reg_msr = XCAN_MSR_LBACK_MASK; 322 reg_sr_mask = XCAN_SR_LBACK_MASK; 323 } else { 324 reg_msr = 0x0; 325 reg_sr_mask = XCAN_SR_NORMAL_MASK; 326 } 327 328 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr); 329 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); 330 331 timeout = jiffies + XCAN_TIMEOUT; 332 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) { 333 if (time_after(jiffies, timeout)) { 334 netdev_warn(ndev, 335 "timed out for correct mode\n"); 336 return -ETIMEDOUT; 337 } 338 } 339 netdev_dbg(ndev, "status:#x%08x\n", 340 priv->read_reg(priv, XCAN_SR_OFFSET)); 341 342 priv->can.state = CAN_STATE_ERROR_ACTIVE; 343 return 0; 344} 345 346/** 347 * xcan_do_set_mode - This sets the mode of the driver 348 * @ndev: Pointer to net_device structure 349 * @mode: Tells the mode of the driver 350 * 351 * This check the drivers state and calls the 352 * the corresponding modes to set. 353 * 354 * Return: 0 on success and failure value on error 355 */ 356static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode) 357{ 358 int ret; 359 360 switch (mode) { 361 case CAN_MODE_START: 362 ret = xcan_chip_start(ndev); 363 if (ret < 0) { 364 netdev_err(ndev, "xcan_chip_start failed!\n"); 365 return ret; 366 } 367 netif_wake_queue(ndev); 368 break; 369 default: 370 ret = -EOPNOTSUPP; 371 break; 372 } 373 374 return ret; 375} 376 377/** 378 * xcan_start_xmit - Starts the transmission 379 * @skb: sk_buff pointer that contains data to be Txed 380 * @ndev: Pointer to net_device structure 381 * 382 * This function is invoked from upper layers to initiate transmission. This 383 * function uses the next available free txbuff and populates their fields to 384 * start the transmission. 385 * 386 * Return: 0 on success and failure value on error 387 */ 388static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev) 389{ 390 struct xcan_priv *priv = netdev_priv(ndev); 391 struct net_device_stats *stats = &ndev->stats; 392 struct can_frame *cf = (struct can_frame *)skb->data; 393 u32 id, dlc, data[2] = {0, 0}; 394 395 if (can_dropped_invalid_skb(ndev, skb)) 396 return NETDEV_TX_OK; 397 398 /* Check if the TX buffer is full */ 399 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) & 400 XCAN_SR_TXFLL_MASK)) { 401 netif_stop_queue(ndev); 402 netdev_err(ndev, "BUG!, TX FIFO full when queue awake!\n"); 403 return NETDEV_TX_BUSY; 404 } 405 406 /* Watch carefully on the bit sequence */ 407 if (cf->can_id & CAN_EFF_FLAG) { 408 /* Extended CAN ID format */ 409 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) & 410 XCAN_IDR_ID2_MASK; 411 id |= (((cf->can_id & CAN_EFF_MASK) >> 412 (CAN_EFF_ID_BITS-CAN_SFF_ID_BITS)) << 413 XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK; 414 415 /* The substibute remote TX request bit should be "1" 416 * for extended frames as in the Xilinx CAN datasheet 417 */ 418 id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK; 419 420 if (cf->can_id & CAN_RTR_FLAG) 421 /* Extended frames remote TX request */ 422 id |= XCAN_IDR_RTR_MASK; 423 } else { 424 /* Standard CAN ID format */ 425 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) & 426 XCAN_IDR_ID1_MASK; 427 428 if (cf->can_id & CAN_RTR_FLAG) 429 /* Standard frames remote TX request */ 430 id |= XCAN_IDR_SRR_MASK; 431 } 432 433 dlc = cf->can_dlc << XCAN_DLCR_DLC_SHIFT; 434 435 if (cf->can_dlc > 0) 436 data[0] = be32_to_cpup((__be32 *)(cf->data + 0)); 437 if (cf->can_dlc > 4) 438 data[1] = be32_to_cpup((__be32 *)(cf->data + 4)); 439 440 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max); 441 priv->tx_head++; 442 443 /* Write the Frame to Xilinx CAN TX FIFO */ 444 priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id); 445 /* If the CAN frame is RTR frame this write triggers tranmission */ 446 priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc); 447 if (!(cf->can_id & CAN_RTR_FLAG)) { 448 priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]); 449 /* If the CAN frame is Standard/Extended frame this 450 * write triggers tranmission 451 */ 452 priv->write_reg(priv, XCAN_TXFIFO_DW2_OFFSET, data[1]); 453 stats->tx_bytes += cf->can_dlc; 454 } 455 456 /* Check if the TX buffer is full */ 457 if ((priv->tx_head - priv->tx_tail) == priv->tx_max) 458 netif_stop_queue(ndev); 459 460 return NETDEV_TX_OK; 461} 462 463/** 464 * xcan_rx - Is called from CAN isr to complete the received 465 * frame processing 466 * @ndev: Pointer to net_device structure 467 * 468 * This function is invoked from the CAN isr(poll) to process the Rx frames. It 469 * does minimal processing and invokes "netif_receive_skb" to complete further 470 * processing. 471 * Return: 1 on success and 0 on failure. 472 */ 473static int xcan_rx(struct net_device *ndev) 474{ 475 struct xcan_priv *priv = netdev_priv(ndev); 476 struct net_device_stats *stats = &ndev->stats; 477 struct can_frame *cf; 478 struct sk_buff *skb; 479 u32 id_xcan, dlc, data[2] = {0, 0}; 480 481 skb = alloc_can_skb(ndev, &cf); 482 if (unlikely(!skb)) { 483 stats->rx_dropped++; 484 return 0; 485 } 486 487 /* Read a frame from Xilinx zynq CANPS */ 488 id_xcan = priv->read_reg(priv, XCAN_RXFIFO_ID_OFFSET); 489 dlc = priv->read_reg(priv, XCAN_RXFIFO_DLC_OFFSET) >> 490 XCAN_DLCR_DLC_SHIFT; 491 492 /* Change Xilinx CAN data length format to socketCAN data format */ 493 cf->can_dlc = get_can_dlc(dlc); 494 495 /* Change Xilinx CAN ID format to socketCAN ID format */ 496 if (id_xcan & XCAN_IDR_IDE_MASK) { 497 /* The received frame is an Extended format frame */ 498 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; 499 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> 500 XCAN_IDR_ID2_SHIFT; 501 cf->can_id |= CAN_EFF_FLAG; 502 if (id_xcan & XCAN_IDR_RTR_MASK) 503 cf->can_id |= CAN_RTR_FLAG; 504 } else { 505 /* The received frame is a standard format frame */ 506 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 507 XCAN_IDR_ID1_SHIFT; 508 if (id_xcan & XCAN_IDR_SRR_MASK) 509 cf->can_id |= CAN_RTR_FLAG; 510 } 511 512 if (!(id_xcan & XCAN_IDR_SRR_MASK)) { 513 data[0] = priv->read_reg(priv, XCAN_RXFIFO_DW1_OFFSET); 514 data[1] = priv->read_reg(priv, XCAN_RXFIFO_DW2_OFFSET); 515 516 /* Change Xilinx CAN data format to socketCAN data format */ 517 if (cf->can_dlc > 0) 518 *(__be32 *)(cf->data) = cpu_to_be32(data[0]); 519 if (cf->can_dlc > 4) 520 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]); 521 } 522 523 stats->rx_bytes += cf->can_dlc; 524 stats->rx_packets++; 525 netif_receive_skb(skb); 526 527 return 1; 528} 529 530/** 531 * xcan_err_interrupt - error frame Isr 532 * @ndev: net_device pointer 533 * @isr: interrupt status register value 534 * 535 * This is the CAN error interrupt and it will 536 * check the the type of error and forward the error 537 * frame to upper layers. 538 */ 539static void xcan_err_interrupt(struct net_device *ndev, u32 isr) 540{ 541 struct xcan_priv *priv = netdev_priv(ndev); 542 struct net_device_stats *stats = &ndev->stats; 543 struct can_frame *cf; 544 struct sk_buff *skb; 545 u32 err_status, status, txerr = 0, rxerr = 0; 546 547 skb = alloc_can_err_skb(ndev, &cf); 548 549 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET); 550 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status); 551 txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK; 552 rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) & 553 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT); 554 status = priv->read_reg(priv, XCAN_SR_OFFSET); 555 556 if (isr & XCAN_IXR_BSOFF_MASK) { 557 priv->can.state = CAN_STATE_BUS_OFF; 558 priv->can.can_stats.bus_off++; 559 /* Leave device in Config Mode in bus-off state */ 560 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); 561 can_bus_off(ndev); 562 if (skb) 563 cf->can_id |= CAN_ERR_BUSOFF; 564 } else if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK) { 565 priv->can.state = CAN_STATE_ERROR_PASSIVE; 566 priv->can.can_stats.error_passive++; 567 if (skb) { 568 cf->can_id |= CAN_ERR_CRTL; 569 cf->data[1] = (rxerr > 127) ? 570 CAN_ERR_CRTL_RX_PASSIVE : 571 CAN_ERR_CRTL_TX_PASSIVE; 572 cf->data[6] = txerr; 573 cf->data[7] = rxerr; 574 } 575 } else if (status & XCAN_SR_ERRWRN_MASK) { 576 priv->can.state = CAN_STATE_ERROR_WARNING; 577 priv->can.can_stats.error_warning++; 578 if (skb) { 579 cf->can_id |= CAN_ERR_CRTL; 580 cf->data[1] |= (txerr > rxerr) ? 581 CAN_ERR_CRTL_TX_WARNING : 582 CAN_ERR_CRTL_RX_WARNING; 583 cf->data[6] = txerr; 584 cf->data[7] = rxerr; 585 } 586 } 587 588 /* Check for Arbitration lost interrupt */ 589 if (isr & XCAN_IXR_ARBLST_MASK) { 590 priv->can.can_stats.arbitration_lost++; 591 if (skb) { 592 cf->can_id |= CAN_ERR_LOSTARB; 593 cf->data[0] = CAN_ERR_LOSTARB_UNSPEC; 594 } 595 } 596 597 /* Check for RX FIFO Overflow interrupt */ 598 if (isr & XCAN_IXR_RXOFLW_MASK) { 599 stats->rx_over_errors++; 600 stats->rx_errors++; 601 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); 602 if (skb) { 603 cf->can_id |= CAN_ERR_CRTL; 604 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; 605 } 606 } 607 608 /* Check for error interrupt */ 609 if (isr & XCAN_IXR_ERROR_MASK) { 610 if (skb) { 611 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 612 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 613 } 614 615 /* Check for Ack error interrupt */ 616 if (err_status & XCAN_ESR_ACKER_MASK) { 617 stats->tx_errors++; 618 if (skb) { 619 cf->can_id |= CAN_ERR_ACK; 620 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 621 } 622 } 623 624 /* Check for Bit error interrupt */ 625 if (err_status & XCAN_ESR_BERR_MASK) { 626 stats->tx_errors++; 627 if (skb) { 628 cf->can_id |= CAN_ERR_PROT; 629 cf->data[2] = CAN_ERR_PROT_BIT; 630 } 631 } 632 633 /* Check for Stuff error interrupt */ 634 if (err_status & XCAN_ESR_STER_MASK) { 635 stats->rx_errors++; 636 if (skb) { 637 cf->can_id |= CAN_ERR_PROT; 638 cf->data[2] = CAN_ERR_PROT_STUFF; 639 } 640 } 641 642 /* Check for Form error interrupt */ 643 if (err_status & XCAN_ESR_FMER_MASK) { 644 stats->rx_errors++; 645 if (skb) { 646 cf->can_id |= CAN_ERR_PROT; 647 cf->data[2] = CAN_ERR_PROT_FORM; 648 } 649 } 650 651 /* Check for CRC error interrupt */ 652 if (err_status & XCAN_ESR_CRCER_MASK) { 653 stats->rx_errors++; 654 if (skb) { 655 cf->can_id |= CAN_ERR_PROT; 656 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ | 657 CAN_ERR_PROT_LOC_CRC_DEL; 658 } 659 } 660 priv->can.can_stats.bus_error++; 661 } 662 663 if (skb) { 664 stats->rx_packets++; 665 stats->rx_bytes += cf->can_dlc; 666 netif_rx(skb); 667 } 668 669 netdev_dbg(ndev, "%s: error status register:0x%x\n", 670 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET)); 671} 672 673/** 674 * xcan_state_interrupt - It will check the state of the CAN device 675 * @ndev: net_device pointer 676 * @isr: interrupt status register value 677 * 678 * This will checks the state of the CAN device 679 * and puts the device into appropriate state. 680 */ 681static void xcan_state_interrupt(struct net_device *ndev, u32 isr) 682{ 683 struct xcan_priv *priv = netdev_priv(ndev); 684 685 /* Check for Sleep interrupt if set put CAN device in sleep state */ 686 if (isr & XCAN_IXR_SLP_MASK) 687 priv->can.state = CAN_STATE_SLEEPING; 688 689 /* Check for Wake up interrupt if set put CAN device in Active state */ 690 if (isr & XCAN_IXR_WKUP_MASK) 691 priv->can.state = CAN_STATE_ERROR_ACTIVE; 692} 693 694/** 695 * xcan_rx_poll - Poll routine for rx packets (NAPI) 696 * @napi: napi structure pointer 697 * @quota: Max number of rx packets to be processed. 698 * 699 * This is the poll routine for rx part. 700 * It will process the packets maximux quota value. 701 * 702 * Return: number of packets received 703 */ 704static int xcan_rx_poll(struct napi_struct *napi, int quota) 705{ 706 struct net_device *ndev = napi->dev; 707 struct xcan_priv *priv = netdev_priv(ndev); 708 u32 isr, ier; 709 int work_done = 0; 710 711 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); 712 while ((isr & XCAN_IXR_RXNEMP_MASK) && (work_done < quota)) { 713 if (isr & XCAN_IXR_RXOK_MASK) { 714 priv->write_reg(priv, XCAN_ICR_OFFSET, 715 XCAN_IXR_RXOK_MASK); 716 work_done += xcan_rx(ndev); 717 } else { 718 priv->write_reg(priv, XCAN_ICR_OFFSET, 719 XCAN_IXR_RXNEMP_MASK); 720 break; 721 } 722 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXNEMP_MASK); 723 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); 724 } 725 726 if (work_done) 727 can_led_event(ndev, CAN_LED_EVENT_RX); 728 729 if (work_done < quota) { 730 napi_complete(napi); 731 ier = priv->read_reg(priv, XCAN_IER_OFFSET); 732 ier |= (XCAN_IXR_RXOK_MASK | XCAN_IXR_RXNEMP_MASK); 733 priv->write_reg(priv, XCAN_IER_OFFSET, ier); 734 } 735 return work_done; 736} 737 738/** 739 * xcan_tx_interrupt - Tx Done Isr 740 * @ndev: net_device pointer 741 * @isr: Interrupt status register value 742 */ 743static void xcan_tx_interrupt(struct net_device *ndev, u32 isr) 744{ 745 struct xcan_priv *priv = netdev_priv(ndev); 746 struct net_device_stats *stats = &ndev->stats; 747 748 while ((priv->tx_head - priv->tx_tail > 0) && 749 (isr & XCAN_IXR_TXOK_MASK)) { 750 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); 751 can_get_echo_skb(ndev, priv->tx_tail % 752 priv->tx_max); 753 priv->tx_tail++; 754 stats->tx_packets++; 755 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); 756 } 757 can_led_event(ndev, CAN_LED_EVENT_TX); 758 netif_wake_queue(ndev); 759} 760 761/** 762 * xcan_interrupt - CAN Isr 763 * @irq: irq number 764 * @dev_id: device id poniter 765 * 766 * This is the xilinx CAN Isr. It checks for the type of interrupt 767 * and invokes the corresponding ISR. 768 * 769 * Return: 770 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise 771 */ 772static irqreturn_t xcan_interrupt(int irq, void *dev_id) 773{ 774 struct net_device *ndev = (struct net_device *)dev_id; 775 struct xcan_priv *priv = netdev_priv(ndev); 776 u32 isr, ier; 777 778 /* Get the interrupt status from Xilinx CAN */ 779 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); 780 if (!isr) 781 return IRQ_NONE; 782 783 /* Check for the type of interrupt and Processing it */ 784 if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) { 785 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK | 786 XCAN_IXR_WKUP_MASK)); 787 xcan_state_interrupt(ndev, isr); 788 } 789 790 /* Check for Tx interrupt and Processing it */ 791 if (isr & XCAN_IXR_TXOK_MASK) 792 xcan_tx_interrupt(ndev, isr); 793 794 /* Check for the type of error interrupt and Processing it */ 795 if (isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | 796 XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK)) { 797 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_ERROR_MASK | 798 XCAN_IXR_RXOFLW_MASK | XCAN_IXR_BSOFF_MASK | 799 XCAN_IXR_ARBLST_MASK)); 800 xcan_err_interrupt(ndev, isr); 801 } 802 803 /* Check for the type of receive interrupt and Processing it */ 804 if (isr & (XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK)) { 805 ier = priv->read_reg(priv, XCAN_IER_OFFSET); 806 ier &= ~(XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK); 807 priv->write_reg(priv, XCAN_IER_OFFSET, ier); 808 napi_schedule(&priv->napi); 809 } 810 return IRQ_HANDLED; 811} 812 813/** 814 * xcan_chip_stop - Driver stop routine 815 * @ndev: Pointer to net_device structure 816 * 817 * This is the drivers stop routine. It will disable the 818 * interrupts and put the device into configuration mode. 819 */ 820static void xcan_chip_stop(struct net_device *ndev) 821{ 822 struct xcan_priv *priv = netdev_priv(ndev); 823 u32 ier; 824 825 /* Disable interrupts and leave the can in configuration mode */ 826 ier = priv->read_reg(priv, XCAN_IER_OFFSET); 827 ier &= ~XCAN_INTR_ALL; 828 priv->write_reg(priv, XCAN_IER_OFFSET, ier); 829 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); 830 priv->can.state = CAN_STATE_STOPPED; 831} 832 833/** 834 * xcan_open - Driver open routine 835 * @ndev: Pointer to net_device structure 836 * 837 * This is the driver open routine. 838 * Return: 0 on success and failure value on error 839 */ 840static int xcan_open(struct net_device *ndev) 841{ 842 struct xcan_priv *priv = netdev_priv(ndev); 843 int ret; 844 845 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags, 846 ndev->name, ndev); 847 if (ret < 0) { 848 netdev_err(ndev, "irq allocation for CAN failed\n"); 849 goto err; 850 } 851 852 ret = clk_prepare_enable(priv->can_clk); 853 if (ret) { 854 netdev_err(ndev, "unable to enable device clock\n"); 855 goto err_irq; 856 } 857 858 ret = clk_prepare_enable(priv->bus_clk); 859 if (ret) { 860 netdev_err(ndev, "unable to enable bus clock\n"); 861 goto err_can_clk; 862 } 863 864 /* Set chip into reset mode */ 865 ret = set_reset_mode(ndev); 866 if (ret < 0) { 867 netdev_err(ndev, "mode resetting failed!\n"); 868 goto err_bus_clk; 869 } 870 871 /* Common open */ 872 ret = open_candev(ndev); 873 if (ret) 874 goto err_bus_clk; 875 876 ret = xcan_chip_start(ndev); 877 if (ret < 0) { 878 netdev_err(ndev, "xcan_chip_start failed!\n"); 879 goto err_candev; 880 } 881 882 can_led_event(ndev, CAN_LED_EVENT_OPEN); 883 napi_enable(&priv->napi); 884 netif_start_queue(ndev); 885 886 return 0; 887 888err_candev: 889 close_candev(ndev); 890err_bus_clk: 891 clk_disable_unprepare(priv->bus_clk); 892err_can_clk: 893 clk_disable_unprepare(priv->can_clk); 894err_irq: 895 free_irq(ndev->irq, ndev); 896err: 897 return ret; 898} 899 900/** 901 * xcan_close - Driver close routine 902 * @ndev: Pointer to net_device structure 903 * 904 * Return: 0 always 905 */ 906static int xcan_close(struct net_device *ndev) 907{ 908 struct xcan_priv *priv = netdev_priv(ndev); 909 910 netif_stop_queue(ndev); 911 napi_disable(&priv->napi); 912 xcan_chip_stop(ndev); 913 clk_disable_unprepare(priv->bus_clk); 914 clk_disable_unprepare(priv->can_clk); 915 free_irq(ndev->irq, ndev); 916 close_candev(ndev); 917 918 can_led_event(ndev, CAN_LED_EVENT_STOP); 919 920 return 0; 921} 922 923/** 924 * xcan_get_berr_counter - error counter routine 925 * @ndev: Pointer to net_device structure 926 * @bec: Pointer to can_berr_counter structure 927 * 928 * This is the driver error counter routine. 929 * Return: 0 on success and failure value on error 930 */ 931static int xcan_get_berr_counter(const struct net_device *ndev, 932 struct can_berr_counter *bec) 933{ 934 struct xcan_priv *priv = netdev_priv(ndev); 935 int ret; 936 937 ret = clk_prepare_enable(priv->can_clk); 938 if (ret) 939 goto err; 940 941 ret = clk_prepare_enable(priv->bus_clk); 942 if (ret) 943 goto err_clk; 944 945 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK; 946 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) & 947 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT); 948 949 clk_disable_unprepare(priv->bus_clk); 950 clk_disable_unprepare(priv->can_clk); 951 952 return 0; 953 954err_clk: 955 clk_disable_unprepare(priv->can_clk); 956err: 957 return ret; 958} 959 960 961static const struct net_device_ops xcan_netdev_ops = { 962 .ndo_open = xcan_open, 963 .ndo_stop = xcan_close, 964 .ndo_start_xmit = xcan_start_xmit, 965 .ndo_change_mtu = can_change_mtu, 966}; 967 968/** 969 * xcan_suspend - Suspend method for the driver 970 * @dev: Address of the platform_device structure 971 * 972 * Put the driver into low power mode. 973 * Return: 0 always 974 */ 975static int __maybe_unused xcan_suspend(struct device *dev) 976{ 977 struct platform_device *pdev = dev_get_drvdata(dev); 978 struct net_device *ndev = platform_get_drvdata(pdev); 979 struct xcan_priv *priv = netdev_priv(ndev); 980 981 if (netif_running(ndev)) { 982 netif_stop_queue(ndev); 983 netif_device_detach(ndev); 984 } 985 986 priv->write_reg(priv, XCAN_MSR_OFFSET, XCAN_MSR_SLEEP_MASK); 987 priv->can.state = CAN_STATE_SLEEPING; 988 989 clk_disable(priv->bus_clk); 990 clk_disable(priv->can_clk); 991 992 return 0; 993} 994 995/** 996 * xcan_resume - Resume from suspend 997 * @dev: Address of the platformdevice structure 998 * 999 * Resume operation after suspend. 1000 * Return: 0 on success and failure value on error 1001 */ 1002static int __maybe_unused xcan_resume(struct device *dev) 1003{ 1004 struct platform_device *pdev = dev_get_drvdata(dev); 1005 struct net_device *ndev = platform_get_drvdata(pdev); 1006 struct xcan_priv *priv = netdev_priv(ndev); 1007 int ret; 1008 1009 ret = clk_enable(priv->bus_clk); 1010 if (ret) { 1011 dev_err(dev, "Cannot enable clock.\n"); 1012 return ret; 1013 } 1014 ret = clk_enable(priv->can_clk); 1015 if (ret) { 1016 dev_err(dev, "Cannot enable clock.\n"); 1017 clk_disable_unprepare(priv->bus_clk); 1018 return ret; 1019 } 1020 1021 priv->write_reg(priv, XCAN_MSR_OFFSET, 0); 1022 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); 1023 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1024 1025 if (netif_running(ndev)) { 1026 netif_device_attach(ndev); 1027 netif_start_queue(ndev); 1028 } 1029 1030 return 0; 1031} 1032 1033static SIMPLE_DEV_PM_OPS(xcan_dev_pm_ops, xcan_suspend, xcan_resume); 1034 1035/** 1036 * xcan_probe - Platform registration call 1037 * @pdev: Handle to the platform device structure 1038 * 1039 * This function does all the memory allocation and registration for the CAN 1040 * device. 1041 * 1042 * Return: 0 on success and failure value on error 1043 */ 1044static int xcan_probe(struct platform_device *pdev) 1045{ 1046 struct resource *res; /* IO mem resources */ 1047 struct net_device *ndev; 1048 struct xcan_priv *priv; 1049 void __iomem *addr; 1050 int ret, rx_max, tx_max; 1051 1052 /* Get the virtual base address for the device */ 1053 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1054 addr = devm_ioremap_resource(&pdev->dev, res); 1055 if (IS_ERR(addr)) { 1056 ret = PTR_ERR(addr); 1057 goto err; 1058 } 1059 1060 ret = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth", &tx_max); 1061 if (ret < 0) 1062 goto err; 1063 1064 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", &rx_max); 1065 if (ret < 0) 1066 goto err; 1067 1068 /* Create a CAN device instance */ 1069 ndev = alloc_candev(sizeof(struct xcan_priv), tx_max); 1070 if (!ndev) 1071 return -ENOMEM; 1072 1073 priv = netdev_priv(ndev); 1074 priv->dev = ndev; 1075 priv->can.bittiming_const = &xcan_bittiming_const; 1076 priv->can.do_set_mode = xcan_do_set_mode; 1077 priv->can.do_get_berr_counter = xcan_get_berr_counter; 1078 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1079 CAN_CTRLMODE_BERR_REPORTING; 1080 priv->reg_base = addr; 1081 priv->tx_max = tx_max; 1082 1083 /* Get IRQ for the device */ 1084 ndev->irq = platform_get_irq(pdev, 0); 1085 ndev->flags |= IFF_ECHO; /* We support local echo */ 1086 1087 platform_set_drvdata(pdev, ndev); 1088 SET_NETDEV_DEV(ndev, &pdev->dev); 1089 ndev->netdev_ops = &xcan_netdev_ops; 1090 1091 /* Getting the CAN can_clk info */ 1092 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk"); 1093 if (IS_ERR(priv->can_clk)) { 1094 dev_err(&pdev->dev, "Device clock not found.\n"); 1095 ret = PTR_ERR(priv->can_clk); 1096 goto err_free; 1097 } 1098 /* Check for type of CAN device */ 1099 if (of_device_is_compatible(pdev->dev.of_node, 1100 "xlnx,zynq-can-1.0")) { 1101 priv->bus_clk = devm_clk_get(&pdev->dev, "pclk"); 1102 if (IS_ERR(priv->bus_clk)) { 1103 dev_err(&pdev->dev, "bus clock not found\n"); 1104 ret = PTR_ERR(priv->bus_clk); 1105 goto err_free; 1106 } 1107 } else { 1108 priv->bus_clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); 1109 if (IS_ERR(priv->bus_clk)) { 1110 dev_err(&pdev->dev, "bus clock not found\n"); 1111 ret = PTR_ERR(priv->bus_clk); 1112 goto err_free; 1113 } 1114 } 1115 1116 ret = clk_prepare_enable(priv->can_clk); 1117 if (ret) { 1118 dev_err(&pdev->dev, "unable to enable device clock\n"); 1119 goto err_free; 1120 } 1121 1122 ret = clk_prepare_enable(priv->bus_clk); 1123 if (ret) { 1124 dev_err(&pdev->dev, "unable to enable bus clock\n"); 1125 goto err_unprepare_disable_dev; 1126 } 1127 1128 priv->write_reg = xcan_write_reg_le; 1129 priv->read_reg = xcan_read_reg_le; 1130 1131 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) { 1132 priv->write_reg = xcan_write_reg_be; 1133 priv->read_reg = xcan_read_reg_be; 1134 } 1135 1136 priv->can.clock.freq = clk_get_rate(priv->can_clk); 1137 1138 netif_napi_add(ndev, &priv->napi, xcan_rx_poll, rx_max); 1139 1140 ret = register_candev(ndev); 1141 if (ret) { 1142 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret); 1143 goto err_unprepare_disable_busclk; 1144 } 1145 1146 devm_can_led_init(ndev); 1147 clk_disable_unprepare(priv->bus_clk); 1148 clk_disable_unprepare(priv->can_clk); 1149 netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth:%d\n", 1150 priv->reg_base, ndev->irq, priv->can.clock.freq, 1151 priv->tx_max); 1152 1153 return 0; 1154 1155err_unprepare_disable_busclk: 1156 clk_disable_unprepare(priv->bus_clk); 1157err_unprepare_disable_dev: 1158 clk_disable_unprepare(priv->can_clk); 1159err_free: 1160 free_candev(ndev); 1161err: 1162 return ret; 1163} 1164 1165/** 1166 * xcan_remove - Unregister the device after releasing the resources 1167 * @pdev: Handle to the platform device structure 1168 * 1169 * This function frees all the resources allocated to the device. 1170 * Return: 0 always 1171 */ 1172static int xcan_remove(struct platform_device *pdev) 1173{ 1174 struct net_device *ndev = platform_get_drvdata(pdev); 1175 struct xcan_priv *priv = netdev_priv(ndev); 1176 1177 if (set_reset_mode(ndev) < 0) 1178 netdev_err(ndev, "mode resetting failed!\n"); 1179 1180 unregister_candev(ndev); 1181 netif_napi_del(&priv->napi); 1182 free_candev(ndev); 1183 1184 return 0; 1185} 1186 1187/* Match table for OF platform binding */ 1188static struct of_device_id xcan_of_match[] = { 1189 { .compatible = "xlnx,zynq-can-1.0", }, 1190 { .compatible = "xlnx,axi-can-1.00.a", }, 1191 { /* end of list */ }, 1192}; 1193MODULE_DEVICE_TABLE(of, xcan_of_match); 1194 1195static struct platform_driver xcan_driver = { 1196 .probe = xcan_probe, 1197 .remove = xcan_remove, 1198 .driver = { 1199 .owner = THIS_MODULE, 1200 .name = DRIVER_NAME, 1201 .pm = &xcan_dev_pm_ops, 1202 .of_match_table = xcan_of_match, 1203 }, 1204}; 1205 1206module_platform_driver(xcan_driver); 1207 1208MODULE_LICENSE("GPL"); 1209MODULE_AUTHOR("Xilinx Inc"); 1210MODULE_DESCRIPTION("Xilinx CAN interface"); 1211